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* Rename jetson-nano-sd to p3450-porgStephen Warren2019-07-011-6/+6
| | | | | | | | | This matches the downstream L4T U-Boot port, which allows the files generated by tegra-pinmux-scripts to be used directly without editing. The mandate to use name jetson-nano-sd in these scripts has been removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
* Add Jetson Nano Developer Kit (SD) BoardStephen Warren2019-06-171-0/+6
| | | | | | | v1.0 downloaded from the following URL on 2019/06/17: https://developer.nvidia.com/embedded/downloads Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Support board CSV files that obscure informationStephen Warren2019-05-091-2/+4
| | | | | | | Some board spreadsheets specify RSVD<n> for some SoC pinmux options even where the SoC does actually support some "real" option. Enhance the pinmux scripts' error checking not to throw an error when board CSVs and SoC data files don't match, in this one specific case.
* Add Colorado Engineering TK1-SOM boardPeter.Chubb@data61.csiro.au2016-08-301-0/+8
| | | | | | | | The TK1 SOM from Colorado Engineering is a small form-factor board similar to the Jetson TK1. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add the Tegra210-smaug boardRhyland Klein2016-04-071-0/+6
| | | | | | | Tegra210-smaug is the name for the Google Pixel C platform. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add P2371-2180 boardStephen Warren2015-07-301-0/+6
| | | | | | P2371-2180 is a Tegra210 reference board. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add P2371-0000 boardStephen Warren2015-07-241-0/+6
| | | | | | P2371-0000 is a Tegra210 development board. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add E2220-1170 boardStephen Warren2015-07-241-0/+6
| | | | | | | | | | | | | | E2220-1170 is a Tegra210 reference board. The following pins have missing gpio_init_val data in the spreadsheet, and were manually fixed to be out0 per discussion with the systems engineering team: lcd_bl_en_pv1 lcd_rst_pv2 usb_vbus_en1_pcc5 Signed-off-by: Stephen Warren <swarren@nvidia.com>
* csv-to-board: allow 'Ball Name' in an abitrary columnStephen Warren2015-07-211-1/+1
| | | | | | | | | csv-to-board currently parses the header row to find out which column each desired piece of data is located in. However, it checks a hard-coded column to determine which row is the header row. Enhance the script to allow the header row identification data to be in an arbitrary column. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* csv-to-board: handle missing gpio_init_valsStephen Warren2015-07-201-0/+8
| | | | | | | | | | Some board spreadsheets have missing values in the gpio_init_val column. This occurs to handle initialization ordering quirks in downstream SW. Modify csv-to-board to handle such spreadsheets without throwing an error, but warn the user that they need to fix up the resultant config file with valid data. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for P2571 boardStephen Warren2015-06-191-0/+6
| | | | | | P2571 is an NVIDIA reference board for the Tegra210 Soc. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Support for MIPI pad ctrl groups in *.boardStephen Warren2015-03-251-7/+23
| | | | | | | Update csv-to-board.py to extract, and board-to-*.py to emit, configuration for MIPI pad ctrl groups. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* csv-to-board: handle missing package columnsStephen Warren2015-03-251-7/+16
| | | | | | | | Some board spreadsheets may have irrelevant package columns removed, leaving only the package column that the specific board uses. Update csv-to-board to handle missing package columns. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Support Tegra210Stephen Warren2015-02-251-0/+297
Tegra210 changes the pinmux HW in a few ways; at least: - The set of drive groups is much more 1:1 with the set of pins. Most pins have an associated drive group register as well as an associated pinmux register, and most drive groups cover a single pin. - Some register fields have moved from the drive group registers into the pinmux registers. - The set of available options for each pin and group varies relative to previous chips, and hence the register layouts vary a bit too. This patch updates tegra-pinmux-scripts minimally to handle these changes, to a level equivalent to the support for previous chips. For example, some new options such as per-pin schmitt aren't handled since the syseng-supplied pinmux spreadsheets don't provide a value for this option. csv-to-board-tegra124-xlsx.py is renamed to csv-to-board.py since it now supports boards using different SoCs, and it's not worth encoding all supported SoCs in the filename (Tegra30/114 aren't supported by it, hence the previous naming). Signed-off-by: Stephen Warren <swarren@nvidia.com>
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