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author | cliechti <cliechti@f19166aa-fa4f-0410-85c2-fa1106f25c8a> | 2009-07-30 21:36:06 +0000 |
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committer | cliechti <cliechti@f19166aa-fa4f-0410-85c2-fa1106f25c8a> | 2009-07-30 21:36:06 +0000 |
commit | 447b50a6dedb5240dd6ce890b6f5d5323a34d980 (patch) | |
tree | e39d76703aef0e5f6ee244ae421f3f7fe6857940 /pyparallel/parallel/parallelutil.py | |
parent | 3509fba7dc90b3fc6f18687993547af6d4cc398d (diff) | |
download | pyserial-git-release0_2.tar.gz |
- create tag for 2.5-rc1release0_2
- fix name of old 0.2 tag
Diffstat (limited to 'pyparallel/parallel/parallelutil.py')
-rw-r--r-- | pyparallel/parallel/parallelutil.py | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/pyparallel/parallel/parallelutil.py b/pyparallel/parallel/parallelutil.py index 036028e..a1a262a 100644 --- a/pyparallel/parallel/parallelutil.py +++ b/pyparallel/parallel/parallelutil.py @@ -1,15 +1,15 @@ class BitaccessMeta(type): """meta class that adds bit access properties to a parallel port implementation""" - + def __new__(self, classname, bases, classdict): klass = type.__new__(self, classname, bases, classdict) - # status lines + #status lines klass.paperOut = property(klass.getInPaperOut, None, "Read the PaperOut signal") - # control lines + #control lines klass.dataStrobe = property(None, klass.setDataStrobe, "Set the DataStrobe signal") - # XXX ... other bits - # data bits + #XXX ... other bits + #data bits for bit in range(8): mask = (1<<bit) def getter(self, mask=mask): @@ -20,7 +20,7 @@ class BitaccessMeta(type): else: self.setData(self.getData() & ~mask) setattr(klass, "D%d" % bit, property(getter, setter, "Access databit %d" % bit)) - # nibbles + #nibbles for name, shift, width in [('D0_D3', 0, 4), ('D4_D7', 4, 4)]: mask = (1<<width) - 1 def getter(self, shift=shift, mask=mask): @@ -33,34 +33,34 @@ class BitaccessMeta(type): class VirtualParallelPort: """provides a virtual parallel port implementation, useful for tests and simulations without real hardware""" - + __metaclass__ = BitaccessMeta - + def __init__(self, port=None): self._data = 0 - + def setData(self, value): self._data = value def getData(self): return self._data - # inputs return dummy value + #inputs return dummy value def getInPaperOut(self): return self._dummy - # ... - # outputs just store a tuple with (action, value) pair + #... + #outputs just store a tuple with (action, value) pair def setDataStrobe(self, value): self._last = ('setDataStrobe', value) - # ... + #... -# testing +#testing if __name__ == '__main__': import unittest, sys - + class TestBitaccess(unittest.TestCase): """Tests a port with no timeout""" def setUp(self): self.p = VirtualParallelPort() - + def testDatabits(self): """bit by bit D0..D7""" p = self.p @@ -75,7 +75,7 @@ if __name__ == '__main__': [p.D7, p.D6, p.D5, p.D4, p.D3, p.D2, p.D1, p.D0], [1, 0, 1, 0, 1, 0, 1, 0] ) - + def testDatabitsGroups(self): """nibbles D0..D7""" p = self.p @@ -86,39 +86,39 @@ if __name__ == '__main__': self.failUnlessEqual(p._data, 0xd0) p.D0_D3 = p.D4_D7 = 0xa self.failUnlessEqual(p._data, 0xaa) - # test bit patterns + #test bit patterns for x in range(256): - # test getting + #test getting p._data = x self.failUnlessEqual((p.D4_D7, p.D0_D3), (((x>>4) & 0xf), (x & 0xf))) - # test setting + #test setting p._data = 0 (p.D4_D7, p.D0_D3) = (((x>>4) & 0xf), (x & 0xf)) self.failUnlessEqual(p._data, x) - + def testStatusbits(self): """bit by bit status lines""" - # read the property: + #read the property: self.p._dummy = 0 self.failUnlessEqual(self.p.paperOut, 0) - + self.p._dummy = 1 self.failUnlessEqual(self.p.paperOut, 1) - - # read only, must not be writable: + + #read only, must not be writable: self.failUnlessRaises(AttributeError, setattr, self.p, 'paperOut', 1) - + def testControlbits(self): """bit by bit control lines""" self.p.dataStrobe = 0 self.failUnlessEqual(self.p._last, ('setDataStrobe', 0)) self.p.dataStrobe = 1 self.failUnlessEqual(self.p._last, ('setDataStrobe', 1)) - - # write only, must not be writable: + + #write only, must not be writable: self.failUnlessRaises(AttributeError, getattr, self.p, 'dataStrobe') - + sys.argv.append('-v') # When this module is executed from the command-line, it runs all its tests unittest.main() - +
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