diff options
Diffstat (limited to 'yjit/src')
| -rw-r--r-- | yjit/src/asm/arm64/inst/conditional.rs | 73 | ||||
| -rw-r--r-- | yjit/src/asm/arm64/inst/mod.rs | 2 | ||||
| -rw-r--r-- | yjit/src/asm/arm64/mod.rs | 22 | ||||
| -rw-r--r-- | yjit/src/backend/arm64/mod.rs | 29 | ||||
| -rw-r--r-- | yjit/src/backend/ir.rs | 18 | ||||
| -rw-r--r-- | yjit/src/backend/x86_64/mod.rs | 44 |
6 files changed, 188 insertions, 0 deletions
diff --git a/yjit/src/asm/arm64/inst/conditional.rs b/yjit/src/asm/arm64/inst/conditional.rs new file mode 100644 index 0000000000..e1950e95b4 --- /dev/null +++ b/yjit/src/asm/arm64/inst/conditional.rs @@ -0,0 +1,73 @@ +use super::super::arg::Sf; + +/// The struct that represents an A64 conditional instruction that can be +/// encoded. +/// +/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 | +/// | 0 0 1 1 0 1 0 1 0 0 0 0 | +/// | sf rm.............. cond....... rn.............. rd.............. | +/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +/// +pub struct Conditional { + /// The number of the general-purpose destination register. + rd: u8, + + /// The number of the first general-purpose source register. + rn: u8, + + /// The condition to use for the conditional instruction. + cond: u8, + + /// The number of the second general-purpose source register. + rm: u8, + + /// The size of the registers of this instruction. + sf: Sf +} + +impl Conditional { + /// CSEL + /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CSEL--Conditional-Select-?lang=en + pub fn csel(rd: u8, rn: u8, rm: u8, cond: u8, num_bits: u8) -> Self { + Self { rd, rn, cond, rm, sf: num_bits.into() } + } +} + +/// https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Register?lang=en#condsel +const FAMILY: u32 = 0b101; + +impl From<Conditional> for u32 { + /// Convert an instruction into a 32-bit value. + fn from(inst: Conditional) -> Self { + 0 + | ((inst.sf as u32) << 31) + | (1 << 28) + | (FAMILY << 25) + | (1 << 23) + | ((inst.rm as u32) << 16) + | ((inst.cond as u32) << 12) + | ((inst.rn as u32) << 5) + | (inst.rd as u32) + } +} + +impl From<Conditional> for [u8; 4] { + /// Convert an instruction into a 4 byte array. + fn from(inst: Conditional) -> [u8; 4] { + let result: u32 = inst.into(); + result.to_le_bytes() + } +} + +#[cfg(test)] +mod tests { + use super::*; + use super::super::super::arg::Condition; + + #[test] + fn test_csel() { + let result: u32 = Conditional::csel(0, 1, 2, Condition::NE, 64).into(); + assert_eq!(0x9a821020, result); + } +} diff --git a/yjit/src/asm/arm64/inst/mod.rs b/yjit/src/asm/arm64/inst/mod.rs index 5d4d252d93..c69bb5e871 100644 --- a/yjit/src/asm/arm64/inst/mod.rs +++ b/yjit/src/asm/arm64/inst/mod.rs @@ -6,6 +6,7 @@ mod branch; mod branch_cond; mod breakpoint; mod call; +mod conditional; mod data_imm; mod data_reg; mod load; @@ -25,6 +26,7 @@ pub use branch::Branch; pub use branch_cond::BranchCond; pub use breakpoint::Breakpoint; pub use call::Call; +pub use conditional::Conditional; pub use data_imm::DataImm; pub use data_reg::DataReg; pub use load::Load; diff --git a/yjit/src/asm/arm64/mod.rs b/yjit/src/asm/arm64/mod.rs index 6eebccaa61..3feee65197 100644 --- a/yjit/src/asm/arm64/mod.rs +++ b/yjit/src/asm/arm64/mod.rs @@ -272,6 +272,23 @@ pub fn cmp(cb: &mut CodeBlock, rn: A64Opnd, rm: A64Opnd) { cb.write_bytes(&bytes); } +/// CSEL - conditionally select between two registers +pub fn csel(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd, cond: u8) { + let bytes: [u8; 4] = match (rd, rn, rm) { + (A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::Reg(rm)) => { + assert!( + rd.num_bits == rn.num_bits && rn.num_bits == rm.num_bits, + "All operands must be of the same size." + ); + + Conditional::csel(rd.reg_no, rn.reg_no, rm.reg_no, cond, rd.num_bits).into() + }, + _ => panic!("Invalid operand combination to csel instruction."), + }; + + cb.write_bytes(&bytes); +} + /// LDADDAL - atomic add with acquire and release semantics pub fn ldaddal(cb: &mut CodeBlock, rs: A64Opnd, rt: A64Opnd, rn: A64Opnd) { let bytes: [u8; 4] = match (rs, rt, rn) { @@ -761,6 +778,11 @@ mod tests { } #[test] + fn test_csel() { + check_bytes("6a018c9a", |cb| csel(cb, X10, X11, X12, Condition::EQ)); + } + + #[test] fn test_ldaddal() { check_bytes("8b01eaf8", |cb| ldaddal(cb, X10, X11, X12)); } diff --git a/yjit/src/backend/arm64/mod.rs b/yjit/src/backend/arm64/mod.rs index 8b5576f7be..1128eb225f 100644 --- a/yjit/src/backend/arm64/mod.rs +++ b/yjit/src/backend/arm64/mod.rs @@ -137,6 +137,17 @@ impl Assembler } asm.cret(C_RET_OPND); }, + Op::CSelZ | Op::CSelNZ | Op::CSelE | Op::CSelNE | + Op::CSelL | Op::CSelLE | Op::CSelG | Op::CSelGE => { + let new_opnds = opnds.into_iter().map(|opnd| { + match opnd { + Opnd::Reg(_) | Opnd::InsnOut { .. } => opnd, + _ => asm.load(opnd) + } + }).collect(); + + asm.push_insn(op, new_opnds, target, text); + }, Op::IncrCounter => { // Every operand to the IncrCounter instruction need to be a // register once it gets there. So here we're going to load @@ -624,6 +635,24 @@ impl Assembler }, Op::Breakpoint => { brk(cb, A64Opnd::None); + }, + Op::CSelZ | Op::CSelE => { + csel(cb, insn.out.into(), insn.opnds[0].into(), insn.opnds[1].into(), Condition::EQ); + }, + Op::CSelNZ | Op::CSelNE => { + csel(cb, insn.out.into(), insn.opnds[0].into(), insn.opnds[1].into(), Condition::NE); + }, + Op::CSelL => { + csel(cb, insn.out.into(), insn.opnds[0].into(), insn.opnds[1].into(), Condition::LT); + }, + Op::CSelLE => { + csel(cb, insn.out.into(), insn.opnds[0].into(), insn.opnds[1].into(), Condition::LE); + }, + Op::CSelG => { + csel(cb, insn.out.into(), insn.opnds[0].into(), insn.opnds[1].into(), Condition::GT); + }, + Op::CSelGE => { + csel(cb, insn.out.into(), insn.opnds[0].into(), insn.opnds[1].into(), Condition::GE); } }; } diff --git a/yjit/src/backend/ir.rs b/yjit/src/backend/ir.rs index e42a0c50b4..a5fd012a2b 100644 --- a/yjit/src/backend/ir.rs +++ b/yjit/src/backend/ir.rs @@ -104,6 +104,16 @@ pub enum Op Jnz, Jo, + // Conditional select instructions + CSelZ, + CSelNZ, + CSelE, + CSelNE, + CSelL, + CSelLE, + CSelG, + CSelGE, + // Push and pop registers to/from the C stack CPush, CPop, @@ -877,3 +887,11 @@ def_push_2_opnd_no_out!(cmp, Op::Cmp); def_push_2_opnd_no_out!(test, Op::Test); def_push_0_opnd_no_out!(breakpoint, Op::Breakpoint); def_push_2_opnd_no_out!(incr_counter, Op::IncrCounter); +def_push_2_opnd!(csel_z, Op::CSelZ); +def_push_2_opnd!(csel_nz, Op::CSelNZ); +def_push_2_opnd!(csel_e, Op::CSelE); +def_push_2_opnd!(csel_ne, Op::CSelNE); +def_push_2_opnd!(csel_l, Op::CSelL); +def_push_2_opnd!(csel_le, Op::CSelLE); +def_push_2_opnd!(csel_g, Op::CSelG); +def_push_2_opnd!(csel_ge, Op::CSelGE); diff --git a/yjit/src/backend/x86_64/mod.rs b/yjit/src/backend/x86_64/mod.rs index 31a907b55e..3ee46e5936 100644 --- a/yjit/src/backend/x86_64/mod.rs +++ b/yjit/src/backend/x86_64/mod.rs @@ -142,6 +142,17 @@ impl Assembler asm.push_insn(op, vec![opnd0, opnd1], target, text); }, + Op::CSelZ | Op::CSelNZ | Op::CSelE | Op::CSelNE | + Op::CSelL | Op::CSelLE | Op::CSelG | Op::CSelGE => { + let new_opnds = opnds.into_iter().map(|opnd| { + match opnd { + Opnd::Reg(_) | Opnd::InsnOut { .. } => opnd, + _ => asm.load(opnd) + } + }).collect(); + + asm.push_insn(op, new_opnds, target, text); + }, Op::Mov => { match (opnds[0], opnds[1]) { (Opnd::Mem(_), Opnd::Mem(_)) => { @@ -388,6 +399,39 @@ impl Assembler Op::Breakpoint => int3(cb), + Op::CSelZ => { + mov(cb, insn.out.into(), insn.opnds[1].into()); + cmovz(cb, insn.out.into(), insn.opnds[0].into()); + }, + Op::CSelNZ => { + mov(cb, insn.out.into(), insn.opnds[1].into()); + cmovnz(cb, insn.out.into(), insn.opnds[0].into()); + }, + Op::CSelE => { + mov(cb, insn.out.into(), insn.opnds[1].into()); + cmove(cb, insn.out.into(), insn.opnds[0].into()); + }, + Op::CSelNE => { + mov(cb, insn.out.into(), insn.opnds[1].into()); + cmovne(cb, insn.out.into(), insn.opnds[0].into()); + }, + Op::CSelL => { + mov(cb, insn.out.into(), insn.opnds[1].into()); + cmovl(cb, insn.out.into(), insn.opnds[0].into()); + }, + Op::CSelLE => { + mov(cb, insn.out.into(), insn.opnds[1].into()); + cmovle(cb, insn.out.into(), insn.opnds[0].into()); + }, + Op::CSelG => { + mov(cb, insn.out.into(), insn.opnds[1].into()); + cmovg(cb, insn.out.into(), insn.opnds[0].into()); + }, + Op::CSelGE => { + mov(cb, insn.out.into(), insn.opnds[1].into()); + cmovge(cb, insn.out.into(), insn.opnds[0].into()); + }, + // We want to keep the panic here because some instructions that // we feed to the backend could get lowered into other // instructions. So it's possible that some of our backend |