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* riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin2022-11-032-14/+14
* riscv: andes_plic.c: use modified IPI schemeYu Chien Peter Lin2022-10-201-3/+4
* dm: core: Drop ofnode_is_available()Simon Glass2022-09-292-2/+2
* treewide: Drop bootm_headers_t typedefSimon Glass2022-09-291-4/+4
* riscv: Introduce AVAILABLE_HARTSRick Chen2022-09-262-0/+4
* spl: introduce SPL_XIP to configNikita Shubin2022-09-262-2/+2
* zynqmp: Run board_get_usable_ram_top() only on main U-BootAshok Reddy Soma2022-07-261-1/+1
* arm: riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLEDMichal Simek2022-07-261-2/+0
* riscv: provide missing base extension functionsHeinrich Schuchardt2022-04-061-0/+65
* event: Convert arch_cpu_init_dm() to use eventsSimon Glass2022-03-101-1/+2
* efi_loader: fix SectionAlignment, FileAlignmentHeinrich Schuchardt2022-01-153-6/+7
* riscv: revert Complete efi header for RV32/64Heinrich Schuchardt2022-01-151-10/+0
* riscv: function to retrieve SBI implementation versionHeinrich Schuchardt2021-11-081-0/+19
* fdtdec: Support reserved-memory flagsThierry Reding2021-10-131-1/+1
* fdtdec: Support compatible string list for reserved memoryThierry Reding2021-10-131-1/+1
* image: Drop IMAGE_ENABLE_OF_LIBFDTSimon Glass2021-10-081-2/+2
* sysreset: provide SBI based sysreset driverHeinrich Schuchardt2021-10-071-0/+12
* riscv: Fix setting no-map in reserved memory nodesSamuel Holland2021-10-071-4/+1
* lmb: riscv: Add arch_lmb_reserve()Marek Vasut2021-09-231-0/+13
* riscv: lib: implement enable_caches for sifive cacheZong Li2021-09-072-0/+28
* common: board_r: support enable_caches for RISC-VZong Li2021-09-071-0/+4
* riscv: show code leading to exceptionHeinrich Schuchardt2021-09-071-0/+33
* efi_loader: add Linux magic to RISC-V crt0Heinrich Schuchardt2021-08-141-2/+5
* riscv: booti: do not force relocation if force_reloc is not setVitaly Wool2021-07-211-1/+6
* riscv: andes_plic: Fix riscv_get_ipi() maskBin Meng2021-06-171-1/+3
* riscv: Drop USE_SPL_FIT_GENERATORBin Meng2021-05-191-100/+0
* riscv: Fix memmove and optimise memcpy when misalignBin Meng2021-05-172-142/+257
* riscv: Fix arch_fixup_fdt always failing without /chosenSean Anderson2021-05-171-4/+7
* riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng2021-05-171-1/+1
* Add support for stack-protectorJoel Peshkin2021-04-201-0/+1
* riscv: assembler versions of memcpy, memmove, memsetHeinrich Schuchardt2021-04-084-0/+289
* riscv: simplify longjmpHeinrich Schuchardt2021-04-081-6/+2
* common: Drop asm/global_data.h from common headerWIP/2021-02-02-drop-asm_global_data-when-unusedSimon Glass2021-02-029-0/+9
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextWIP/05Jan2021-nextTom Rini2021-01-051-1/+1
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| * dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-051-1/+1
* | riscv: Complete efi header for RV32/64Leo Yu-Chi Liang2020-12-141-0/+10
* | riscv: Fix efi header size for RV32Leo Yu-Chi Liang2020-12-141-3/+14
* | riscv: Fix efi header for RV32Atish Patra2020-12-141-1/+6
* | riscv: reset after crashHeinrich Schuchardt2020-12-141-4/+4
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* riscv: Move timer portions of SiFive CLINT to drivers/timerSean Anderson2020-10-261-39/+2
* riscv: Move Andes PLMT driver to drivers/timerSean Anderson2020-10-262-51/+0
* timer: Return count from timer_ops.get_countSean Anderson2020-10-222-8/+4
* Merge branch 'next'Tom Rini2020-10-058-126/+98
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| * riscv: Ensure gp is NULL or points to valid dataSean Anderson2020-09-301-1/+2
| * riscv: Use a valid bit to ignore already-pending IPIsSean Anderson2020-09-301-2/+14
| * riscv: Match memory barriers between send_ipi_many and handle_ipiSean Anderson2020-09-301-0/+2
| * riscv: Rework Sifive CLINT as UCLASS_TIMER driverSean Anderson2020-09-301-28/+34
| * riscv: Clean up initialization in Andes PLICSean Anderson2020-09-301-33/+25
| * riscv: Rework Andes PLMT as a UCLASS_TIMER driverSean Anderson2020-09-301-23/+21
| * riscv: Rework riscv timer driver to only support S-modeSean Anderson2020-09-302-39/+0
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