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* ARM: add LS1021A to Layerscape machine supportRenaud Barbier2023-03-151-1/+170
| | | | | | | | | | | | | This updates the Layerscape support in preparation for the introduction of the LS1021A-IOT: - Makefile/Kconfig - LS1021A specific register maps and configurations - errata workarounds update Signed-off-by: Renaud Barbier <renaud.barbier@ametek.com> Link: https://lore.barebox.org/BL0PR07MB56654DCD4F18A3B1A6A2F2E4ECB99@BL0PR07MB5665.namprd07.prod.outlook.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr_dimms: Move FSL dimm_params to include/ddr_dimms.hJohn Watts2023-01-241-91/+1
| | | | | | | | This is in preparation for use for generic SPD calculations. Signed-off-by: John Watts <contact@jookia.org> Link: https://lore.barebox.org/20230121144429.3524905-4-contact@jookia.org Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/caam'Sascha Hauer2023-01-201-0/+17
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| * crypto: caam - implement early PBL initAhmad Fatoum2023-01-121-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the CAAM is TrustZone aware, Linux and OP-TEE drivers are not necessarily so: - Linux running in normal world will attempt to set up RNG via DECO, which can be restricted to secure world - OP-TEE may depend on RNG being set up by BL2 While the proper solution would be to teach their drivers how to instantiate the RNG via SHs, we'll want to support existing firmware, so take the easy way out and just set up RNG4 SH0 and SH1 in barebox. We already do that for the i.MX6, but the setup there happens in barebox proper. For security reasons, we want to install OP-TEE as early as possible while running the prebootloader, so we replicate the setup for PBL. This has been tested with the i.MX8MM and i.MX8MN. Note that barebox itself does not yet benefit from this setup and that the barebox proper driver for CAAM is unaffected by this change. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230111075940.922817-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | mtd: nand: atmel: import Linux NAND controller driverAhmad Fatoum2023-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | For a few years, Linux has been using the new EBI bindings for NAND controllers on all AT91 SoCs newer than the AT91RM2000. We have so far only supported the old bindings by hacking the DT, but this doesn't suffice for the SAMA5D4. Therefore import a new state of the Linux NAND controller driver. We still keep around the old barebox driver to support the non-DT enabled AT91 platforms. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230111174023.1719129-13-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | memory: add Atmel EBI driverAhmad Fatoum2023-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This driver is used to configure the EBI (external bus interface) when the device-tree is used. This bus supports NANDs, external Ethernet controller, SRAMs, ATA devices, etc. We import it from Linux in barebox in preparation for importing a newer state of the Atmel NAND controller driver. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230111174023.1719129-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Rename struct device_d to deviceSascha Hauer2023-01-102-5/+5
|/ | | | | | | | | | | | | The '_d' suffix was originally introduced in case we want to import Linux struct device as a separate struct into barebox. Over time it became clear that this won't happen, instead barebox struct device_d is basically the same as Linux struct device. Rename the struct name accordingly to make porting Linux code easier. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.barebox.org/20221214123512.189688-3-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2022-12-122-4/+2
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| * include: soc: switch to SPDX-License-IdentifierAhmad Fatoum2022-12-092-4/+2
| | | | | | | | | | | | | | | | Two files in include/soc miss an SPDX-License-Identifier. Add them. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221209071644.3767682-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx7-nand-xload'Sascha Hauer2022-12-121-0/+147
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| * | ARM: i.MX: xload nand: Move mxs_nand_mode_fcb_62bit() to header fileSascha Hauer2022-11-021-0/+33
| | | | | | | | | | | | | | | | | | | | | mxs_nand_mode_fcb_62bit() can be shared between the regular MTD NAND driver and the upcoming i.MX7 xload driver. Move to header file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: nand-mxs: Move register definitions to separate fileSascha Hauer2022-11-021-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPMI registers are needed in the MTD GPMI driver and also in the xload-gpmi driver. So far both use their own set of register defines. Move the MTD GPMI register defines to include/ so that we can use them in the xload driver as well. While at it replace some register defines to use FIELD_PREP instead. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: imx8m: allow ddr_get_firmware to be called from other unitsLucas Stach2022-12-091-1/+1
| |/ |/| | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://lore.barebox.org/20221207220924.148327-1-l.stach@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: stm32mp: mark iwdg2 with barebox,restart-warm-bootromAhmad Fatoum2022-10-271-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | All STM32MP1 DTs already include their respective barebox SoC header, so set barebox,restart-warm-bootrom there, so users can portably run: tamp.reboot_mode.next=serial reset -w To get into DFU mode. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221017071000.1458292-9-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | usb: gadget: fsl_udc: add imx7_barebox_(load/start)_usbAhmad Fatoum2022-10-271-0/+3
|/ | | | | | | | | | | These can be called from barebox PBL when booted from USB to continue USB boot. This isn't necessary in the general case when RAM setup is done via DCD, but for cases where setup is done in PBL, these helpers come in handy. Tested on i.MX7D revision 1.2. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221017071036.1458761-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8MP: add feature controller support for PlusAhmad Fatoum2022-10-181-0/+3
| | | | | | | | | | | | | | Plus has lots of peripherals that need be disabled, depending on fusebox settings. Some of these are already described in the upstream device tree, so reference them in the barebox DT and add the necessary glue for disabling them like we already do on i.MX8MM/N. We omit CPU fusing for now. These are handled by tester3 and would need a bit more rework. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221017134929.622022-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-mxs: add i.MX7 FCB write supportJohannes Zink2022-10-051-0/+11
| | | | | | | | | | | | The FCB on the i.MX7 is written in BCH62 mode and with randomizer enabled. This needs special FCB read/write functions. Add them to the driver. Signed-off-by: Johannes Zink <j.zink@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Johannes Zink <j.zink@pengutronix.de> # innocomm S810 Link: https://lore.barebox.org/20220930121553.335796-4-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2022-09-141-0/+25
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| * soc: imx: add i.MX8M feature controller driverAhmad Fatoum2022-09-011-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tester4 fuse bank of the i.MX8M is a 32-bit collection of fuses, apaprently fused during test, which contains information about the available IPs: How many cores are available and whether a VPU and GPU is available an usable. Add a imx8m_feat_ctrl_init() function that initializes a bitmap of supported features using tester4's value and registers a feature controller with a check callback that just looks up the relevant bit. This function can then be called from a standalone driver or from the fuse bank (ocotp) driver itself. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220818051955.2088238-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | usb: gadget: fsl_udc: add imx6_barebox_(load/start)_usbAhmad Fatoum2022-09-011-0/+3
|/ | | | | | | | | | | These can be called from barebox PBL when booted from USB to continue USB boot. This isn't necessary in the general case when RAM setup is done via DCD, but for cases where setup is done in PBL, these helpers come in handy. Tested on i.MX6Q. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220901104153.171235-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: remove struct dram_timing_info::dram_type againAhmad Fatoum2022-08-081-12/+23
| | | | | | | | | | | | | We had added dram_timing_info::dram_type to allow the same build to support both DDR4 and LPDDR4. Since then imx8m_ddr_init has gained a new member describing the DRAM type, so we can just use that instead of the struct member. The benefit of that is that we can keep the DRAM timing code resulting from the generator unchanged. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.barebox.org/20220805125413.1046239-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr: imx8m: rename type to more fitting ddrc|dram_typeAhmad Fatoum2022-08-081-27/+27
| | | | | | | | | | | type is ambiguous and can mean either DDR controller (SoC) type, DRAM type or firmware (1D/2D) type. Replace variables called type plainly, with more descriptive ddrc_type, dram_type and fw_type. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.barebox.org/20220805125413.1046239-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: move TF-A chainload functions in <mach/xload.h>Ahmad Fatoum2022-08-081-9/+0
| | | | | | | | | | We already have <mach/xload.h> with related functions, so reuse that header instead of adding a new one. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.barebox.org/20220805125413.1046239-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8MP: Add common code to load image and jump to it via TF-ASascha Hauer2022-08-081-0/+1
| | | | | | | | | Add imx8mp_load_and_start_image_via_tfa() to load barebox proper image and jump to it via TF-A. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20220714072722.2863571-4-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: include only necessary ddrphy firmwares in imageSascha Hauer2022-07-121-4/+46
| | | | | | | | | So far we always include ddrphy firmwares for DDR4 and LPDDR4 in the images. Pass the DDR type to the RAM controller initialization so that the type is known at compile time. With this the compiler can discard the unused firmware files. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8MM: Consolidate common code to load image and jump to it via TF-AUwe Kleine-König2022-07-111-0/+8
| | | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.barebox.org/20220706081236.2833520-1-u.kleine-koenig@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rpi4'Sascha Hauer2022-06-291-0/+40
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| * ARM: rpi: parse useful data from vc fdtDaniel Brát2022-06-271-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Videocore first-stage loader on rpi passes us many useful information inside the vc fdt, including the real value of PM_RSTS register, not easily available by other means and which we can use to determine the reset cause. Also make the relevant funtions just print error/warning and continue in case of some errors, since the fdt from vc is now optional for barebox's basic function. Signed-off-by: Daniel Brát <danek.brat@gmail.com> Link: https://lore.barebox.org/20220617215811.5687-1-danek.brat@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2022-06-291-1/+0
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| * | ddr: imx8m: remove header including itselfAhmad Fatoum2022-06-241-1/+0
| |/ | | | | | | | | | | | | | | This line has noeffect because of the include guard, so just drop it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220623085741.3680767-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ddr: imx8m: workaround old spreadsheets not initializing ADDRMAP7Ahmad Fatoum2022-06-271-0/+1
|/ | | | | | | | | | | | | | | | | | | | Older NXP DDR spreadsheets don't initialize ADDRMAP7, leaving it at its POR default of zero. Now that barebox looks at ADDRMAP7 to be able to correctly detect bigger memory sizes, barebox proper on out-of-tree boards with older spreadsheets may read back 4x times as much RAM as actually fitted. Work around this by writing a trailing 0xf0f (the neutral ignore-me value for the register) if the register wasn't written through dram_timing_info::ddrc_cfg. We consider this safe to do, because the DDRC is held in reset while these values are programmed. Fixes: dad2b5636bd8 ("ARM: imx: Add imx8 support for 18 bit SDRAM row size handle") Fixes: 6cf197fa61f9 ("arm: imx: mmdc_size: Increase row_max for imx8m") Tested-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220623130717.1447999-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: stm32mp1: sync with Linux v5.17-rc1Ahmad Fatoum2022-03-081-0/+16
| | | | | | | | | | | | Linux has meanwhile extended the RCC driver to support both reset and clocks as well as peaceful co-existence with the SCMI driver. Import these changes into barebox and remove the reset controller handling from the old RCC reset driver. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-22-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/spdx'Sascha Hauer2022-01-193-0/+6
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| * include: add SPDX-License-IdentifierAhmad Fatoum2022-01-053-0/+6
| | | | | | | | | | | | | | | | | | All these files lack a license statement, so add the default GPL-2.0-only. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | pinctrl: stm32: replace magic values with defines for STM32_PINMODEAhmad Fatoum2022-01-141-0/+4
|/ | | | | | | | | Makes the code easier to follow and allows using the new macros in PBL code for early pinmuxing of e.g. the debug UART. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20220114065943.698337-1-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr: imx8m: ddrphy_train: add DDR4 supportAhmad Fatoum2021-10-051-1/+19
| | | | | | | | | | | | | | | There are DDR3L, DDR4 and LPDDR4 variants of the i.MX8M* SoMs used with the NXP EVKs. So far, we only supported LPDDR4. For DDR4, we just need different PHY training code. Encode the DRAM variant information into a new dram_timing_info::dram_type and adjust the driver to make use of it. The new CONFIG_FIRMWARE_IMX_DDR4_PMU_TRAIN Kconfig symbol can co-exist with CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN, allowing the same barebox binary to target different memory types, provided board code can determine what kind of DRAM is fitted. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20211001100949.6891-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr: imx8m: add i.MX8MN (Nano) supportAhmad Fatoum2021-10-051-0/+2
| | | | | | | | | | DRAM setup on i.MX8MP is the same as on the i.MX8MP, except for DDRC_DDR_SS_GPR0, which the vendor's U-Boot port explicitly skips on the nano, irrespective of the configured DRAM type. Do likewise. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20211001100949.6891-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX6: boot: detect USB serial downloader more reliableMarco Felsch2021-08-181-0/+11
| | | | | | | | | | | | | | | | | | | | | The problem with the BootROM is that the SRC registers are not set accordingly in case of a failed primary boot. E.g. if the device is configured to boot from an eMMC and the eMMC is empty or image is corrupt, the BootROM goes into 'recovery boot mode' (reference manual Figure 8-1) and the last possible recovery option is the serial downloader. In such case the SRC registers still indicate that the device was booted from an eMMC instead of serial-download. This commit ports the U-Boot commit [1] with slightly adaptions suggested by Ahmad to Barebox. Also we need to reorder the imx6_init() else we reset the otg-controller to early. [1] https://source.denx.de/u-boot/u-boot/-/commit/e203dcf23e9eabc2e4f3d0b079457cd1516f2081 Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210812083651.3576-1-m.felsch@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* reset: add StarFive reset controller driverAhmad Fatoum2021-06-241-0/+41
| | | | | | | | | | | | | | | | The StarFive SoC has a single reset controller, which seems to control reset of all clocks and peripherals. It differs from the ones supported by the Linux reset-simple driver in that it has a dedicated status registers that needs to be polled to verify the reset has completed. Also special is that most resets (> 70) are synchronous. As the reset status poll would just time out without the clock, have the reset controller enable the clock as part of the reset. OS can decide later, which clocks to disable again. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-24-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* net: designware: add support for IP integrated into StarFive SoCAhmad Fatoum2021-06-241-0/+15
| | | | | | | | | | The Designware MAC on the StarFive jh7100 needs some special speed configuration. Match against a new starfive,stmmac compatible that describes that. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-17-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: soc: sifive: add basic L2 cache controller driverAhmad Fatoum2021-06-241-0/+10
| | | | | | | | | | | | | | SiFive SoCs are cache coherent with respect to other DMA masters, so there is no need to explicitly flush cache lines. Incoming StarFive SoC uses SiFive CPU and L2 cache controller, but is cache-incoherent and thus needs the maintenance for DMA. Add a basic driver that exports the cache flush function for SoC-specific drivers to use. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-13-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: move BCB structures to header filePrimoz Fiser2021-02-011-0/+80
| | | | | | | | | Move i.MX BCB related structures to header file so they can be used by others. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Signed-off-by: Andrej Picej <andrej.picej@norik.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr: imx8m: remove bogus definesLucas Stach2021-01-061-7/+0
| | | | | | | | | Most of those defines aren't used. Whether DDR_ONE_RANK should be defined is really dependent on the used DRAM on a specific board, so move this from the common header into the board DRAM setup. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr: imx8m: implement i.MX8MQ supportLucas Stach2021-01-061-2/+2
| | | | | | | | | | | | The i.MX8MQ uses a different PLL type than the later i.MX8M family members, so the PLL setup did not actually work on this SoC. In U-Boot the used PLL setup routine is a compile time decision. As we want our DRAM init code to work for multi-image builds, this passes the SoC type through to the PLL init, so we can use the correct setup routine depending on the SoC we are running on. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr: imx8m: add workaround for DDRPHY rank to rank issueLucas Stach2020-11-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | This is a port of upstream U-Boot commit b335966958a9. Sadly there is no more information to be found about the issue. The currently available errata documents don't mention this issue at all and the U-Boot commit doesn't tell much either, however this commit has been pointed out by NXP engineers as a solution to reports of board instabilities. | drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue | | Add logic to automatically update umctl2's setting based | on phy training CDD value for rank to rank space issue | | Acked-by: Ye Li <ye.li@nxp.com> | Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com> | Signed-off-by: Jacky Bai <ping.bai@nxp.com> | Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Sascha Hauer <s.hauer@pengutronix.de> (on i.MX8MP) Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr: imx8m: clean up entry pointsLucas Stach2020-11-091-0/+7
| | | | | | | | | | The DDRC address in the memory map and the TF-A parameter store address is the same for all i.MX8M* SoCs. The only difference (for now) is in the power up sequence. Add a enum for the DDRC type, so we can take different code paths in imx8m_ddr_init() depending on the SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Add DDR controller supportSascha Hauer2020-02-192-0/+504
| | | | | | | | | | | | | | | This adds the DDR driver for the i.MX8MQ/i.MX8MM. It's taken from U-Boot v2020.04-rc1 with slight modifications for barebox The i.MX8MQ boards in the tree currently use the output of an earlier version of the NXP i.MX8M DDR Tool which doesn't use a controller driver but instead does most stuff in board code. It seems this can coexist with the new driver, only a few helper functions that previously lived in arch/arm/mach-imx/imx8-ddrc.c are now provided by the new driver. Tested on an i.MX8MM EVK Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: Add pll14xx supportSascha Hauer2020-02-191-0/+7
| | | | | | | | This adds support for the pll14xx found on i.MX8MM devices. This is taken from the Kernel as of v5.5. Since we'll need some early setup for the PLL a PBL hook is added to be called from lowlevel code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* usb: gadget: fsl_udc: Add PBL image loading supportSascha Hauer2020-02-191-0/+6
| | | | | | | | | | | | | | | | | For boards that do the RAM setup in code we can up to now only download the PBL part to SRAM. This patch adds support for downloading the rest of the image after the RAM has been configured. The ROM is nice enough to leave the USB controller initialized after a download, so we don't have to reinitialize it, but can simply continue to use the controller. Like all two-staged loading processes on i.MX this needs board support, it will only work when a board calls imx_barebox_load_usb() or one of the SoC specific variants. This needs the host counterpart in imx-usb-loader which is done in the next patch. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* USB: gadget: fsl_udc: move register definitions to header fileSascha Hauer2020-02-191-0/+377
| | | | | | | The register definitions will be shared by the regular and the pbl driver, so move them to a header file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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