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* configs/builder: add default config for Intel Archer City CRBChristian Walter2023-04-271-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | which is based on Intel Sapphire Rapids Scalable Processor chipset which was product launched on Jan. 10 2023. The site-local/* files are Intel binaries that are not published yet but coreboot build validation system would skip these binaries when they are in "site-local" directory. Please make sure you have the correct Intel binaries for your AC CRB and place them to the right location accordingly. CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage" is LinuxBoot payload, there are several ways to build it, one way is to build it from the x86_64 qemu example from osf-builder: git clone https://github.com/linuxboot/osf-builder cd examples/qemu; make kernel commit ae90fc0bb (soc/intel/xeon_sp/spr: Default to X2APIC support) would enable DEFAULT_X2APIC_RUNTIME, your LinuxBoot kernel needs to enable X2APIC support, otherwise need to set CONFIG_XAPIC_ONLY=y in your defconfig. Change-Id: I15aefc3edb2d22fc00d854850e948fe2048a992e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71969 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.lenovo_t400_vboot_and_debug: Move PT lowerArthur Heymans2023-04-061-0/+1
| | | | | | | | | | Bootblock gets too big, so move the RO page table downwards. Change-Id: I3f72d1639478eaaac09d7cfb3408944ac76307c4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74219 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/protectli/vault_ehl: Add initial structureKacper Stojek2023-03-031-0/+13
| | | | | | | | | | | | | | | | This patch adds base code for the Protectli VP2420. The GPIO config has been extracted with inteltool from the stock firmware and then parsed with intelp2m. As of now, the platform runs with edk2 with no apparent issues. Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: Ia00c27117d48b76db306d3f988f159fc5d50e4a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* mb/protectli/vault_cml: Add Comet Lake 6 port board supportMichał Żygowski2023-02-172-0/+26
| | | | | | | | Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* configs/builder/config.ocp.tiogapass: Add CONFIG_BOARD_OCP_TIOGAPASSJohnny Lin2023-02-021-0/+1
| | | | | | | | | | | | Otherwise configurations in src/mainboard/ocp/tiogapass/Kconfig cannot be selected by make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.tiogapass Change-Id: I88d5619269a6a9c09e84061642206a17c91db042 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* configs/config.facebook_fbg1701.sbom: Fix var namesMaximilian Brune2023-01-311-4/+4
| | | | | | | | | | | The variables defined in this defconfig are incorrectly named, therefore fix them. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I9299be96f8c44d6a87d380f4f942c4d26af7050d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* configs/google_skyrim.no_video: Fix typo and regenerateMartin Roth2023-01-141-2/+6
| | | | | | | | | | | | | | | | | | | | | | | There was a typo in the config disabling bootblock should have been: # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK is not set As the line moved, it is the missing underscore after CONFIG, preventing it from working as intended. The other changes are updates to allow it to match what we get by copying it to .config, then running: make olddefconfig; make savedefconfig Change-Id: Ic41a91e0a6ecd254a86d0872da19a0d4d321b8e3 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71840 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/msi/ms7d25: Add support for DDR5 variantMichał Żygowski2023-01-132-0/+21
| | | | | | | | | | | | | | The DDR5 board is almost identical to the DDR4 one. The only major difference is the board's DDR5 memory design. TEST=Boot MSI PRO Z690-A board successfully to Ubuntu 22.04. Memory: Crucial CT8G48C40U5.M4A1 in all 4 slots. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I652a879d1616df4708fe4690797ad98384897f53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* configs: Build x201 for 64bitArthur Heymans2023-01-091-0/+1
| | | | | | | | | | | This now also tests a lot of debug code on 64bit. Change-Id: Iea3d5b8926fd8300c9daba0bc6dac91b9e55cdd6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* configs: Add 64bit buildtest for prodrive/hermesArthur Heymans2022-12-161-0/+17
| | | | | | | | | | This configuration also boots on real hardware. Change-Id: Ic62a33f8d8c3fdaa8182e797b2bf6fbed6b55731 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69236 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/haswell: Introduce option to not use MRC.binAngel Pons2022-12-121-0/+5
| | | | | | | | | | | | | | | Introduce the `USE_NATIVE_RAMINIT` Kconfig option, which should allow booting coreboot on Haswell mainboards without the need of the closed source MRC.bin. For now, this option does not work at all; the needed magic will be implemented in subsequent commits. Add a config file to make sure the newly-introduced option gets build-tested. Change-Id: I46c77586f9b5771624082e07c60c205e578edd8e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* configs: Buildtest 64bit amd/picassoArthur Heymans2022-11-161-0/+3
| | | | | | | | Change-Id: Ia7b9925ab0a594a0ec26746cbe938f7cf2aa0118 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* configs: Build test STB features on google skyrimMartin Roth2022-11-102-0/+27
| | | | | | | | | | | | | | - Update the google_skyrim.with_binaries to test printing the STB entries. - Add a new saved config to test building without video, building using an x86 verstage, and STB_SPILL_TO_DRAM Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Idddcf2441b91b79575e5dfed1cc56d207234205b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* coreboot_tables: Drop uart PCI addrArthur Heymans2022-10-261-1/+0
| | | | | | | | | | | | | | | Only edk2 used this to fill in a different struct but even there the entries go unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* configs: Add skyrim config with binariesMartin Roth2022-10-221-0/+29
| | | | | | | | | | | | | | | | | We've seen failures because the binaries were not being built into the image. In particular, the APCB is modified by the coreboot build process, so if the APCB isn't built correctly to support the correct number of SPDs, the build can fail. The mendocino FSP binaries are not yet pushed, so the build is currently pointing at the cezanne binaries. The mendocino FSP will be pushed when the mendocino chips are released for sale. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I31d11c5327416f4339930373c447531ae9f79d28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* mb/prodrive/hermes: Allow using the Intel iGPU as primaryArthur Heymans2022-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the Intel iGPU as primary video adapter if enabled according to EEPROM settings. The default is to use the ASPEED BMC as primary video adapter, which only has a VGA output and the remote KVM output. For now, use the FSP GOP driver to light up the iGPU. There are several issues with libgfxinit on the Hermes, probably due to the unusual setup of the iGPU's display outputs. They are routed to a mezzanine connector for a piggy-back sub-board, of which there are two models. The Poseidon piggy-back has two DisplayPort outputs and an HDMI output coming from a MegaChips LSPCON. The Avalanche piggy-back routes all three DisplayPort outputs from the iGPU into a FPGA, which acts as a DisplayPort sink. Note that the FSP GOP only initializes at most 2 iGPU display outputs. However, all three outputs function properly once OS (Windows, Linux) graphics drivers take over. Additionally, update the config file that Prodrive uses to build coreboot images so that the iGPU can be used as primary. TEST=Verify that the iGPU's outputs work properly in pre-OS, Windows and Linux, on both the Poseidon and Avalanche piggy-backs. Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62649 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.msi_ms7d25: Enable CBFS serial and UUID as defaultMichał Żygowski2022-10-111-0/+2
| | | | | | | | | | | | | | | | There is no option to calculate or generate the serial number and UUID on this platform. Enable CBFS UUID and serial by default so anybody can easily populate the missing fields. TEST=Add UUID and serial CBFS files, boot the platform and see both UUID and serial number are populated correctly. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic8af889f12617d4ab6a27c6f336276c04f26244c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64640 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.prodrive_hermes: Fix typoAngel Pons2022-09-061-1/+1
| | | | | | | | | | | Remove extra 'o' in "Tech*o*nologies". Change-Id: Icf24e00fb895a670ea798f64a79035d858ec0d4f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Add SBOM (Software Bill of Materials) GenerationMaximilian Brune2022-08-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Firmware is typically delivered as one large binary image that gets flashed. Since this final image consists of binaries and data from a vast number of different people and companies, it's hard to determine what all the small parts included in it are. The goal of the software bill of materials (SBOM) is to take a firmware image and make it easy to find out what it consists of and where those pieces came from. Basically, this answers the question, who supplied the code that's running on my system right now? For example, buyers of a system can use an SBOM to perform an automated vulnerability check or license analysis, both of which can be used to evaluate risk in a product. Furthermore, one can quickly check to see if the firmware is subject to a new vulnerability included in one of the software parts (with the specified version) of the firmware. Further reference: https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/ - Add Makefile.inc to generate and build coswid tags - Add templates for most payloads, coreboot, intel-microcode, amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM, intel ME and compiler (gcc,clang,other) - Add Kconfig entries to optionally supply a path to CoSWID tags instead of using the default CoSWID tags - Add CBFS entry called SBOM to each build via Makefile.inc - Add goswid utility tool to generate SBOM data Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* payloads/tianocore: Rename TianoCore to edk2Sean Rhodes2022-08-134-10/+10
| | | | | | | | | | | | | | | | | | | | | | coreboot uses TianoCore interchangeably with EDK II, and whilst the meaning is generally clear, it's not the payload it uses. EDK II is commonly written as edk2. coreboot builds edk2 directly from the edk2 repository. Whilst it can build some components from edk2-platforms, the target is still edk2. [1] tianocore.org - "Welcome to TianoCore, the community supporting" [2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform firmware development environment for the UEFI and UEFI Platform Initialization (PI) specifications." Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* configs: Update prodrive hermesPatrick Rudolph2022-07-141-0/+2
| | | | | | | | | | | Enable resizable BAR support and allow up to 64GiB BARs. Change-Id: If484f474aed82bf7637926c29c1d8c2907f2a161 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mainboard/msi/ms7d25: Enable PTTMichał Żygowski2022-07-111-0/+2
| | | | | | | | | | | | | | | Original firmware ships with PTT enabled by default on poweron. PTT takes priority over SPI/LPC TPM so enable the CRB interface until coreboot implements a way to select the interface and adapt the API to handle any TPM detection. TEST=Boot the board and see PTT is detected by Windows and Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/msi/ms7d25: Configure PCIe Root PortsMichał Żygowski2022-07-111-2/+3
| | | | | | | | | | | | | | | | | | | | | Add the full PCIe root port configuration. Proper initialization of the root ports depends on the correct GPIO programming including virtual wires. Do not program the CLKREQ signals in coreboot to let FSP detect and configure CLKREQ pads. Otherwise the CLKREQ pads are reprogrammed by FSP despite having GpioOverride=1. The pads that should not be touched by coreboot are left commented in the board GPIO file. CLKREQ reprogramming caused undefined behavior when ASPM and Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe x4 slot (coreboot printed a lot of exceptions and simply halted). TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots populated and check if they are detected and functional in Linux. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFIMichał Żygowski2022-07-071-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* treewide: Unify Google brandingJon Murphy2022-07-041-1/+1
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* nb/intel/gm45: Enable 64bit supportArthur Heymans2022-05-131-0/+1
| | | | | | | | | | | | | | | | | This patch does the following: - Allow selecting 64bit from Kconfig - Fix up integer to pointer conversion that gcc complains about - Add a buildtest target in configs Tested on Thinkpad X200: boots fine to the payload Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboardYaroslav Kurlaev2022-02-111-0/+1
| | | | | | | | | | | Add initial implementation for booting on QEMU POWER9 emulation. Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* configs/i440fx: Build-test PARALLEL_MPArthur Heymans2022-02-071-0/+1
| | | | | | | | | Change-Id: If30d715c5a3b44be2832c96316003dc9d139b53f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59695 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Add build test configs for CBFS verificationJulius Werner2022-01-082-0/+9
| | | | | | | | | | | | | Now that CBFS verification is available as an optional feature in menuconfig (CB:59982), we should add build test configs to ensure it doesn't break without notice. One Arm and one x86 board should be good enough for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I530dfd37472e63b80a67badd22a13d54d2c4621b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* configs: Add config for Prodrive HermesAngel Pons2021-12-201-0/+13
| | | | | | | | | | | | Build-test the configuration Prodrive uses to build coreboot for their Hermes mainboard. Change-Id: I62e79d3143851bf14dfdbe70e60c60f13dd06c3f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Justin van Son <justin.van.son@prodrive-technologies.com>
* configs/config.facebook_fbg1701: Remove CONFIG_ONBOARD_SAMSUNG_MEMFrans Hendriks2021-12-091-1/+0
| | | | | | | | | | | | | | | | CONFIG_ONBOARD_SAMSUMG_MEM was used to force Samsung memory. CPLD is used to determine the memory type leaving CONFIG_ONBOARD_SAMSUNG_MEM unused. Remove this config. BUG = N/A TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4 Change-Id: I60626552f2e2338cf5cbaaf4dca1b1eb2756d8df Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59755 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.google_meep_cros: don't select ADD_FSP_BINARIESFelix Held2021-09-041-1/+0
| | | | | | | | | | | | | | This config selected ADD_FSP_BINARIES even though HAVE_INTEL_FSP_REPO is only defined for Apollolake and not Geminilake that resides in the same SoC directory and uses the same Kconfig file. This results in the paths to the FSP binaries not being defined, in which case the ADD_FSP_BINARIES option shouldn't be selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95123c4930b44a3b76c87768e130eb7359bbf625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* AGESA f15tn: Fix building IDS tracing supportAngel Pons2021-08-221-0/+7
| | | | | | | | | | Also add a config file to ensure the code gets build-tested. Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53986 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Explicitly specify vendor and mainboardAngel Pons2021-07-0713-0/+17
| | | | | | | | | | | | | | | Relying on the implicit defaults for these settings can cause issues in the future. For example, commit 8cc4c5a1e76c0c8aee3a14618c15d38e3bd2bd61 (config.dell_optiplex_9010_sff: Specify board model) was done to prevent a build failure when adding support for other Dell mainboards which make the default board change. Change-Id: Ie0da6254def8b38e9fb053fc7d530dfb46760861 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56079 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.foxconn_g41m: Build test with X86_64Arthur Heymans2021-07-061-0/+3
| | | | | | | | | | Change-Id: I755f2037bc9368e610eb97a2633aa66da7f626b0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56042 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Build test x86_64 on Sandy BridgePatrick Rudolph2021-07-051-0/+3
| | | | | | | | | | | Add defconfig to build test x86_64 code on Sandy Bridge. Change-Id: I2c18af8bfa87636c68741e4759059276c287d052 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrik Tesarik <depate@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* src: Consolidate x86_64 support KconfigAngel Pons2021-07-021-1/+1
| | | | | | | | | | | | | Introduce `USE_EXP_X86_64_SUPPORT` in `src/arch/x86/Kconfig` and guard it with `HAVE_EXP_X86_64_SUPPORT`. Replace the per-CPU implementations of the same functionality with the newly-added Kconfig options. Update documentation and the config file for QEMU accordingly. Change-Id: I550216fd2a8323342d6b605306b0b95ffd5dcd1c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* security/intel/cbnt: Build test CBnT provisioningArthur Heymans2021-06-281-0/+8
| | | | | | | | | | | This updates the intel-sec-tools submodule pointer to include a fake acm binary to be included for buildtesting. Change-Id: Id4a9e177f71306b8c5538a578da229a53d19487a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/broadwell: Re-do SerialIO UART console supportAngel Pons2021-06-141-0/+5
| | | | | | | | | | | | | Use the same code from Lynx Point on Broadwell, and adjust as needed. Also add a config file to ensure the code gets build-tested. Tested on out-of-tree Compal LA-A992P (Haswell ULT), UART 0 works. Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb/intel/lynxpoint: Add SerialIO UART console supportAngel Pons2021-06-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | Derived from Broadwell and adapted to follow what soc/intel does. Note that SERIALIO_UART_CONSOLE is meant to be selected from the mainboards which expose a SerialIO UART. UART_FOR_CONSOLE also needs to be set in mainboard Kconfig accordingly. It is possible that some of the UART configuration steps in bootblock are unnecessary. However, some of the steps turn off power management features and others are undocumented: omitting them could cause weird issues. Finally, add a config file to ensure the code gets build-tested. Tested on out-of-tree Compal LA-A992P, SerialIO UART 0 can be used to receive coreboot and SeaBIOS logs. Change-Id: Ifb3460dd50ed03421a38f03c80f91ae9fd604022 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52489 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* config.dell_optiplex_9010_sff: Specify board modelAngel Pons2021-06-091-0/+1
| | | | | | | | | | | | Add `CONFIG_BOARD_DELL_OPTIPLEX_9010=y` to avoid issues when other Dell mainboards get added. Change-Id: Ice2073a3073a345aeb9ead7398cb4129453dd5ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* configs: Update configs for OCP Delta Lake LinuxBoot payloadJohnny Lin2021-06-011-1/+10
| | | | | | | | | | | | | | | | | | | OCP Delta Lake is developed and validated against LinuxBoot payload. Need to put the respective binary blobs in site-local/deltalake to build the final coreboot image. Add LINUX_COMMAND_LINE for LinuxBoot payload kernel cmdline, CPU_UCODE_BINARIES for CPU microcode binary, CONSOLE_SERIAL_57600 is the serial baud rate used by OCP Delta Lake, DEFAULT_CONSOLE_LOGLEVEL_4 is for a faster boot time. Tested=On OCP Delta Lake it can boot up target CentOS 8 GNU/Linux OS. Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55058 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tpm: Remove USER_TPMx options, make TPM1/TPM2 menuconfig visibleJulius Werner2021-05-272-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | We would like to have an easy way to completely disable TPM support on a board. For boards that don't pre-select a TPM protocol via the MAINBOARD_HAS_TPMx options, this is already possible with the USER_NO_TPM option. In order to make this available for all boards, this patch just removes the whole USER_TPMx option group and directly makes the TPM1 and TPM2 options visible to menuconfig. The MAINBOARD_HAS_TPMx options can still be used to select defaults and to prevent selection of a protocol that the TPM is known to not support, but the NO_TPM option always remains available. Also fix some mainboards that selected TPM2 directly, which they're not supposed to do (that's what MAINBOARD_HAS_TPM2 is for), and add a missing dependency to TPM_CR50 so it is set correctly for a NO_TPM scenario. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib0a73da3c42fa4e8deffecb53f29ee38cbb51a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* cpu/x86/smm: Drop the V1 smmloaderArthur Heymans2021-04-191-2/+0
| | | | | | | | Change-Id: I536a104428ae86e82977f2510b9e76715398b442 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/system76/gaze15: Add System76 Gazelle 15Tim Crawford2021-03-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux 20.10 and Windows 10 Not working: - Discrete/Hybrid graphics This requires a new driver to work correctly, which will be added and enabled later. Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Build-test QEMU i440fx with AddressSanitizer (ASan)Paul Menzel2021-03-191-0/+1
| | | | | | | | | | | The artifacts can then be run on test system. Change-Id: I2300af7b9be5fbb42a874566971854b93292885e Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51293 Reviewed-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/qemu-x86: Add an option to use the smmloader v2Arthur Heymans2021-03-181-0/+4
| | | | | | | | | | | The idea is to get rid of having 2 different smmloaders so add this option only to qemu/q35 to get it buildtested. Change-Id: Id4901784c4044e945b7f258b3acdc8d549665f3a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51525 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.google_volteer.build_test_purposes: Add fileAngel Pons2021-03-031-0/+32
| | | | | | | | | | | This is meant to build-test Crashlog and various debug options. Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com>
* configs/config.asrock_b85m_pro4...: Build-test ASanAngel Pons2021-02-221-0/+2
| | | | | | | | | | | | | | | | This build-tests ASan support for both romstage and ramstage, because the Haswell northbridge selects the HAVE_ASAN_IN_ROMSTAGE option. x86 Kconfig selects the HAVE_ASAN_IN_RAMSTAGE option, and Haswell is x86. Change-Id: I892881d2315c09aa6d9d80903a8399d0f4d648e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Document Gigabyte GA-G41M-ES2LAlexey Vazhnov2021-02-221-0/+13
| | | | | | | | | | | | | | | | | To replace wiki page https://www.coreboot.org/Board:gigabyte/ga-g41m-es2l + configs/config.gigabyte_ga-g41m-es2l + lshw output examples + memory modules compatibility Tested in Devuan 4 Chimaera. Tested from exact steps from this documentation. Change-Id: Ib45cfea15b43d7399e9d209f7ba7c6b24fe860dd Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
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