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authorDevaraj Ranganna <devaraj.ranganna@arm.com>2023-04-18 07:53:31 +0100
committerGitHub <noreply@github.com>2023-04-18 12:23:31 +0530
commit27cbc7f6a2313894a0a8edf8569856d51eeda32b (patch)
tree44a0ab28d62c8c548d4db5bc31f04460b349b2f6
parent5eaf2f3bce7d4f2959b289a2e4c17167f55a00fc (diff)
downloadfreertos-git-27cbc7f6a2313894a0a8edf8569856d51eeda32b.tar.gz
Update M33F simulator Keil example (#990)
* Update M33F simulator Keil example The example is updated to use latest CMSIS 5.9.0 and Device startup 2.1.0. Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com> * Increase timeout and correct config file path in the secure project Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Remove auto-generated files Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> --------- Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com> Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Diffstat
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/.gitignore8
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.sct77
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvoptx45
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvprojx55
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h1260
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s267
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c99
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/ReadMe.txt7
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.sct72
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvoptx8
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvprojx50
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h1260
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s267
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c99
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/VHT_MPS2_Cortex-M33-config.txt24
15 files changed, 263 insertions, 3335 deletions
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/.gitignore
new file mode 100644
index 000000000..669e150d1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/.gitignore
@@ -0,0 +1,8 @@
+# Keil autogenerated files.
+RTE/
+*.uvgui*
+EventRecorderStub.scvd
+
+# Build artifacts.
+Objects/
+Listings/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.sct b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.sct
index bf9373b06..387a8745c 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.sct
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.sct
@@ -1,3 +1,9 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
+; command above MUST be in first line (no comment above!)
+
+;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
+; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse
+
; NOTE: ARMv8-M MPU requires that each region must start on a 32 byte aligned
; address and the size of a region must be a multiple of 32 bytes.
;
@@ -19,7 +25,58 @@
; | Unprivileged Data |
; ---------------------
-LR_APP 0x00200000 ; load region
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00200000
+#define __ROM_SIZE 0x00200000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20200000
+#define __RAM_SIZE 0x00020000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+
+/* ----------------------------------------------------------------------------
+ Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE ( 8 )
+#else
+#define __STACKSEAL_SIZE ( 0 )
+#endif
+
+LR_APP __ROM_BASE __ROM_SIZE ; load region
{
ER_IROM_NS_PRIVILEGED +0 ALIGN 32
{
@@ -50,7 +107,7 @@ LR_APP 0x00200000 ; load region
{
}
- ER_IRAM_NS_PRIVILEGED 0x20200000 ALIGN 32
+ ER_IRAM_NS_PRIVILEGED __RAM_BASE ALIGN 32
{
*(privileged_data)
}
@@ -67,4 +124,20 @@ LR_APP 0x00200000 ; load region
ER_IRAM_NS_UNPRIVILEGED_ALIGN +0 ALIGN 32 EMPTY 0x0
{
}
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE ; Reserve empty region for heap
+ {
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE ; Reserve empty region for stack
+ {
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ STACKSEAL +0 EMPTY __STACKSEAL_SIZE ; Reserve empty region for stack seal immediately after stack
+ {
+ }
+#endif
}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvoptx b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvoptx
index 5d7cd2f50..bbc8f09a0 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvoptx
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvoptx
@@ -10,7 +10,7 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
- <tExt>*.txt; *.h; *.inc</tExt>
+ <tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
@@ -103,7 +103,7 @@
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
- <nTsel>16</nTsel>
+ <nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@@ -120,7 +120,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
- <Name>(6010=70,43,547,639,0)(6018=1091,145,1280,478,0)(6019=1091,137,1280,457,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=1022,0,1280,731,0)(6015=2837,586,3095,1208,1)(6003=2678,41,3260,577,1)(6000=-1,-1,-1,-1,0)</Name>
+ <Name>(6010=70,43,547,639,0)(6018=1091,145,1280,478,0)(6019=1091,137,1280,457,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=1022,0,1280,731,0)(6015=1278,242,1536,864,1)(6003=1966,270,2548,806,1)(6000=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@@ -135,7 +135,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
- <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF".\FVP\MPS2_Cortex-M\ARMCM33_DSP_FP_TZ_config.txt" -MA</Name>
+ <Name>-I -S -L"cpu0" -O528390 -C0 -MC".\VHT\VHT_MPS2_Cortex-M33.exe" -MF"..\VHT_MPS2_Cortex-M33-config.txt" -PF -MA</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@@ -143,40 +143,7 @@
<Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
- <Breakpoint>
- <Bp>
- <Number>0</Number>
- <Type>0</Type>
- <LineNumber>105</LineNumber>
- <EnabledFlag>1</EnabledFlag>
- <Address>2116472</Address>
- <ByteObject>0</ByteObject>
- <HtxType>0</HtxType>
- <ManyObjects>0</ManyObjects>
- <SizeOfObject>0</SizeOfObject>
- <BreakByAccess>0</BreakByAccess>
- <BreakIfRCount>1</BreakIfRCount>
- <Filename>&lt;2&gt;.\main_ns.c</Filename>
- <ExecCommand></ExecCommand>
- <Expression>\\FreeRTOSDemo_ns\main_ns.c\105</Expression>
- </Bp>
- <Bp>
- <Number>1</Number>
- <Type>0</Type>
- <LineNumber>67</LineNumber>
- <EnabledFlag>1</EnabledFlag>
- <Address>2044</Address>
- <ByteObject>0</ByteObject>
- <HtxType>0</HtxType>
- <ManyObjects>0</ManyObjects>
- <SizeOfObject>0</SizeOfObject>
- <BreakByAccess>0</BreakByAccess>
- <BreakIfRCount>1</BreakIfRCount>
- <Filename>&lt;1&gt;.\main_s.c</Filename>
- <ExecCommand></ExecCommand>
- <Expression>\\FreeRTOSDemo_s\main_s.c\67</Expression>
- </Bp>
- </Breakpoint>
+ <Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
@@ -472,7 +439,7 @@
<Group>
<GroupName>User</GroupName>
- <tvExp>1</tvExp>
+ <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvprojx
index 4edbd14c6..88ad64e9d 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvprojx
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvprojx
@@ -10,13 +10,13 @@
<TargetName>FVP Simulation Model</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
- <pCCUsed>6130001::V6.13.1::.\ARMCLANG</pCCUsed>
+ <pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM33_DSP_FP_TZ</Device>
<Vendor>ARM</Vendor>
- <PackID>ARM.CMSIS.5.6.0</PackID>
+ <PackID>ARM.CMSIS.5.9.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@@ -185,6 +185,8 @@
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
+ <RvdsCdeCp>0</RvdsCdeCp>
+ <nBranchProt>0</nBranchProt>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2>
<StupSel>16</StupSel>
@@ -312,7 +314,7 @@
</ArmAdsMisc>
<Cads>
<interw>1</interw>
- <Optim>2</Optim>
+ <Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
@@ -351,7 +353,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
- <uClangAs>0</uClangAs>
+ <ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@@ -512,14 +514,14 @@
<RTE>
<apis/>
<components>
- <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.0" condition="ARMv6_7_8-M Device">
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
- <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS">
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS">
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
@@ -538,26 +540,38 @@
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
<targetInfos/>
</file>
- <file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.0">
- <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
- <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+ <file attr="config" category="linkerScript" condition="Startup ARMCC6 Unsecure" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6.sct" version="1.1.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
- <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
- <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
+ <file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.0">
+ <instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC6" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.S" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.S</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.3.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.1.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
- <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
@@ -625,4 +639,13 @@
</files>
</RTE>
+ <LayerInfo>
+ <Layers>
+ <Layer>
+ <LayName>FreeRTOSDemo_ns</LayName>
+ <LayPrjMark>1</LayPrjMark>
+ </Layer>
+ </Layers>
+ </LayerInfo>
+
</Project>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
deleted file mode 100644
index 9f104f57f..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
+++ /dev/null
@@ -1,1260 +0,0 @@
-/**************************************************************************//**
- * @file partition_ARMCM33.h
- * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version V5.0.1
- * @date 07. December 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef PARTITION_ARMCM33_H
-#define PARTITION_ARMCM33_H
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
-*/
-
-/*
-// <e>Initialize Security Attribution Unit (SAU) CTRL register
-*/
-#define SAU_INIT_CTRL 1
-
-/*
-// <q> Enable SAU
-// <i> Value for SAU->CTRL register bit ENABLE
-*/
-#define SAU_INIT_CTRL_ENABLE 1
-
-/*
-// <o> When SAU is disabled
-// <0=> All Memory is Secure
-// <1=> All Memory is Non-Secure
-// <i> Value for SAU->CTRL register bit ALLNS
-// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
-*/
-#define SAU_INIT_CTRL_ALLNS 0
-
-/*
-// </e>
-*/
-
-/*
-// <h>Initialize Security Attribution Unit (SAU) Address Regions
-// <i>SAU configuration specifies regions to be one of:
-// <i> - Secure and Non-Secure Callable
-// <i> - Non-Secure
-// <i>Note: All memory regions not configured by SAU are Secure
-*/
-#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
-
-/*
-// <e>Initialize SAU Region 0
-// <i> Setup SAU Region 0 memory attributes
-*/
-#define SAU_INIT_REGION0 1
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC0 1
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 1
-// <i> Setup SAU Region 1 memory attributes
-*/
-#define SAU_INIT_REGION1 1
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START1 0x00200000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END1 0x003FFFFF
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC1 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 2
-// <i> Setup SAU Region 2 memory attributes
-*/
-#define SAU_INIT_REGION2 1
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START2 0x20200000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END2 0x203FFFFF
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC2 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 3
-// <i> Setup SAU Region 3 memory attributes
-*/
-#define SAU_INIT_REGION3 1
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START3 0x40000000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END3 0x40040000
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC3 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 4
-// <i> Setup SAU Region 4 memory attributes
-*/
-#define SAU_INIT_REGION4 0
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC4 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 5
-// <i> Setup SAU Region 5 memory attributes
-*/
-#define SAU_INIT_REGION5 0
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START5 0x00000000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END5 0x00000000
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC5 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 6
-// <i> Setup SAU Region 6 memory attributes
-*/
-#define SAU_INIT_REGION6 0
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START6 0x00000000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END6 0x00000000
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC6 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 7
-// <i> Setup SAU Region 7 memory attributes
-*/
-#define SAU_INIT_REGION7 0
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START7 0x00000000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END7 0x00000000
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC7 0
-/*
-// </e>
-*/
-
-/*
-// </h>
-*/
-
-/*
-// <e>Setup behaviour of Sleep and Exception Handling
-*/
-#define SCB_CSR_AIRCR_INIT 1
-
-/*
-// <o> Deep Sleep can be enabled by
-// <0=>Secure and Non-Secure state
-// <1=>Secure state only
-// <i> Value for SCB->CSR register bit DEEPSLEEPS
-*/
-#define SCB_CSR_DEEPSLEEPS_VAL 1
-
-/*
-// <o>System reset request accessible from
-// <0=> Secure and Non-Secure state
-// <1=> Secure state only
-// <i> Value for SCB->AIRCR register bit SYSRESETREQS
-*/
-#define SCB_AIRCR_SYSRESETREQS_VAL 1
-
-/*
-// <o>Priority of Non-Secure exceptions is
-// <0=> Not altered
-// <1=> Lowered to 0x80-0xFF
-// <i> Value for SCB->AIRCR register bit PRIS
-*/
-#define SCB_AIRCR_PRIS_VAL 1
-
-/*
-// <o>BusFault, HardFault, and NMI target
-// <0=> Secure state
-// <1=> Non-Secure state
-// <i> Value for SCB->AIRCR register bit BFHFNMINS
-*/
-#define SCB_AIRCR_BFHFNMINS_VAL 1
-
-/*
-// </e>
-*/
-
-/*
-// <e>Setup behaviour of Floating Point Unit
-*/
-#define TZ_FPU_NS_USAGE 1
-
-/*
-// <o>Floating Point Unit usage
-// <0=> Secure state only
-// <3=> Secure and Non-Secure state
-// <i> Value for SCB->NSACR register bits CP10, CP11
-*/
-#define SCB_NSACR_CP10_11_VAL 3
-
-/*
-// <o>Treat floating-point registers as Secure
-// <0=> Disabled
-// <1=> Enabled
-// <i> Value for FPU->FPCCR register bit TS
-*/
-#define FPU_FPCCR_TS_VAL 0
-
-/*
-// <o>Clear on return (CLRONRET) accessibility
-// <0=> Secure and Non-Secure state
-// <1=> Secure state only
-// <i> Value for FPU->FPCCR register bit CLRONRETS
-*/
-#define FPU_FPCCR_CLRONRETS_VAL 0
-
-/*
-// <o>Clear floating-point caller saved registers on exception return
-// <0=> Disabled
-// <1=> Enabled
-// <i> Value for FPU->FPCCR register bit CLRONRET
-*/
-#define FPU_FPCCR_CLRONRET_VAL 1
-
-/*
-// </e>
-*/
-
-/*
-// <h>Setup Interrupt Target
-*/
-
-/*
-// <e>Initialize ITNS 0 (Interrupts 0..31)
-*/
-#define NVIC_INIT_ITNS0 1
-
-/*
-// Interrupts 0..31
-// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS0_VAL 0x0000122B
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 1 (Interrupts 32..63)
-*/
-#define NVIC_INIT_ITNS1 1
-
-/*
-// Interrupts 32..63
-// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS1_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 2 (Interrupts 64..95)
-*/
-#define NVIC_INIT_ITNS2 0
-
-/*
-// Interrupts 64..95
-// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS2_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 3 (Interrupts 96..127)
-*/
-#define NVIC_INIT_ITNS3 0
-
-/*
-// Interrupts 96..127
-// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS3_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 4 (Interrupts 128..159)
-*/
-#define NVIC_INIT_ITNS4 0
-
-/*
-// Interrupts 128..159
-// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS4_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 5 (Interrupts 160..191)
-*/
-#define NVIC_INIT_ITNS5 0
-
-/*
-// Interrupts 160..191
-// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS5_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 6 (Interrupts 192..223)
-*/
-#define NVIC_INIT_ITNS6 0
-
-/*
-// Interrupts 192..223
-// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS6_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 7 (Interrupts 224..255)
-*/
-#define NVIC_INIT_ITNS7 0
-
-/*
-// Interrupts 224..255
-// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS7_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8 0
-
-/*
-// Interrupts 0..31
-// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9 0
-
-/*
-// Interrupts 32..63
-// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10 0
-
-/*
-// Interrupts 64..95
-// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11 0
-
-/*
-// Interrupts 96..127
-// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12 0
-
-/*
-// Interrupts 128..159
-// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13 0
-
-/*
-// Interrupts 160..191
-// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14 0
-
-/*
-// Interrupts 192..223
-// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15 0
-
-/*
-// Interrupts 224..255
-// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// </h>
-*/
-
-
-
-/*
- max 128 SAU regions.
- SAU regions are defined in partition.h
- */
-
-#define SAU_INIT_REGION(n) \
- SAU->RNR = (n & SAU_RNR_REGION_Msk); \
- SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
- SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
- ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
-
-/**
- \brief Setup a SAU Region
- \details Writes the region information contained in SAU_Region to the
- registers SAU_RNR, SAU_RBAR, and SAU_RLAR
- */
-__STATIC_INLINE void TZ_SAU_Setup (void)
-{
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-
- #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
- SAU_INIT_REGION(0);
- #endif
-
- #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
- SAU_INIT_REGION(1);
- #endif
-
- #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
- SAU_INIT_REGION(2);
- #endif
-
- #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
- SAU_INIT_REGION(3);
- #endif
-
- #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
- SAU_INIT_REGION(4);
- #endif
-
- #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
- SAU_INIT_REGION(5);
- #endif
-
- #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
- SAU_INIT_REGION(6);
- #endif
-
- #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
- SAU_INIT_REGION(7);
- #endif
-
- /* repeat this for all possible SAU regions */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-
- #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
- SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
- ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
- #endif
-
- #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
- SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
- ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
-
- SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
- SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
- ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
- ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
- ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
- ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
- #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
-
- #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
- defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
-
- SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |
- ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
-
- FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
- ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
- ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
- ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
- #endif
-
- #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
- NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
- NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
- NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
- NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
- NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
- NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
- NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
- NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
- NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
- NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
- NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
- NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
- NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
- NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
- NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
- NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
- #endif
-
- /* repeat this for all possible ITNS elements */
-
-}
-
-#endif /* PARTITION_ARMCM33_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s
deleted file mode 100644
index bbba5e35b..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s
+++ /dev/null
@@ -1,267 +0,0 @@
-;/**************************************************************************//**
-; * @file startup_ARMCM33.s
-; * @brief CMSIS Core Device Startup File for
-; * ARMCM33 Device Series
-; * @version V5.00
-; * @date 21. October 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000C00
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD SecureFault_Handler ; Secure Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SecureFault_Handler\
- PROC
- EXPORT SecureFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
-
- ENDP
-
-
- ALIGN
-
-
-; User Initial Stack & Heap
-
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
- ENDIF
-
-
- END
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
deleted file mode 100644
index 9d13d545c..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/**************************************************************************//**
- * @file system_ARMCM33.c
- * @brief CMSIS Device System Source File for
- * ARMCM33 Device Series
- * @version V5.00
- * @date 02. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined (ARMCM33)
- #include "ARMCM33.h"
-#elif defined (ARMCM33_TZ)
- #include "ARMCM33_TZ.h"
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #include "partition_ARMCM33.h"
- #endif
-#elif defined (ARMCM33_DSP_FP)
- #include "ARMCM33_DSP_FP.h"
-#elif defined (ARMCM33_DSP_FP_TZ)
- #include "ARMCM33_DSP_FP_TZ.h"
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #include "partition_ARMCM33.h"
- #endif
-#else
- #error device not specified!
-#endif
-
-/*----------------------------------------------------------------------------
- Define clocks
- *----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
-
-#define SYSTEM_CLOCK (5U * XTAL)
-
-
-/*----------------------------------------------------------------------------
- Externals
- *----------------------------------------------------------------------------*/
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- extern uint32_t __Vectors;
-#endif
-
-/*----------------------------------------------------------------------------
- System Core Clock Variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
-
-
-/*----------------------------------------------------------------------------
- System Core Clock update function
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)
-{
- SystemCoreClock = SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
- System initialization function
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-
-#if defined (__FPU_USED) && (__FPU_USED == 1U)
- SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
- (3U << 11U*2U) ); /* set CP11 Full Access */
-#endif
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
- SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- TZ_SAU_Setup();
-#endif
-
- SystemCoreClock = SYSTEM_CLOCK;
-}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/ReadMe.txt b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/ReadMe.txt
index d2d6653e8..5c82c33e7 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/ReadMe.txt
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/ReadMe.txt
@@ -1,3 +1,10 @@
+Prerequisites:
+- Keil MDK release 5.38a or 5.37
+
+Notes:
+The demo has been updated to work with latest MDK release 5.38a. From Keil MDK version 5.37, Arm Virtual Hardware (AVH)
+models Version 11.17.40 are replacing the FVP models.
+
Instructions to Build and Run:
- The Keil multi-project workspace FreeRTOSDemo.uvmpw contains projects for both the secure project, and non secure project.
- Set the FreeRTOSDemo_s project as Active - Right click on "Project: FreeRTOSDemo_s" and select "Set as Active Project".
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.sct b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.sct
index 1895482ff..bb29029a8 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.sct
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.sct
@@ -1,8 +1,60 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse
+; command above MUST be in first line (no comment above!)
-LR_IROM_S 0x00000000 0x00200000 ; load region size_region
+;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
+; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse
+
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00200000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00020000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
+
+/* ----------------------------------------------------------------------------
+ Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE ( 8 )
+#else
+#define __STACKSEAL_SIZE ( 0 )
+#endif
+
+LR_IROM_S __ROM_BASE __ROM_SIZE ; load region size_region
{
ER_IROM_S +0 ; load address = execution address
{
@@ -13,8 +65,18 @@ LR_IROM_S 0x00000000 0x00200000 ; load region size_region
.ANY (+XO)
}
- RW_IRAM_S 0x20000000 0x00020000 ; RW data
+ RW_IRAM_S __RAM_BASE __RAM_SIZE ; RW data
{
.ANY (+RW +ZI)
}
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE ; Reserve empty region for stack
+ {
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ STACKSEAL +0 EMPTY __STACKSEAL_SIZE ; Reserve empty region for stack seal immediately after stack
+ {
+ }
+#endif
}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvoptx b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvoptx
index ac87fd034..6cf31dae5 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvoptx
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvoptx
@@ -10,7 +10,7 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
- <tExt>*.txt; *.h; *.inc</tExt>
+ <tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
@@ -73,7 +73,7 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
- <tvExp>0</tvExp>
+ <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
@@ -103,7 +103,7 @@
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
- <nTsel>16</nTsel>
+ <nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@@ -135,7 +135,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
- <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF".\FVP\MPS2_Cortex-M\ARMCM33_DSP_FP_TZ_config.txt" -MA</Name>
+ <Name>-I -S -L"cpu0" -O528390 -C0 -MC".\VHT\VHT_MPS2_Cortex-M33.exe" -MF"..\VHT_MPS2_Cortex-M33-config.txt" -PF -MA</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvprojx
index 220ee39be..e779cecaa 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvprojx
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvprojx
@@ -10,13 +10,13 @@
<TargetName>FVP Simulation Model</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
- <pCCUsed>6130001::V6.13.1::.\ARMCLANG</pCCUsed>
+ <pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM33_DSP_FP_TZ</Device>
<Vendor>ARM</Vendor>
- <PackID>ARM.CMSIS.5.6.0</PackID>
+ <PackID>ARM.CMSIS.5.9.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@@ -185,6 +185,8 @@
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
+ <RvdsCdeCp>0</RvdsCdeCp>
+ <nBranchProt>0</nBranchProt>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2>
<StupSel>8</StupSel>
@@ -312,7 +314,7 @@
</ArmAdsMisc>
<Cads>
<interw>1</interw>
- <Optim>2</Optim>
+ <Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
@@ -351,7 +353,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
- <uClangAs>0</uClangAs>
+ <ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@@ -472,40 +474,54 @@
<RTE>
<apis/>
<components>
- <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.0" condition="ARMv6_7_8-M Device">
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
- <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS">
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS">
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
</components>
<files>
- <file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.0">
+ <file attr="config" category="linkerScript" condition="Startup ARMCC6 Secure" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6_s.sct" version="1.1.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6_s.sct</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="header" condition="TZ Secure" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
- <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
- <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
- <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
- <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+ <file attr="config" category="sourceAsm" condition="ARMCC6" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.S" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.S</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.3.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.1.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
- <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
+ <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
deleted file mode 100644
index 3a0f2e139..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
+++ /dev/null
@@ -1,1260 +0,0 @@
-/**************************************************************************//**
- * @file partition_ARMCM33.h
- * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version V5.0.1
- * @date 07. December 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef PARTITION_ARMCM33_H
-#define PARTITION_ARMCM33_H
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
-*/
-
-/*
-// <e>Initialize Security Attribution Unit (SAU) CTRL register
-*/
-#define SAU_INIT_CTRL 1
-
-/*
-// <q> Enable SAU
-// <i> Value for SAU->CTRL register bit ENABLE
-*/
-#define SAU_INIT_CTRL_ENABLE 1
-
-/*
-// <o> When SAU is disabled
-// <0=> All Memory is Secure
-// <1=> All Memory is Non-Secure
-// <i> Value for SAU->CTRL register bit ALLNS
-// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
-*/
-#define SAU_INIT_CTRL_ALLNS 0
-
-/*
-// </e>
-*/
-
-/*
-// <h>Initialize Security Attribution Unit (SAU) Address Regions
-// <i>SAU configuration specifies regions to be one of:
-// <i> - Secure and Non-Secure Callable
-// <i> - Non-Secure
-// <i>Note: All memory regions not configured by SAU are Secure
-*/
-#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
-
-/*
-// <e>Initialize SAU Region 0
-// <i> Setup SAU Region 0 memory attributes
-*/
-#define SAU_INIT_REGION0 1
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC0 1
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 1
-// <i> Setup SAU Region 1 memory attributes
-*/
-#define SAU_INIT_REGION1 1
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START1 0x00200000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END1 0x003FFFFF
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC1 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 2
-// <i> Setup SAU Region 2 memory attributes
-*/
-#define SAU_INIT_REGION2 1
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START2 0x20200000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END2 0x203FFFFF
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC2 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 3
-// <i> Setup SAU Region 3 memory attributes
-*/
-#define SAU_INIT_REGION3 1
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START3 0x40000000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END3 0x40040000
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC3 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 4
-// <i> Setup SAU Region 4 memory attributes
-*/
-#define SAU_INIT_REGION4 0
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC4 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 5
-// <i> Setup SAU Region 5 memory attributes
-*/
-#define SAU_INIT_REGION5 0
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START5 0x00000000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END5 0x00000000
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC5 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 6
-// <i> Setup SAU Region 6 memory attributes
-*/
-#define SAU_INIT_REGION6 0
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START6 0x00000000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END6 0x00000000
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC6 0
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize SAU Region 7
-// <i> Setup SAU Region 7 memory attributes
-*/
-#define SAU_INIT_REGION7 0
-
-/*
-// <o>Start Address <0-0xFFFFFFE0>
-*/
-#define SAU_INIT_START7 0x00000000
-
-/*
-// <o>End Address <0x1F-0xFFFFFFFF>
-*/
-#define SAU_INIT_END7 0x00000000
-
-/*
-// <o>Region is
-// <0=>Non-Secure
-// <1=>Secure, Non-Secure Callable
-*/
-#define SAU_INIT_NSC7 0
-/*
-// </e>
-*/
-
-/*
-// </h>
-*/
-
-/*
-// <e>Setup behaviour of Sleep and Exception Handling
-*/
-#define SCB_CSR_AIRCR_INIT 1
-
-/*
-// <o> Deep Sleep can be enabled by
-// <0=>Secure and Non-Secure state
-// <1=>Secure state only
-// <i> Value for SCB->CSR register bit DEEPSLEEPS
-*/
-#define SCB_CSR_DEEPSLEEPS_VAL 1
-
-/*
-// <o>System reset request accessible from
-// <0=> Secure and Non-Secure state
-// <1=> Secure state only
-// <i> Value for SCB->AIRCR register bit SYSRESETREQS
-*/
-#define SCB_AIRCR_SYSRESETREQS_VAL 1
-
-/*
-// <o>Priority of Non-Secure exceptions is
-// <0=> Not altered
-// <1=> Lowered to 0x80-0xFF
-// <i> Value for SCB->AIRCR register bit PRIS
-*/
-#define SCB_AIRCR_PRIS_VAL 1
-
-/*
-// <o>BusFault, HardFault, and NMI target
-// <0=> Secure state
-// <1=> Non-Secure state
-// <i> Value for SCB->AIRCR register bit BFHFNMINS
-*/
-#define SCB_AIRCR_BFHFNMINS_VAL 0
-
-/*
-// </e>
-*/
-
-/*
-// <e>Setup behaviour of Floating Point Unit
-*/
-#define TZ_FPU_NS_USAGE 1
-
-/*
-// <o>Floating Point Unit usage
-// <0=> Secure state only
-// <3=> Secure and Non-Secure state
-// <i> Value for SCB->NSACR register bits CP10, CP11
-*/
-#define SCB_NSACR_CP10_11_VAL 3
-
-/*
-// <o>Treat floating-point registers as Secure
-// <0=> Disabled
-// <1=> Enabled
-// <i> Value for FPU->FPCCR register bit TS
-*/
-#define FPU_FPCCR_TS_VAL 0
-
-/*
-// <o>Clear on return (CLRONRET) accessibility
-// <0=> Secure and Non-Secure state
-// <1=> Secure state only
-// <i> Value for FPU->FPCCR register bit CLRONRETS
-*/
-#define FPU_FPCCR_CLRONRETS_VAL 0
-
-/*
-// <o>Clear floating-point caller saved registers on exception return
-// <0=> Disabled
-// <1=> Enabled
-// <i> Value for FPU->FPCCR register bit CLRONRET
-*/
-#define FPU_FPCCR_CLRONRET_VAL 1
-
-/*
-// </e>
-*/
-
-/*
-// <h>Setup Interrupt Target
-*/
-
-/*
-// <e>Initialize ITNS 0 (Interrupts 0..31)
-*/
-#define NVIC_INIT_ITNS0 1
-
-/*
-// Interrupts 0..31
-// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS0_VAL 0x0000122B
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 1 (Interrupts 32..63)
-*/
-#define NVIC_INIT_ITNS1 1
-
-/*
-// Interrupts 32..63
-// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS1_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 2 (Interrupts 64..95)
-*/
-#define NVIC_INIT_ITNS2 0
-
-/*
-// Interrupts 64..95
-// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS2_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 3 (Interrupts 96..127)
-*/
-#define NVIC_INIT_ITNS3 0
-
-/*
-// Interrupts 96..127
-// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS3_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 4 (Interrupts 128..159)
-*/
-#define NVIC_INIT_ITNS4 0
-
-/*
-// Interrupts 128..159
-// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS4_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 5 (Interrupts 160..191)
-*/
-#define NVIC_INIT_ITNS5 0
-
-/*
-// Interrupts 160..191
-// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS5_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 6 (Interrupts 192..223)
-*/
-#define NVIC_INIT_ITNS6 0
-
-/*
-// Interrupts 192..223
-// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS6_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 7 (Interrupts 224..255)
-*/
-#define NVIC_INIT_ITNS7 0
-
-/*
-// Interrupts 224..255
-// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS7_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8 0
-
-/*
-// Interrupts 0..31
-// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9 0
-
-/*
-// Interrupts 32..63
-// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10 0
-
-/*
-// Interrupts 64..95
-// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11 0
-
-/*
-// Interrupts 96..127
-// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12 0
-
-/*
-// Interrupts 128..159
-// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13 0
-
-/*
-// Interrupts 160..191
-// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14 0
-
-/*
-// Interrupts 192..223
-// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15 0
-
-/*
-// Interrupts 224..255
-// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// </h>
-*/
-
-
-
-/*
- max 128 SAU regions.
- SAU regions are defined in partition.h
- */
-
-#define SAU_INIT_REGION(n) \
- SAU->RNR = (n & SAU_RNR_REGION_Msk); \
- SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
- SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
- ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
-
-/**
- \brief Setup a SAU Region
- \details Writes the region information contained in SAU_Region to the
- registers SAU_RNR, SAU_RBAR, and SAU_RLAR
- */
-__STATIC_INLINE void TZ_SAU_Setup (void)
-{
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-
- #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
- SAU_INIT_REGION(0);
- #endif
-
- #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
- SAU_INIT_REGION(1);
- #endif
-
- #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
- SAU_INIT_REGION(2);
- #endif
-
- #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
- SAU_INIT_REGION(3);
- #endif
-
- #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
- SAU_INIT_REGION(4);
- #endif
-
- #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
- SAU_INIT_REGION(5);
- #endif
-
- #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
- SAU_INIT_REGION(6);
- #endif
-
- #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
- SAU_INIT_REGION(7);
- #endif
-
- /* repeat this for all possible SAU regions */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-
- #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
- SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
- ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
- #endif
-
- #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
- SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
- ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
-
- SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
- SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
- ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
- ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
- ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
- ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
- #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
-
- #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
- defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
-
- SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |
- ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
-
- FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
- ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
- ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
- ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
- #endif
-
- #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
- NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
- NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
- NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
- NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
- NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
- NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
- NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
- NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
- NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
- NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
- NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
- NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
- NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
- NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
- NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
- NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
- #endif
-
- /* repeat this for all possible ITNS elements */
-
-}
-
-#endif /* PARTITION_ARMCM33_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s
deleted file mode 100644
index bbba5e35b..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s
+++ /dev/null
@@ -1,267 +0,0 @@
-;/**************************************************************************//**
-; * @file startup_ARMCM33.s
-; * @brief CMSIS Core Device Startup File for
-; * ARMCM33 Device Series
-; * @version V5.00
-; * @date 21. October 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000C00
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD SecureFault_Handler ; Secure Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SecureFault_Handler\
- PROC
- EXPORT SecureFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
-
- ENDP
-
-
- ALIGN
-
-
-; User Initial Stack & Heap
-
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
- ENDIF
-
-
- END
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
deleted file mode 100644
index 9d13d545c..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/**************************************************************************//**
- * @file system_ARMCM33.c
- * @brief CMSIS Device System Source File for
- * ARMCM33 Device Series
- * @version V5.00
- * @date 02. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined (ARMCM33)
- #include "ARMCM33.h"
-#elif defined (ARMCM33_TZ)
- #include "ARMCM33_TZ.h"
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #include "partition_ARMCM33.h"
- #endif
-#elif defined (ARMCM33_DSP_FP)
- #include "ARMCM33_DSP_FP.h"
-#elif defined (ARMCM33_DSP_FP_TZ)
- #include "ARMCM33_DSP_FP_TZ.h"
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #include "partition_ARMCM33.h"
- #endif
-#else
- #error device not specified!
-#endif
-
-/*----------------------------------------------------------------------------
- Define clocks
- *----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
-
-#define SYSTEM_CLOCK (5U * XTAL)
-
-
-/*----------------------------------------------------------------------------
- Externals
- *----------------------------------------------------------------------------*/
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- extern uint32_t __Vectors;
-#endif
-
-/*----------------------------------------------------------------------------
- System Core Clock Variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
-
-
-/*----------------------------------------------------------------------------
- System Core Clock update function
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)
-{
- SystemCoreClock = SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
- System initialization function
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-
-#if defined (__FPU_USED) && (__FPU_USED == 1U)
- SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
- (3U << 11U*2U) ); /* set CP11 Full Access */
-#endif
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
- SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- TZ_SAU_Setup();
-#endif
-
- SystemCoreClock = SYSTEM_CLOCK;
-}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/VHT_MPS2_Cortex-M33-config.txt b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/VHT_MPS2_Cortex-M33-config.txt
new file mode 100644
index 000000000..04e32d1f2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/VHT_MPS2_Cortex-M33-config.txt
@@ -0,0 +1,24 @@
+# Parameters:
+# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
+#----------------------------------------------------------------------------------------------
+cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
+cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
+cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
+cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
+cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
+cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
+cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
+cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
+cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
+cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
+cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
+cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
+cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
+idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
+cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
+cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
+cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
+cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
+cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
+fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
+#----------------------------------------------------------------------------------------------
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