diff options
| author | gaurav-aws <gaurav-aws@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2020-01-12 12:33:17 +0000 |
|---|---|---|
| committer | gaurav-aws <gaurav-aws@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2020-01-12 12:33:17 +0000 |
| commit | bb4ffb99ad8167a5ee63454ac29dc08eccfa8ede (patch) | |
| tree | 9d68367693f1b58d9e70dd65e70a5ed0be1441cb | |
| parent | 50ff3134dc87e8a059ea6f4a8cefdb85f2f6fd17 (diff) | |
| download | freertos-bb4ffb99ad8167a5ee63454ac29dc08eccfa8ede.tar.gz | |
Add MPU demo project for LPC54018 board.
git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2803 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
70 files changed, 67783 insertions, 0 deletions
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h new file mode 100644 index 000000000..f2aa78e88 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ ( SystemCoreClock )
+#define configTICK_RATE_HZ ( ( TickType_t ) 200 )
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 256 )
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c). */
+#define configFRTOS_MEMORY_SCHEME 4
+
+/* Tasks.c additions (e.g. Thread Aware Debug capability). */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ( ( size_t )( 10 * 1024 ) )
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency. */
+ #include <stdint.h>
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 3 /* 8 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+/* Ensure that system calls can only be made from kernel code. */
+#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 1
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c new file mode 100644 index 000000000..6d8e06739 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c @@ -0,0 +1,138 @@ +/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* BSP includes. */
+#include "board.h"
+#include "pin_mux.h"
+
+/* Demo includes. */
+#include "mpu_demo.h"
+
+/**
+ * @brief Performs board specific initialization.
+ */
+static void prvInitHardware( void );
+/*-----------------------------------------------------------*/
+
+static void prvInitHardware( void )
+{
+ /* Attach 12 MHz clock to FLEXCOMM0 (debug console). */
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+ BOARD_InitPins();
+ BOARD_BootClockPLL180M();
+ BOARD_InitDebugConsole();
+}
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+ /* Initialize hardware. */
+ prvInitHardware();
+
+ /* Start the MPU demo. */
+ vStartMPUDemo();
+
+ /* Start the scheduler. */
+ vTaskStartScheduler();
+
+ /* Should not get here. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+ /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this
+ function will automatically get called if a task overflows its stack. */
+ ( void ) pxTask;
+ ( void ) pcTaskName;
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will
+ be called automatically if a call to pvPortMalloc() fails. pvPortMalloc()
+ is called automatically when a task, queue or semaphore is created. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
+implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
+used by the Idle task. */
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+{
+/* If the buffers to be provided to the Idle task are declared inside this
+function then they must be declared static - otherwise they will be allocated on
+the stack and so not exists after this function exits. */
+static StaticTask_t xIdleTaskTCB;
+static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
+ state will be stored. */
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+ /* Pass out the array that will be used as the Idle task's stack. */
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+ Note that, as the array is necessarily of type StackType_t,
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+/*-----------------------------------------------------------*/
+
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
+application must provide an implementation of vApplicationGetTimerTaskMemory()
+to provide the memory that is used by the Timer service task. */
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
+{
+/* If the buffers to be provided to the Timer task are declared inside this
+function then they must be declared static - otherwise they will be allocated on
+the stack and so not exists after this function exits. */
+static StaticTask_t xTimerTaskTCB;
+static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
+
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer
+ task's state will be stored. */
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+
+ /* Pass out the array that will be used as the Timer task's stack. */
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;
+
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
+ Note that, as the array is necessarily of type StackType_t,
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c new file mode 100644 index 000000000..039439a91 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c @@ -0,0 +1,301 @@ +/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/** ARMv7 MPU Details:
+ *
+ * - ARMv7 MPU requires that the size of a MPU region is a power of 2.
+ * - Smallest supported region size is 32 bytes.
+ * - Start address of a region must be aligned to an integer multiple of the
+ * region size. For example, if the region size is 4 KB(0x1000), the starting
+ * address must be N x 0x1000, where N is an integer.
+ */
+
+/**
+ * @brief Size of the shared memory region.
+ */
+#define SHARED_MEMORY_SIZE 32
+
+/**
+ * @brief Memory region shared between two tasks.
+ */
+static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) );
+
+/**
+ * @brief Memory region used to track Memory Fault intentionally caused by the
+ * RO Access task.
+ *
+ * RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal
+ * memory. Illegal memory access causes Memory Fault and the fault handler
+ * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We
+ * recover gracefully from an expected fault by jumping to the next instruction.
+ *
+ * @note We are declaring a region of 32 bytes even though we need only one.
+ * The reason is that the smallest supported MPU region size is 32 bytes.
+ */
+static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ) = { 0 };
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Implements the task which has Read Only access to the memory region
+ * ucSharedMemory.
+ *
+ * @param pvParameters[in] Parameters as passed during task creation.
+ */
+static void prvROAccessTask( void * pvParameters );
+
+/**
+ * @brief Implements the task which has Read Write access to the memory region
+ * ucSharedMemory.
+ *
+ * @param pvParameters[in] Parameters as passed during task creation.
+ */
+static void prvRWAccessTask( void * pvParameters );
+
+/*-----------------------------------------------------------*/
+
+static void prvROAccessTask( void * pvParameters )
+{
+uint8_t ucVal;
+
+ /* Unused parameters. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* This task has RO access to ucSharedMemory and therefore it can read
+ * it but cannot modify it. */
+ ucVal = ucSharedMemory[ 0 ];
+
+ /* Silent compiler warnings about unused variables. */
+ ( void ) ucVal;
+
+ /* Since this task has Read Only access to the ucSharedMemory region,
+ * writing to it results in Memory Fault. Set ucROTaskFaultTracker[ 0 ]
+ * to 1 to tell the Memory Fault Handler that this is an expected fault.
+ * The handler will recover from this fault gracefully by jumping to the
+ * next instruction. */
+ ucROTaskFaultTracker[ 0 ] = 1;
+
+ /* Illegal access to generate Memory Fault. */
+ ucSharedMemory[ 0 ] = 0;
+
+ /* Ensure that the above line did generate MemFault and the fault
+ * handler did clear the ucROTaskFaultTracker[ 0 ]. */
+ configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );
+
+ #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+ {
+ /* Generate an SVC to raise the privilege. Since privilege
+ * escalation is only allowed from kernel code, this request must
+ * get rejected and the task must remain unprivileged. As a result,
+ * trying to write to ucSharedMemory will still result in Memory
+ * Fault. */
+ portRAISE_PRIVILEGE();
+
+ /* Set ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault
+ * Handler that this is an expected fault. The handler will then be
+ * able to recover from this fault gracefully by jumping to the
+ * next instruction.*/
+ ucROTaskFaultTracker[ 0 ] = 1;
+
+ /* The following must still result in Memory Fault since the task
+ * is still running unprivileged. */
+ ucSharedMemory[ 0 ] = 0;
+
+ /* Ensure that the above line did generate MemFault and the fault
+ * handler did clear the ucROTaskFaultTracker[ 0 ]. */
+ configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );
+ }
+ #else
+ {
+ /* Generate an SVC to raise the privilege. Since
+ * configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not enabled, the
+ * task will be able to escalate privilege. */
+ portRAISE_PRIVILEGE();
+
+ /* At this point, the task is running privileged. The following
+ * access must not result in Memory Fault. If something goes
+ * wrong and we do get a fault, the execution will stop in fault
+ * handler as ucROTaskFaultTracker[ 0 ] is not set (i.e.
+ * un-expected fault). */
+ ucSharedMemory[ 0 ] = 0;
+
+ /* Lower down the privilege. */
+ portSWITCH_TO_USER_MODE();
+
+ /* Now the task is running unprivileged and therefore an attempt to
+ * write to ucSharedMemory will result in a Memory Fault. Set
+ * ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault Handler
+ * that this is an expected fault. The handler will then be able to
+ * recover from this fault gracefully by jumping to the next
+ * instruction.*/
+ ucROTaskFaultTracker[ 0 ] = 1;
+
+ /* The following must result in Memory Fault since the task is now
+ * running unprivileged. */
+ ucSharedMemory[ 0 ] = 0;
+
+ /* Ensure that the above line did generate MemFault and the fault
+ * handler did clear the ucROTaskFaultTracker[ 0 ]. */
+ configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );
+ }
+ #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+ /* Wait for a second. */
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvRWAccessTask( void * pvParameters )
+{
+ /* Unused parameters. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* This task has RW access to ucSharedMemory and therefore can write to
+ * it. */
+ ucSharedMemory[ 0 ] = 0;
+
+ /* Wait for a second. */
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vStartMPUDemo( void )
+{
+/**
+ * Since stack of a task is protected using MPU, it must satisfy MPU
+ * requirements as mentioned at the top of this file.
+ */
+static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );
+static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );
+TaskParameters_t xROAccessTaskParameters =
+{
+ .pvTaskCode = prvROAccessTask,
+ .pcName = "ROAccess",
+ .usStackDepth = configMINIMAL_STACK_SIZE,
+ .pvParameters = NULL,
+ .uxPriority = tskIDLE_PRIORITY,
+ .puxStackBuffer = xROAccessTaskStack,
+ .xRegions = {
+ { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY | portMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucROTaskFaultTracker, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER },
+ { 0, 0, 0 },
+ }
+};
+TaskParameters_t xRWAccessTaskParameters =
+{
+ .pvTaskCode = prvRWAccessTask,
+ .pcName = "RWAccess",
+ .usStackDepth = configMINIMAL_STACK_SIZE,
+ .pvParameters = NULL,
+ .uxPriority = tskIDLE_PRIORITY,
+ .puxStackBuffer = xRWAccessTaskStack,
+ .xRegions = {
+ { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER},
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ }
+};
+
+ /* Create an unprivileged task with RO access to ucSharedMemory. */
+ xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL );
+
+ /* Create an unprivileged task with RW access to ucSharedMemory. */
+ xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL );
+}
+/*-----------------------------------------------------------*/
+
+portDONT_DISCARD void vHandleMemoryFault( uint32_t * pulFaultStackAddress )
+{
+uint32_t ulPC;
+uint16_t usOffendingInstruction;
+
+ /* Is this an expected fault? */
+ if( ucROTaskFaultTracker[ 0 ] == 1 )
+ {
+ /* Read program counter. */
+ ulPC = pulFaultStackAddress[ 6 ];
+
+ /* Read the offending instruction. */
+ usOffendingInstruction = *( uint16_t * )ulPC;
+
+ /* From ARM docs:
+ * If the value of bits[15:11] of the halfword being decoded is one of
+ * the following, the halfword is the first halfword of a 32-bit
+ * instruction:
+ * - 0b11101.
+ * - 0b11110.
+ * - 0b11111.
+ * Otherwise, the halfword is a 16-bit instruction.
+ */
+
+ /* Extract bits[15:11] of the offending instruction. */
+ usOffendingInstruction = usOffendingInstruction & 0xF800;
+ usOffendingInstruction = ( usOffendingInstruction >> 11 );
+
+ /* Determine if the offending instruction is a 32-bit instruction or
+ * a 16-bit instruction. */
+ if( usOffendingInstruction == 0x001F ||
+ usOffendingInstruction == 0x001E ||
+ usOffendingInstruction == 0x001D )
+ {
+ /* Since the offending instruction is a 32-bit instruction,
+ * increment the program counter by 4 to move to the next
+ * instruction. */
+ ulPC += 4;
+ }
+ else
+ {
+ /* Since the offending instruction is a 16-bit instruction,
+ * increment the program counter by 2 to move to the next
+ * instruction. */
+ ulPC += 2;
+ }
+
+ /* Save the new program counter on the stack. */
+ pulFaultStackAddress[ 6 ] = ulPC;
+
+ /* Mark the fault as handled. */
+ ucROTaskFaultTracker[ 0 ] = 0;
+ }
+ else
+ {
+ /* This is an unexpected fault - loop forever. */
+ for( ; ; )
+ {
+ }
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h new file mode 100644 index 000000000..e62402761 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h @@ -0,0 +1,45 @@ +/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __MPU_DEMO_H__
+#define __MPU_DEMO_H__
+
+/**
+ * @brief Creates all the tasks for MPU demo.
+ *
+ * The MPU demo creates 2 unprivileged tasks - One of which has Read Only access
+ * to a shared memory region while the other has Read Write access. The task
+ * with Read Only access then tries to write to the shared memory which results
+ * in a Memory fault. The fault handler examines that it is the fault generated
+ * by the task with Read Only access and if so, it recovers from the fault
+ * greacefully by moving the Program Counter to the next instruction to the one
+ * which generated the fault. If any other memory access violation occurs, the
+ * fault handler will get stuck in an inifinite loop.
+ */
+void vStartMPUDemo( void );
+
+#endif /* __MPU_DEMO_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_common_tables.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_common_tables.h new file mode 100644 index 000000000..233f62357 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_common_tables.h
+ * Description: Extern declaration for common tables
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_const_structs.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_const_structs.h new file mode 100644 index 000000000..677073e59 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_const_structs.h
+ * Description: Constant structs that are initialized for user convenience.
+ * For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_math.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_math.h new file mode 100644 index 000000000..40788c52c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_math.h @@ -0,0 +1,7210 @@ +/******************************************************************************
+ * @file arm_math.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.6.0
+ * @date 18. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transform functions
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+ * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+ * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+ * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+ * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+ * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ *
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP\\Projects\\ARM</code> folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
+ *
+ * Preprocessor Macros
+ * ------------
+ *
+ * Each library project have different preprocessor macros.
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_LOOPUNROLL:
+ *
+ * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions
+ *
+ * <hr>
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+ * |File/Folder |Content |
+ * |---------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite |
+ * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP\\Include | DSP_Lib include files |
+ * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries |
+ * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries |
+ * |\b CMSIS\\DSP\\Source | DSP_Lib source files |
+ *
+ * <hr>
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15()
+ * for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+
+
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wsign-conversion"
+ #pragma GCC diagnostic ignored "-Wconversion"
+ #pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+
+#include "cmsis_compiler.h"
+#include "string.h"
+#include "math.h"
+
+/* evaluate ARM architecture */
+#if defined (__ARM_ARCH_6M__)
+ #define ARM_MATH_CM0_FAMILY 1
+#elif defined (__ARM_ARCH_7M__)
+//#define ARM_MATH_CM0_FAMILY 0
+#elif defined (__ARM_ARCH_7EM__)
+//#define ARM_MATH_CM0_FAMILY 0
+#elif defined (__ARM_ARCH_8M_BASE__)
+ #define ARM_MATH_CM0_FAMILY 1
+#elif defined (__ARM_ARCH_8M_MAIN__)
+//#define ARM_MATH_CM0_FAMILY 0
+#else
+ #error "Unknown Arm Architecture!"
+#endif
+
+/* evaluate ARM DSP feature */
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+ #define ARM_MATH_DSP 1
+#endif
+
+
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+
+/**
+ @brief definition to read/write two 16 bit values.
+ @deprecated
+ */
+#if defined ( __CC_ARM )
+ #define __SIMD32_TYPE int32_t __packed
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __GNUC__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __ICCARM__ )
+ #define __SIMD32_TYPE int32_t __packed
+#elif defined ( __TI_ARM__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __CSMC__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __TASKING__ )
+ #define __SIMD32_TYPE __unaligned int32_t
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
+#define __SIMD64(addr) (*( int64_t **) & (addr))
+
+/* SIMD replacement */
+
+/**
+ @brief Read 2 Q15 from Q15 pointer.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2 (
+ q15_t * pQ15)
+{
+ q31_t val;
+
+ memcpy (&val, pQ15, 4);
+
+ return (val);
+}
+
+/**
+ @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2_ia (
+ q15_t ** pQ15)
+{
+ q31_t val;
+
+ memcpy (&val, *pQ15, 4);
+ *pQ15 += 2;
+
+ return (val);
+}
+
+/**
+ @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2_da (
+ q15_t ** pQ15)
+{
+ q31_t val;
+
+ memcpy (&val, *pQ15, 4);
+ *pQ15 -= 2;
+
+ return (val);
+}
+
+/**
+ @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
+ @param[in] pQ15 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q15x2_ia (
+ q15_t ** pQ15,
+ q31_t value)
+{
+ q31_t val = value;
+
+ memcpy (*pQ15, &val, 4);
+ *pQ15 += 2;
+}
+
+/**
+ @brief Write 2 Q15 to Q15 pointer.
+ @param[in] pQ15 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q15x2 (
+ q15_t * pQ15,
+ q31_t value)
+{
+ q31_t val = value;
+
+ memcpy (pQ15, &val, 4);
+}
+
+
+/**
+ @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
+ @param[in] pQ7 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q7x4_ia (
+ q7_t ** pQ7)
+{
+ q31_t val;
+
+ memcpy (&val, *pQ7, 4);
+ *pQ7 += 4;
+
+ return (val);
+}
+
+/**
+ @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
+ @param[in] pQ7 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q7x4_da (
+ q7_t ** pQ7)
+{
+ q31_t val;
+
+ memcpy (&val, *pQ7, 4);
+ *pQ7 -= 4;
+
+ return (val);
+}
+
+/**
+ @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
+ @param[in] pQ7 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q7x4_ia (
+ q7_t ** pQ7,
+ q31_t value)
+{
+ q31_t val = value;
+
+ memcpy (*pQ7, &val, 4);
+ *pQ7 += 4;
+}
+
+
+#ifndef ARM_MATH_DSP
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+ #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+ #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+#endif
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ __STATIC_FORCEINLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ __STATIC_FORCEINLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ __STATIC_FORCEINLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ __STATIC_FORCEINLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+ __STATIC_FORCEINLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y) ) );
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+ __STATIC_FORCEINLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ const q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1U);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ __STATIC_FORCEINLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ const q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+/*
+ * @brief C custom defined intrinsic functions
+ */
+#if !defined (ARM_MATH_DSP)
+
+ /*
+ * @brief C custom defined QADD8
+ */
+ __STATIC_FORCEINLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8
+ */
+ __STATIC_FORCEINLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16
+ */
+ __STATIC_FORCEINLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16
+ */
+ __STATIC_FORCEINLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16
+ */
+ __STATIC_FORCEINLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16
+ */
+ __STATIC_FORCEINLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX
+ */
+ __STATIC_FORCEINLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX
+ */
+ __STATIC_FORCEINLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX
+ */
+ __STATIC_FORCEINLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX
+ */
+ __STATIC_FORCEINLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD
+ */
+ __STATIC_FORCEINLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB
+ */
+ __STATIC_FORCEINLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD
+ */
+ __STATIC_FORCEINLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX
+ */
+ __STATIC_FORCEINLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16
+ */
+ __STATIC_FORCEINLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA
+ */
+ __STATIC_FORCEINLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns either
+ * <code>ARM_MATH_SUCCESS</code> if initialization was successful or
+ * <code>ARM_MATH_ARGUMENT_ERROR</code> if <code>numTaps</code> is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+arm_status arm_rfft_32_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
+
+arm_status arm_rfft_64_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
+
+arm_status arm_rfft_128_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
+
+arm_status arm_rfft_256_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
+
+arm_status arm_rfft_512_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
+
+arm_status arm_rfft_1024_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
+
+arm_status arm_rfft_2048_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
+
+arm_status arm_rfft_4096_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
+
+
+ void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ const float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ const float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ const q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ const q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ const float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ const q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ const q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ const q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ const q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ const q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ const q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ const float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ const q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ const q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ const q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+/**
+ @brief Instance structure for floating-point FIR decimator.
+ */
+typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+/**
+ @brief Processing function for floating-point FIR decimator.
+ @param[in] S points to an instance of the floating-point FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ */
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ @brief Initialization function for the floating-point FIR decimator.
+ @param[in,out] S points to an instance of the floating-point FIR decimator structure
+ @param[in] numTaps number of coefficients in the filter
+ @param[in] M decimation factor
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process per call
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_LENGTH_ERROR : <code>blockSize</code> is not a multiple of <code>M</code>
+ */
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ const q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ const q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void arm_correlate_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+/**
+ @brief Correlation of Q15 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @return none
+ */
+void arm_correlate_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence.
+ @param[in] srcALen length of the first input sequence.
+ @param[in] pSrcB points to the second input sequence.
+ @param[in] srcBLen length of the second input sequence.
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void arm_correlate_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ @brief Correlation of Q31 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ * </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return processed output sample.
+ */
+ __STATIC_FORCEINLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+/**
+ @brief Process function for the Q31 PID Control.
+ @param[in,out] S points to an instance of the Q31 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+__STATIC_FORCEINLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+/**
+ @brief Process function for the Q15 PID Control.
+ @param[in,out] S points to an instance of the Q15 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+__STATIC_FORCEINLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+/**
+ @brief Clarke transform for Q31 version
+ @param[in] Ia input three-phase coordinate <code>a</code>
+ @param[in] Ib input three-phase coordinate <code>b</code>
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+/**
+ @brief Inverse Clarke transform for Q31 version
+ @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ @param[in] Ibeta input two-phase orthogonal vector axis beta
+ @param[out] pIa points to output three-phase coordinate <code>a</code>
+ @param[out] pIb points to output three-phase coordinate <code>b</code>
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ __STATIC_FORCEINLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+/**
+ @brief Park transform for Q31 version
+ @param[in] Ialpha input two-phase vector coordinate alpha
+ @param[in] Ibeta input two-phase vector coordinate beta
+ @param[out] pId points to output rotor reference frame d
+ @param[out] pIq points to output rotor reference frame q
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+/**
+ @brief Inverse Park transform for Q31 version
+ @param[in] Id input coordinate of rotor reference frame d
+ @param[in] Iq input coordinate of rotor reference frame q
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ __STATIC_FORCEINLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ __STATIC_FORCEINLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1U);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ __STATIC_FORCEINLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ __STATIC_FORCEINLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ @brief Floating-point square root function.
+ @param[in] in input value
+ @param[out] pOut square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+__STATIC_FORCEINLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ *pOut = __sqrtf(in);
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+/**
+ @brief Q31 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+/**
+ @brief Q15 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t rOffset;
+ int32_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset;
+ q15_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset;
+ q7_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ const q15_t * pSrcCmplx,
+ const q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ const q31_t * pSrcCmplx,
+ const q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ const float32_t * pSrcCmplx,
+ const float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ const float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ const float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ const float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ const q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ const q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ const q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ const q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ const q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ const q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ const q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ const q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ const q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h new file mode 100644 index 000000000..f0fec127e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h @@ -0,0 +1,869 @@ +/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.0.5
+ * @date 14. December 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang.h new file mode 100644 index 000000000..2b53fb003 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang.h @@ -0,0 +1,1420 @@ +/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.1.0
+ * @date 14. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang_ltm.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang_ltm.h new file mode 100644 index 000000000..6aa02067a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang_ltm.h @@ -0,0 +1,1866 @@ +/**************************************************************************//**
+ * @file cmsis_armclang_ltm.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.0.1
+ * @date 19. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_compiler.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_compiler.h new file mode 100644 index 000000000..2c8bb0458 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_compiler.h @@ -0,0 +1,271 @@ +/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h new file mode 100644 index 000000000..6ab451117 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h @@ -0,0 +1,2101 @@ +/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.1.0
+ * @date 20. December 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h new file mode 100644 index 000000000..682849e61 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h @@ -0,0 +1,940 @@ +/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.8
+ * @date 04. September 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include <intrinsics.h>
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h new file mode 100644 index 000000000..ae3f2e33d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_armv81mml.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_armv81mml.h new file mode 100644 index 000000000..f4b6dde5d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_armv81mml.h @@ -0,0 +1,2967 @@ +/**************************************************************************//**
+ * @file core_armv81mml.h
+ * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
+ * @version V1.0.0
+ * @date 15. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV81MML_H_GENERIC
+#define __CORE_ARMV81MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMV81MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+#define __ARM_ARCH_8M_MAIN__ 1 // patching for now
+/* CMSIS ARMV81MML definitions */
+#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV81MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV81MML_H_DEPENDANT
+#define __CORE_ARMV81MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv81MML_REV
+ #define __ARMv81MML_REV 0x0000U
+ #warning "__ARMv81MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv81MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV81MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_armv8mbl.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_armv8mbl.h new file mode 100644 index 000000000..6789cba09 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//**
+ * @file core_armv8mbl.h
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MBL
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MBL_REV
+ #define __ARMv8MBL_REV 0x0000U
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_armv8mml.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_armv8mml.h new file mode 100644 index 000000000..034558416 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_armv8mml.h @@ -0,0 +1,2832 @@ +/**************************************************************************//**
+ * @file core_armv8mml.h
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version V5.1.0
+ * @date 12. September 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MML_REV
+ #define __ARMv8MML_REV 0x0000U
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_cm4.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_cm4.h new file mode 100644 index 000000000..5a17f8b61 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/core_cm4.h @@ -0,0 +1,2121 @@ +/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.1.0
+ * @date 13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = (uint32_t )SCB->VTOR;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/mpu_armv7.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/mpu_armv7.h new file mode 100644 index 000000000..337eb6556 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/mpu_armv7.h @@ -0,0 +1,272 @@ +/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.1.0
+ * @date 08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if shareable) or 010b (if non-shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h new file mode 100644 index 000000000..2fe28b687 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h @@ -0,0 +1,346 @@ +/******************************************************************************
+ * @file mpu_armv8.h
+ * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version V5.1.0
+ * @date 08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable */
+#define ARM_MPU_SH_NON (0U)
+
+/** \brief Normal memory outer shareable */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+ ((BASE & MPU_RBAR_BASE_Msk) | \
+ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+ ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; /*!< Region Base Address Register value */
+ uint32_t RLAR; /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+ const uint8_t reg = idx / 4U;
+ const uint32_t pos = ((idx % 4U) * 8U);
+ const uint32_t mask = 0xFFU << pos;
+
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+ return; // invalid index
+ }
+
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+ mpu->RNR = rnr;
+ mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ mpu->RNR = rnr;
+ mpu->RBAR = rbar;
+ mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ if (cnt == 1U) {
+ mpu->RNR = rnr;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+ } else {
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+ mpu->RNR = rnrBase;
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+ table += c;
+ cnt -= c;
+ rnrOffset = 0U;
+ rnrBase += MPU_TYPE_RALIASES;
+ mpu->RNR = rnrBase;
+ }
+
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/board.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/board.c new file mode 100644 index 000000000..ed24029ed --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/board.c @@ -0,0 +1,227 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "board.h"
+#include <stdint.h>
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_emc.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+#if defined BOARD_USE_CODEC
+#include "fsl_wm8904.h"
+#endif
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* The SDRAM timing. */
+
+#define W9812G6JB6I
+
+#ifdef MTL48LC8M16A2B
+#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
+#define SDRAM_TRP_NS (18u)
+#define SDRAM_TRAS_NS (42u)
+#define SDRAM_TSREX_NS (67u)
+#define SDRAM_TAPR_NS (18u)
+#define SDRAM_TWRDELT_NS (6u)
+#define SDRAM_TRC_NS (60u)
+#define SDRAM_RFC_NS (60u)
+#define SDRAM_XSR_NS (67u)
+#define SDRAM_RRD_NS (12u)
+#define SDRAM_MRD_NCLK (2u)
+#define SDRAM_RAS_NCLK (2u)
+#define SDRAM_MODEREG_VALUE (0x23u)
+#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
+#endif
+
+#ifdef W9812G6JB6I
+#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
+#define SDRAM_TRP_NS (20u)
+#define SDRAM_TRAS_NS (42u)
+#define SDRAM_TSREX_NS (72u)
+#define SDRAM_TAPR_NS (18u)
+#define SDRAM_TWRDELT_NS (12u)
+#define SDRAM_TRC_NS (60u)
+#define SDRAM_RFC_NS (60u)
+#define SDRAM_XSR_NS (67u)
+#define SDRAM_RRD_NS (12u)
+#define SDRAM_MRD_NCLK (2u)
+#define SDRAM_RAS_NCLK (2u)
+#define SDRAM_MODEREG_VALUE (0x23u)
+#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Clock rate on the CLKIN pin */
+const uint32_t ExtClockIn = BOARD_EXTCLKINRATE;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+status_t BOARD_InitDebugConsole(void)
+{
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+ status_t result;
+ uint8_t instance = BOARD_DEBUG_UART_INSTANCE;
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ if (BOARD_DEBUG_UART_TYPE == kSerialPort_UsbCdc)
+ {
+ instance = kSerialManager_UsbControllerLpcIp3511Hs0;
+ }
+#endif
+
+ /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+ RESET_PeripheralReset(BOARD_DEBUG_UART_RST);
+ result = DbgConsole_Init(instance, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, BOARD_DEBUG_UART_CLK_FREQ);
+ assert(kStatus_Success == result);
+ return result;
+#else
+ return kStatus_Success;
+#endif
+}
+
+/* Initialize the external memory. */
+void BOARD_InitSDRAM(void)
+{
+ uint32_t emcFreq;
+ emc_basic_config_t basicConfig;
+ emc_dynamic_timing_config_t dynTiming;
+ emc_dynamic_chip_config_t dynChipConfig;
+
+ emcFreq = CLOCK_GetEmcClkFreq();
+ assert(emcFreq != 0); /* Check the clock of emc */
+ /* Basic configuration. */
+ basicConfig.endian = kEMC_LittleEndian;
+ basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk;
+ /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M.
+ * If you change the divide to 0 and EMC clock is larger than 100M
+ * please take refer to emc.dox to adjust EMC clock delay.
+ */
+ basicConfig.emcClkDiv = 1;
+ /* Dynamic memory timing configuration. */
+ dynTiming.readConfig = kEMC_Cmddelay;
+ dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS;
+ dynTiming.tRp_Ns = SDRAM_TRP_NS;
+ dynTiming.tRas_Ns = SDRAM_TRAS_NS;
+ dynTiming.tSrex_Ns = SDRAM_TSREX_NS;
+ dynTiming.tApr_Ns = SDRAM_TAPR_NS;
+ dynTiming.tWr_Ns = (1000000000 / emcFreq + SDRAM_TWRDELT_NS); /* one clk + 6ns */
+ dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns;
+ dynTiming.tRc_Ns = SDRAM_TRC_NS;
+ dynTiming.tRfc_Ns = SDRAM_RFC_NS;
+ dynTiming.tXsr_Ns = SDRAM_XSR_NS;
+ dynTiming.tRrd_Ns = SDRAM_RRD_NS;
+ dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK;
+ /* Dynamic memory chip specific configuration: Chip 0 - W9812G6JB-6I */
+ dynChipConfig.chipIndex = 0;
+ dynChipConfig.dynamicDevice = kEMC_Sdram;
+ dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK;
+ dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE;
+ dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */
+ dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP;
+ /* EMC Basic configuration. */
+ EMC_Init(EMC, &basicConfig);
+ /* EMC Dynamc memory configuration. */
+ EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1);
+}
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+ i2c_master_config_t i2cConfig = {0};
+
+ I2C_MasterGetDefaultConfig(&i2cConfig);
+ I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize)
+{
+ i2c_master_transfer_t masterXfer;
+
+ /* Prepare transfer structure. */
+ masterXfer.slaveAddress = deviceAddress;
+ masterXfer.direction = kI2C_Write;
+ masterXfer.subaddress = subAddress;
+ masterXfer.subaddressSize = subaddressSize;
+ masterXfer.data = txBuff;
+ masterXfer.dataSize = txBuffSize;
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize)
+{
+ i2c_master_transfer_t masterXfer;
+
+ /* Prepare transfer structure. */
+ masterXfer.slaveAddress = deviceAddress;
+ masterXfer.subaddress = subAddress;
+ masterXfer.subaddressSize = subaddressSize;
+ masterXfer.data = rxBuff;
+ masterXfer.dataSize = rxBuffSize;
+ masterXfer.direction = kI2C_Read;
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+ BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+ uint8_t data = (uint8_t)txBuff;
+
+ return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+ BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+ txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/board.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/board.h new file mode 100644 index 000000000..ff1907809 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/board.h @@ -0,0 +1,232 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPC54018-IoT-Module"
+
+#define BOARD_EXTCLKINRATE (0)
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#ifndef BOARD_DEBUG_UART_TYPE
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#endif
+
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE 0U
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFlexCommClkFreq(0U)
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn
+#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ FLEXCOMM0_IRQn
+/* TODO: obsolete */
+#define BOARD_DEBUG_SPI_CLK_FREQ 12000000
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_ACCEL_I2C_BASEADDR I2C2
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
+
+#define BOARD_CODEC_I2C_BASEADDR I2C2
+#define BOARD_CODEC_I2C_INSTANCE 2U
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
+
+/*! @brief The ENET PHY address. */
+#define BOARD_ENET0_PHY_ADDRESS (0x00U) /* Phy address of enet port 0. */
+
+#ifndef BOARD_LED1_GPIO
+#define BOARD_LED1_GPIO GPIO
+#endif
+#define BOARD_LED1_GPIO_PORT 3U
+#ifndef BOARD_LED1_GPIO_PIN
+#define BOARD_LED1_GPIO_PIN 14U
+#endif
+
+#ifndef BOARD_LED2_GPIO
+#define BOARD_LED2_GPIO GPIO
+#endif
+#define BOARD_LED2_GPIO_PORT 3U
+#ifndef BOARD_LED2_GPIO_PIN
+#define BOARD_LED2_GPIO_PIN 3U
+#endif
+#ifndef BOARD_LED3_GPIO
+#define BOARD_LED3_GPIO GPIO
+#endif
+#define BOARD_LED3_GPIO_PORT 3U
+#ifndef BOARD_LED3_GPIO_PIN
+#define BOARD_LED3_GPIO_PIN 13U
+#endif
+
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 0U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 4U
+#endif
+#define BOARD_SW1_NAME "SW1"
+#define BOARD_SW3_IRQ PIN_INT0_IRQn
+#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler
+
+#ifndef BOARD_SW2_GPIO
+#define BOARD_SW2_GPIO GPIO
+#endif
+#define BOARD_SW2_GPIO_PORT 0U
+#ifndef BOARD_SW2_GPIO_PIN
+#define BOARD_SW2_GPIO_PIN 6U
+#endif
+#define BOARD_SW2_NAME "SW2"
+#define BOARD_SW2_IRQ PIN_INT0_IRQn
+#define BOARD_SW2_IRQ_HANDLER PIN_INT0_IRQHandler
+
+#ifndef BOARD_SW3_GPIO
+#define BOARD_SW3_GPIO GPIO
+#endif
+#define BOARD_SW3_GPIO_PORT 0U
+#ifndef BOARD_SW3_GPIO_PIN
+#define BOARD_SW3_GPIO_PIN 5U
+#endif
+#define BOARD_SW3_NAME "SW3"
+#define BOARD_SW3_IRQ PIN_INT0_IRQn
+#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler
+#define BOARD_SW3_GPIO_PININT_INDEX 0
+
+#ifndef BOARD_SW4_GPIO
+#define BOARD_SW4_GPIO GPIO
+#endif
+#ifndef BOARD_SW4_GPIO_PORT
+#define BOARD_SW4_GPIO_PORT 0U
+#endif
+#ifndef BOARD_SW4_GPIO_PIN
+#define BOARD_SW4_GPIO_PIN 4U
+#endif
+#define BOARD_SW4_NAME "SW4"
+#define BOARD_SW4_IRQ PIN_INT0_IRQn
+#define BOARD_SW4_IRQ_HANDLER PIN_INT0_IRQHandler
+#define BOARD_SW4_GPIO_PININT_INDEX 0
+
+#ifndef BOARD_SW5_GPIO
+#define BOARD_SW5_GPIO GPIO
+#endif
+#ifndef BOARD_SW5_GPIO_PORT
+#define BOARD_SW5_GPIO_PORT 1U
+#endif
+#ifndef BOARD_SW5_GPIO_PIN
+#define BOARD_SW5_GPIO_PIN 1U
+#endif
+#define BOARD_SW5_NAME "SW5"
+#define BOARD_SW5_IRQ PIN_INT1_IRQn
+#define BOARD_SW5_IRQ_HANDLER PIN_INT1_IRQHandler
+#define BOARD_SW5_GPIO_PININT_INDEX 0
+
+#define BOARD_SDIF_BASEADDR SDIF
+#define BOARD_SDIF_CLK_FREQ CLOCK_GetSdioClkFreq()
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
+#define BOARD_SDIF_IRQ SDIO_IRQn
+
+#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
+#define BOARD_SD_CARD_DETECT_PIN 10
+#define BOARD_SD_CARD_DETECT_PORT 2
+#define BOARD_SD_CARD_DETECT_GPIO GPIO
+#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD
+
+#define BOARD_SDIF_CD_GPIO_INIT() \
+ { \
+ CLOCK_EnableClock(kCLOCK_Gpio2); \
+ GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \
+ }
+#define BOARD_SDIF_CD_STATUS() \
+ GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
+
+/* Board led color mapping */
+#define LOGIC_LED_ON 0U
+#define LOGIC_LED_OFF 1U
+
+#define LED1_INIT(output) \
+ GPIO_PinInit(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, BOARD_LED1_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
+#define LED1_ON() \
+ GPIO_PortClear(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED1_OFF() \
+ GPIO_PortSet(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED1_TOGGLE() \
+ GPIO_PortToggle(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Toggle on target LED1 */
+#define LED2_INIT(output) \
+ GPIO_PinInit(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, BOARD_LED2_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED2 */
+#define LED2_ON() \
+ GPIO_PortClear(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Turn on target LED2 */
+#define LED2_OFF() \
+ GPIO_PortSet(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Turn off target LED2 */
+#define LED2_TOGGLE() \
+ GPIO_PortToggle(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Toggle on target LED2 */
+
+#define LED3_INIT(output) \
+ GPIO_PinInit(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, BOARD_LED3_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED3 */
+#define LED3_ON() \
+ GPIO_PortClear(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Turn on target LED3 */
+#define LED3_OFF() \
+ GPIO_PortSet(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Turn off target LED3 */
+#define LED3_TOGGLE() \
+ GPIO_PortToggle(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Toggle on target LED3 */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+status_t BOARD_InitDebugConsole(void);
+void BOARD_InitSDRAM(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/clock_config.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/clock_config.c new file mode 100644 index 000000000..c163b1e97 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/clock_config.c @@ -0,0 +1,269 @@ +/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017,2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Setup voltage for the fastest of the clock outputs
+ *
+ * 3. Set up wait states of the flash.
+ *
+ * 4. Set up all dividers.
+ *
+ * 5. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC54018
+package_id: LPC54018JET180
+mcu_data: ksdk2_0
+processor_version: 0.7.1
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockPLL180M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+ /*!< Set up the clock sources */
+ /*!< Set up FRO */
+ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+ accidentally being below the voltage for current speed */
+ /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+ before calling this API since this API is implemented in ROM code */
+ CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
+ POWER_SetVoltageForFreq(
+ 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+ /*!< Set up the clock sources */
+ /*!< Set up FRO */
+ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+ accidentally being below the voltage for current speed */
+ POWER_SetVoltageForFreq(
+ 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+ /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+ before calling this API since this API is implemented in ROM code */
+ CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 96 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+sources:
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+ /*!< Set up the clock sources */
+ /*!< Set up FRO */
+ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+ accidentally being below the voltage for current speed */
+ POWER_SetVoltageForFreq(
+ 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+ /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+ before calling this API since this API is implemented in ROM code */
+ CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL180M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL180M
+called_from_default_init: true
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 180 MHz}
+- {id: SYSPLL_clock.outFreq, value: 180 MHz}
+- {id: System_clock.outFreq, value: 180 MHz}
+- {id: USB0_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
+- {id: SYSCON.M_MULT.scale, value: '30', locked: true}
+- {id: SYSCON.N_DIV.scale, value: '1', locked: true}
+- {id: SYSCON.PDEC.scale, value: '2', locked: true}
+- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.fro_hf}
+- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
+sources:
+- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL180M(void)
+{
+ /*!< Set up the clock sources */
+ /*!< Set up FRO */
+ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+ accidentally being below the voltage for current speed */
+ POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */
+ SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) |
+ SYSCON_SYSOSCCTRL_FREQRANGE(0U)); /*!< Set system oscillator range */
+ POWER_SetVoltageForFreq(
+ 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+ /*!< Set up SYS PLL */
+ const pll_setup_t pllSetup = {
+ .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
+ .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
+ .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
+ .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
+ .pllRate = 180000000U,
+ .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
+ CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
+ CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
+ /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+ before calling this API since this API is implemented in ROM code */
+ CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Set USB0CLKDIV divider to value 1 */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
+ CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); /*!< Switch USB0_CLK to FRO_HF */
+ SYSCON->MAINCLKSELA =
+ ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) |
+ SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/clock_config.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/clock_config.h new file mode 100644 index 000000000..9947c1fad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/clock_config.h @@ -0,0 +1,142 @@ +/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017,2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency:12000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency:48000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency:96000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL180M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL180M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/pin_mux.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/pin_mux.c new file mode 100644 index 000000000..2fa7f0244 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/pin_mux.c @@ -0,0 +1,90 @@ +/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v3.0
+processor: LPC54018
+package_id: LPC54018JET180
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ *END**************************************************************************/
+void BOARD_InitBootPins(void) {
+ BOARD_InitPins();
+}
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u /*!< Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u /*!< Selects pin function 1 */
+#define IOCON_PIO_INPFILT_OFF 0x0200u /*!< Input filter disabled */
+#define IOCON_PIO_INV_DI 0x00u /*!< Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u /*!< No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!< Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!< Standard mode, output slew rate control is enabled */
+#define PIN29_IDX 29u /*!< Pin number for pin 29 in a port 0 */
+#define PIN30_IDX 30u /*!< Pin number for pin 30 in a port 0 */
+#define PORT0_IDX 0u /*!< Port index */
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: B13, peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI/CTIMER2_MAT3/SCT0_OUT8/TRACEDATA(2), mode: inactive, invert: disabled,
+ glitch_filter: disabled, slew_rate: standard, open_drain: disabled}
+ - {pin_num: A2, peripheral: FLEXCOMM0, signal: TXD_SCL_MISO, pin_signal: PIO0_30/FC0_TXD_SCL_MISO/CTIMER0_MAT0/SCT0_OUT9/TRACEDATA(1), mode: inactive, invert: disabled,
+ glitch_filter: disabled, slew_rate: standard, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ *
+ *END**************************************************************************/
+void BOARD_InitPins(void) { /* Function assigned for the Core #0 (ARM Cortex-M4) */
+ CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */
+
+ const uint32_t port0_pin29_config = (
+ IOCON_PIO_FUNC1 | /* Pin is configured as FC0_RXD_SDA_MOSI */
+ IOCON_PIO_MODE_INACT | /* No addition pin function */
+ IOCON_PIO_INV_DI | /* Input function is not inverted */
+ IOCON_PIO_DIGITAL_EN | /* Enables digital function */
+ IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
+ IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
+ IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
+ );
+ IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN29_IDX, port0_pin29_config); /* PORT0 PIN29 (coords: B13) is configured as FC0_RXD_SDA_MOSI */
+ const uint32_t port0_pin30_config = (
+ IOCON_PIO_FUNC1 | /* Pin is configured as FC0_TXD_SCL_MISO */
+ IOCON_PIO_MODE_INACT | /* No addition pin function */
+ IOCON_PIO_INV_DI | /* Input function is not inverted */
+ IOCON_PIO_DIGITAL_EN | /* Enables digital function */
+ IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
+ IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
+ IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
+ );
+ IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN30_IDX, port0_pin30_config); /* PORT0 PIN30 (coords: A2) is configured as FC0_TXD_SCL_MISO */
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/pin_mux.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/pin_mux.h new file mode 100644 index 000000000..5a4169dda --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/pin_mux.h @@ -0,0 +1,61 @@ +/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Direction type */
+typedef enum _pin_mux_direction
+{
+ kPIN_MUX_DirectionInput = 0U, /* Input direction */
+ kPIN_MUX_DirectionOutput = 1U, /* Output direction */
+ kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M4F */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/lists/generic_list.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/lists/generic_list.c new file mode 100644 index 000000000..8224c8ef8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/lists/generic_list.c @@ -0,0 +1,423 @@ +/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+#include "fsl_common.h"
+#include "generic_list.h"
+
+static list_status_t LIST_Scan(list_handle_t list, list_element_handle_t newElement)
+{
+ list_element_handle_t element = list->head;
+
+ while (element != NULL)
+ {
+ if (element == newElement)
+ {
+ return kLIST_DuplicateError;
+ }
+ element = element->next;
+ }
+ return kLIST_Ok;
+}
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*! *********************************************************************************
+ * \brief Initialises the list descriptor.
+ *
+ * \param[in] list - LIST_ handle to init.
+ * max - Maximum number of elements in list. 0 for unlimited.
+ *
+ * \return void.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+void LIST_Init(list_handle_t list, uint32_t max)
+{
+ list->head = NULL;
+ list->tail = NULL;
+ list->max = (uint16_t)max;
+ list->size = 0;
+}
+
+/*! *********************************************************************************
+ * \brief Gets the list that contains the given element.
+ *
+ * \param[in] element - Handle of the element.
+ *
+ * \return NULL if element is orphan.
+ * Handle of the list the element is inserted into.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_handle_t LIST_GetList(list_element_handle_t element)
+{
+ return element->list;
+}
+
+/*! *********************************************************************************
+ * \brief Links element to the tail of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ * element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ * kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element)
+{
+ uint32_t regPrimask = DisableGlobalIRQ();
+
+ if ((list->max != 0U) && (list->max == list->size))
+ {
+ EnableGlobalIRQ(regPrimask);
+ return kLIST_Full;
+ }
+
+ if (kLIST_DuplicateError == LIST_Scan(list, element))
+ {
+ EnableGlobalIRQ(regPrimask);
+ return kLIST_DuplicateError;
+ }
+
+ if (list->size == 0U)
+ {
+ list->head = element;
+ }
+ else
+ {
+ list->tail->next = element;
+ }
+ element->prev = list->tail;
+ element->next = NULL;
+ element->list = list;
+ list->tail = element;
+ list->size++;
+
+ EnableGlobalIRQ(regPrimask);
+ return kLIST_Ok;
+}
+
+/*! *********************************************************************************
+ * \brief Links element to the head of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ * element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ * kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element)
+{
+ uint32_t regPrimask = DisableGlobalIRQ();
+
+ if ((list->max != 0U) && (list->max == list->size))
+ {
+ EnableGlobalIRQ(regPrimask);
+ return kLIST_Full;
+ }
+
+ if (kLIST_DuplicateError == LIST_Scan(list, element))
+ {
+ EnableGlobalIRQ(regPrimask);
+ return kLIST_DuplicateError;
+ }
+
+ if (list->size == 0U)
+ {
+ list->tail = element;
+ }
+ else
+ {
+ list->head->prev = element;
+ }
+ element->next = list->head;
+ element->prev = NULL;
+ element->list = list;
+ list->head = element;
+ list->size++;
+
+ EnableGlobalIRQ(regPrimask);
+ return kLIST_Ok;
+}
+
+/*! *********************************************************************************
+ * \brief Unlinks element from the head of the list.
+ *
+ * \param[in] list - ID of list to remove from.
+ *
+ * \return NULL if list is empty.
+ * ID of removed element(pointer) if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_RemoveHead(list_handle_t list)
+{
+ list_element_handle_t element;
+
+ uint32_t regPrimask = DisableGlobalIRQ();
+
+ if ((NULL == list) || (list->size == 0U))
+ {
+ EnableGlobalIRQ(regPrimask);
+ return NULL; /*LIST_ is empty*/
+ }
+
+ element = list->head;
+ list->size--;
+ if (list->size == 0U)
+ {
+ list->tail = NULL;
+ }
+ else
+ {
+ element->next->prev = NULL;
+ }
+ list->head = element->next; /*Is NULL if element is head*/
+ element->list = NULL;
+
+ EnableGlobalIRQ(regPrimask);
+ return element;
+}
+
+/*! *********************************************************************************
+ * \brief Gets head element ID.
+ *
+ * \param[in] list - ID of list.
+ *
+ * \return NULL if list is empty.
+ * ID of head element if list is not empty.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetHead(list_handle_t list)
+{
+ return list->head;
+}
+
+/*! *********************************************************************************
+ * \brief Gets next element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is tail.
+ * ID of next element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetNext(list_element_handle_t element)
+{
+ return element->next;
+}
+
+/*! *********************************************************************************
+ * \brief Gets previous element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is head.
+ * ID of previous element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetPrev(list_element_handle_t element)
+{
+ return element->prev;
+}
+
+/*! *********************************************************************************
+ * \brief Unlinks an element from its list.
+ *
+ * \param[in] element - ID of the element to remove.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ * kLIST_Ok if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_RemoveElement(list_element_handle_t element)
+{
+ if (element->list == NULL)
+ {
+ return kLIST_OrphanElement; /*Element was previusly removed or never added*/
+ }
+
+ uint32_t regPrimask = DisableGlobalIRQ();
+
+ if (element->prev == NULL) /*Element is head or solo*/
+ {
+ element->list->head = element->next; /*is null if solo*/
+ }
+ if (element->next == NULL) /*Element is tail or solo*/
+ {
+ element->list->tail = element->prev; /*is null if solo*/
+ }
+ if (element->prev != NULL) /*Element is not head*/
+ {
+ element->prev->next = element->next;
+ }
+ if (element->next != NULL) /*Element is not tail*/
+ {
+ element->next->prev = element->prev;
+ }
+ element->list->size--;
+ element->list = NULL;
+
+ EnableGlobalIRQ(regPrimask);
+ return kLIST_Ok;
+}
+
+/*! *********************************************************************************
+ * \brief Links an element in the previous position relative to a given member
+ * of a list.
+ *
+ * \param[in] element - ID of a member of a list.
+ * newElement - new element to insert before the given member.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ * kLIST_Full if list is full.
+ * kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement)
+{
+ if (element->list == NULL)
+ {
+ return kLIST_OrphanElement; /*Element was previusly removed or never added*/
+ }
+ uint32_t regPrimask = DisableGlobalIRQ();
+
+ if ((element->list->max != 0U) && (element->list->max == element->list->size))
+ {
+ EnableGlobalIRQ(regPrimask);
+ return kLIST_Full;
+ }
+
+ if (kLIST_DuplicateError == LIST_Scan(element->list, newElement))
+ {
+ EnableGlobalIRQ(regPrimask);
+ return kLIST_DuplicateError;
+ }
+
+ if (element->prev == NULL) /*Element is list head*/
+ {
+ element->list->head = newElement;
+ }
+ else
+ {
+ element->prev->next = newElement;
+ }
+ newElement->list = element->list;
+ element->list->size++;
+ newElement->next = element;
+ newElement->prev = element->prev;
+ element->prev = newElement;
+
+ EnableGlobalIRQ(regPrimask);
+ return kLIST_Ok;
+}
+
+/*! *********************************************************************************
+ * \brief Gets the current size of a list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Current size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetSize(list_handle_t list)
+{
+ return list->size;
+}
+
+/*! *********************************************************************************
+ * \brief Gets the number of free places in the list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Available size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetAvailableSize(list_handle_t list)
+{
+ return ((uint32_t)list->max - (uint32_t)list->size);
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/lists/generic_list.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/lists/generic_list.h new file mode 100644 index 000000000..5477520d7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/lists/generic_list.h @@ -0,0 +1,191 @@ +/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _GENERIC_LIST_H_
+#define _GENERIC_LIST_H_
+
+/*!
+ * @addtogroup GenericList
+ * @{
+ */
+
+/*!*********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public macro definitions
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public type definitions
+*************************************************************************************
+********************************************************************************** */
+/*! @brief The list status */
+typedef enum _list_status
+{
+ kLIST_Ok = kStatus_Success, /*!< Success */
+ kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */
+ kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */
+ kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */
+ kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */
+} list_status_t;
+
+/*! @brief The list structure*/
+typedef struct list_label
+{
+ struct list_element_tag *head; /*!< list head */
+ struct list_element_tag *tail; /*!< list tail */
+ uint16_t size; /*!< list size */
+ uint16_t max; /*!< list max number of elements */
+} list_label_t, *list_handle_t;
+
+/*! @brief The list element*/
+typedef struct list_element_tag
+{
+ struct list_element_tag *next; /*!< next list element */
+ struct list_element_tag *prev; /*!< previous list element */
+ struct list_label *list; /*!< pointer to the list */
+} list_element_t, *list_element_handle_t;
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public prototypes
+*************************************************************************************
+********************************************************************************** */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+/*!
+ * @brief Initialize the list.
+ *
+ * This function initialize the list.
+ *
+ * @param list - List handle to initialize.
+ * @param max - Maximum number of elements in list. 0 for unlimited.
+ */
+void LIST_Init(list_handle_t list, uint32_t max);
+
+/*!
+ * @brief Gets the list that contains the given element.
+ *
+ *
+ * @param element - Handle of the element.
+ * @retval NULL if element is orphan, Handle of the list the element is inserted into.
+ */
+list_handle_t LIST_GetList(list_element_handle_t element);
+
+/*!
+ * @brief Links element to the head of the list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element);
+
+/*!
+ * @brief Links element to the tail of the list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element);
+
+/*!
+ * @brief Unlinks element from the head of the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_RemoveHead(list_handle_t list);
+
+/*!
+ * @brief Gets head element handle.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetHead(list_handle_t list);
+
+/*!
+ * @brief Gets next element handle for given element handle.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetNext(list_element_handle_t element);
+
+/*!
+ * @brief Gets previous element handle for given element handle.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetPrev(list_element_handle_t element);
+
+/*!
+ * @brief Unlinks an element from its list.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_RemoveElement(list_element_handle_t element);
+
+/*!
+ * @brief Links an element in the previous position relative to a given member of a list.
+ *
+ * @param element - Handle of the element.
+ * @param newElement - New element to insert before the given member.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement);
+
+/*!
+ * @brief Gets the current size of a list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Current size of the list.
+ */
+uint32_t LIST_GetSize(list_handle_t list);
+
+/*!
+ * @brief Gets the number of free places in the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Available size of the list.
+ */
+uint32_t LIST_GetAvailableSize(list_handle_t list);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /*_GENERIC_LIST_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_manager.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_manager.c new file mode 100644 index 000000000..f82163c99 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_manager.c @@ -0,0 +1,1382 @@ +/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include <string.h>
+
+#include "serial_manager.h"
+#include "serial_port_internal.h"
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#include "generic_list.h"
+
+/*
+ * The OSA_USED macro can only be defined when the OSA component is used.
+ * If the source code of the OSA component does not exist, the OSA_USED cannot be defined.
+ * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED
+ * also cannot be defined.
+ * The source code path of the OSA component is <MCUXpresso_SDK>/components/osa.
+ *
+ */
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#include "common_task.h"
+#else
+#include "fsl_os_abstraction.h"
+#endif
+
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#define SERIAL_EVENT_DATA_RECEIVED (1U << 0)
+#define SERIAL_EVENT_DATA_SENT (1U << 1)
+
+#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U
+#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+typedef enum _serial_manager_transmission_mode
+{
+ kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/
+ kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/
+} serial_manager_transmission_mode_t;
+
+/* TX transfer structure */
+typedef struct _serial_manager_transfer
+{
+ uint8_t *buffer;
+ volatile uint32_t length;
+ volatile uint32_t soFar;
+ serial_manager_transmission_mode_t mode;
+ serial_manager_status_t status;
+} serial_manager_transfer_t;
+#endif
+
+/* write handle structure */
+typedef struct _serial_manager_send_handle
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ list_element_t link; /*!< list element of the link */
+ serial_manager_transfer_t transfer;
+#endif
+ struct _serial_manager_handle *serialManagerHandle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serial_manager_callback_t callback;
+ void *callbackParam;
+ uint32_t tag;
+#endif
+} serial_manager_write_handle_t;
+
+typedef serial_manager_write_handle_t serial_manager_read_handle_t;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/* receive state structure */
+typedef struct _serial_manager_read_ring_buffer
+{
+ uint8_t *ringBuffer;
+ uint32_t ringBufferSize;
+ volatile uint32_t ringHead;
+ volatile uint32_t ringTail;
+} serial_manager_read_ring_buffer_t;
+#endif
+
+#if defined(__CC_ARM)
+#pragma anon_unions
+#endif
+/* The serial manager handle structure */
+typedef struct _serial_manager_handle
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ list_label_t runningWriteHandleHead; /*!< The queue of running write handle */
+ list_label_t completedWriteHandleHead; /*!< The queue of completed write handle */
+#endif
+ serial_manager_read_handle_t *volatile openedReadHandleHead;
+ volatile uint32_t openedWriteHandleCount;
+ union
+ {
+ uint8_t lowLevelhandleBuffer[1];
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE];
+#endif
+ };
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serial_manager_read_ring_buffer_t ringBuffer;
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ common_task_message_t commontaskMsg;
+#else
+ uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */
+ uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */
+#endif
+
+#endif
+
+#endif
+
+ serial_port_type_t type;
+} serial_manager_handle_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_Task(void *param);
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+
+#else
+ /*
+ * \brief Defines the serial manager task's stack
+ */
+OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false);
+#endif
+
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_AddTail(list_label_t *queue, serial_manager_write_handle_t *node)
+{
+ (void)LIST_AddTail(queue, &node->link);
+}
+
+static void SerialManager_RemoveHead(list_label_t *queue)
+{
+ (void)LIST_RemoveHead(queue);
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+ serial_manager_write_handle_t *writeHandle =
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead);
+
+ if (writeHandle != NULL)
+ {
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+ default:
+ status = kStatus_SerialManager_Error;
+ break;
+ }
+ }
+ return status;
+}
+
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,
+ serial_manager_read_handle_t *readHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ if (NULL != readHandle)
+ {
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ if (handle->type == kSerialPort_UsbCdc)
+ {
+ status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ }
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ if (handle->type == kSerialPort_UsbCdcVirtual)
+ {
+ status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ }
+#endif
+ }
+ return status;
+}
+
+#else
+
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle,
+ serial_manager_write_handle_t *writeHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ if (NULL != writeHandle)
+ {
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+ default:
+ status = kStatus_SerialManager_Error;
+ break;
+ }
+ }
+ return status;
+}
+
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,
+ serial_manager_read_handle_t *readHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ if (NULL != readHandle)
+ {
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+ default:
+ status = kStatus_SerialManager_Error;
+ break;
+ }
+ }
+ return status;
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_IsrFunction(serial_manager_handle_t *handle)
+{
+ uint32_t regPrimask = DisableGlobalIRQ();
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ Serial_UsbCdcIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ Serial_SwoIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ Serial_UsbCdcVirtualIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+ EnableGlobalIRQ(regPrimask);
+}
+
+static void SerialManager_Task(void *param)
+{
+ serial_manager_handle_t *handle = (serial_manager_handle_t *)param;
+ serial_manager_write_handle_t *serialWriteHandle;
+ serial_manager_read_handle_t *serialReadHandle;
+ uint32_t primask;
+ serial_manager_callback_message_t msg;
+
+ if (NULL != handle)
+ {
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ osa_event_flags_t ev = 0;
+
+ do
+ {
+ if (KOSA_StatusSuccess ==
+ OSA_EventWait((osa_event_handle_t)handle->event, osaEventFlagsAll_c, false, osaWaitForever_c, &ev))
+ {
+ if (ev & SERIAL_EVENT_DATA_SENT)
+#endif
+
+#endif
+ {
+ serialWriteHandle =
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead);
+ while (NULL != serialWriteHandle)
+ {
+ SerialManager_RemoveHead(&handle->completedWriteHandleHead);
+ msg.buffer = serialWriteHandle->transfer.buffer;
+ msg.length = serialWriteHandle->transfer.soFar;
+ serialWriteHandle->transfer.buffer = NULL;
+ if (NULL != serialWriteHandle->callback)
+ {
+ serialWriteHandle->callback(serialWriteHandle->callbackParam, &msg,
+ serialWriteHandle->transfer.status);
+ }
+ serialWriteHandle =
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead);
+ }
+ }
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ if (ev & SERIAL_EVENT_DATA_RECEIVED)
+#endif
+
+#endif
+ {
+ primask = DisableGlobalIRQ();
+ serialReadHandle = handle->openedReadHandleHead;
+ EnableGlobalIRQ(primask);
+
+ if (NULL != serialReadHandle)
+ {
+ if (NULL != serialReadHandle->transfer.buffer)
+ {
+ if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)
+ {
+ msg.buffer = serialReadHandle->transfer.buffer;
+ msg.length = serialReadHandle->transfer.soFar;
+ serialReadHandle->transfer.buffer = NULL;
+ if (NULL != serialReadHandle->callback)
+ {
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg,
+ serialReadHandle->transfer.status);
+ }
+ }
+ }
+ }
+ }
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ }
+ } while (gUseRtos_c);
+#endif
+
+#endif
+ }
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_TxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_write_handle_t *writeHandle;
+
+ assert(callbackParam);
+ assert(message);
+
+ handle = (serial_manager_handle_t *)callbackParam;
+
+ writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead);
+
+ if (NULL != writeHandle)
+ {
+ SerialManager_RemoveHead(&handle->runningWriteHandleHead);
+ (void)SerialManager_StartWriting(handle);
+ writeHandle->transfer.soFar = message->length;
+ writeHandle->transfer.status = status;
+ if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode)
+ {
+ SerialManager_AddTail(&handle->completedWriteHandleHead, writeHandle);
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ handle->commontaskMsg.callback = SerialManager_Task;
+ handle->commontaskMsg.callbackParam = handle;
+ COMMON_TASK_post_message(&handle->commontaskMsg);
+#else
+ (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_SENT);
+#endif
+
+#else
+ SerialManager_Task(handle);
+#endif
+ }
+ else
+ {
+ writeHandle->transfer.buffer = NULL;
+ }
+ }
+}
+
+static void SerialManager_RxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ serial_manager_handle_t *handle;
+ uint32_t ringBufferLength;
+ uint32_t primask;
+
+ assert(callbackParam);
+ assert(message);
+
+ handle = (serial_manager_handle_t *)callbackParam;
+
+ status = kStatus_SerialManager_Notify;
+
+ for (uint32_t i = 0; i < message->length; i++)
+ {
+ handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead++] = message->buffer[i];
+ if (handle->ringBuffer.ringHead >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringHead = 0U;
+ }
+ if (handle->ringBuffer.ringHead == handle->ringBuffer.ringTail)
+ {
+ status = kStatus_SerialManager_RingBufferOverflow;
+ handle->ringBuffer.ringTail++;
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringTail = 0U;
+ }
+ }
+ }
+
+ ringBufferLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
+ ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize;
+
+ primask = DisableGlobalIRQ();
+ if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->transfer.buffer))
+ {
+ if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)
+ {
+ uint32_t remainLength =
+ handle->openedReadHandleHead->transfer.length - handle->openedReadHandleHead->transfer.soFar;
+ for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++)
+ {
+ handle->openedReadHandleHead->transfer.buffer[handle->openedReadHandleHead->transfer.soFar] =
+ handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];
+ handle->ringBuffer.ringTail++;
+ handle->openedReadHandleHead->transfer.soFar++;
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringTail = 0U;
+ }
+ }
+ ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength);
+ }
+
+ if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)
+ {
+ }
+ else
+ {
+ if (kSerialManager_TransmissionBlocking == handle->openedReadHandleHead->transfer.mode)
+ {
+ handle->openedReadHandleHead->transfer.buffer = NULL;
+ }
+ else
+ {
+ handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success;
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ handle->commontaskMsg.callback = SerialManager_Task;
+ handle->commontaskMsg.callbackParam = handle;
+ COMMON_TASK_post_message(&handle->commontaskMsg);
+#else
+ (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_RECEIVED);
+#endif
+
+#else
+ SerialManager_Task(handle);
+#endif
+ }
+ }
+ }
+
+ if (0U != ringBufferLength)
+ {
+ message->buffer = NULL;
+ message->length = ringBufferLength;
+ if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback))
+ {
+ handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, message, status);
+ }
+ }
+
+ ringBufferLength = handle->ringBuffer.ringBufferSize - 1U - ringBufferLength;
+
+ if (NULL != handle->openedReadHandleHead)
+ {
+ (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength);
+ }
+ EnableGlobalIRQ(primask);
+}
+
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ serial_manager_transmission_mode_t mode)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+ serial_manager_handle_t *handle;
+ serial_manager_status_t status = kStatus_SerialManager_Success;
+ uint32_t primask;
+ uint8_t isEmpty = 0U;
+
+ assert(writeHandle);
+ assert(buffer);
+ assert(length);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+ handle = serialWriteHandle->serialManagerHandle;
+
+ assert(handle);
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+ assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback)));
+
+ primask = DisableGlobalIRQ();
+ if (NULL != serialWriteHandle->transfer.buffer)
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ serialWriteHandle->transfer.buffer = buffer;
+ serialWriteHandle->transfer.length = length;
+ serialWriteHandle->transfer.soFar = 0U;
+ serialWriteHandle->transfer.mode = mode;
+
+ if (NULL == LIST_GetHead(&handle->runningWriteHandleHead))
+ {
+ isEmpty = 1U;
+ }
+ SerialManager_AddTail(&handle->runningWriteHandleHead, serialWriteHandle);
+ EnableGlobalIRQ(primask);
+
+ if (0U != isEmpty)
+ {
+ status = SerialManager_StartWriting(handle);
+ if ((serial_manager_status_t)kStatus_SerialManager_Success != status)
+ {
+ return status;
+ }
+ }
+
+ if (kSerialManager_TransmissionBlocking == mode)
+ {
+ while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar)
+ {
+#if defined(__GIC_PRIO_BITS)
+ if (0x13 == (__get_CPSR() & CPSR_M_Msk))
+#else
+ if (0U != __get_IPSR())
+#endif
+ {
+ SerialManager_IsrFunction(handle);
+ }
+ }
+ }
+ return kStatus_SerialManager_Success;
+}
+
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ serial_manager_transmission_mode_t mode,
+ uint32_t *receivedLength)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+ serial_manager_handle_t *handle;
+ uint32_t dataLength;
+ uint32_t primask;
+
+ assert(readHandle);
+ assert(buffer);
+ assert(length);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+ handle = serialReadHandle->serialManagerHandle;
+
+ assert(handle);
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+ assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback)));
+
+ primask = DisableGlobalIRQ();
+ if (NULL != serialReadHandle->transfer.buffer)
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ serialReadHandle->transfer.buffer = buffer;
+ serialReadHandle->transfer.length = length;
+ serialReadHandle->transfer.soFar = 0U;
+ serialReadHandle->transfer.mode = mode;
+
+ dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
+ dataLength = dataLength % handle->ringBuffer.ringBufferSize;
+
+ for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length);
+ serialReadHandle->transfer.soFar++)
+ {
+ buffer[serialReadHandle->transfer.soFar] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];
+ handle->ringBuffer.ringTail++;
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringTail = 0U;
+ }
+ }
+
+ dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
+ dataLength = dataLength % handle->ringBuffer.ringBufferSize;
+ dataLength = handle->ringBuffer.ringBufferSize - 1U - dataLength;
+
+ (void)SerialManager_StartReading(handle, readHandle, NULL, dataLength);
+
+ if (NULL != receivedLength)
+ {
+ *receivedLength = serialReadHandle->transfer.soFar;
+ serialReadHandle->transfer.buffer = NULL;
+ EnableGlobalIRQ(primask);
+ }
+ else
+ {
+ if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)
+ {
+ serialReadHandle->transfer.buffer = NULL;
+ EnableGlobalIRQ(primask);
+ if (kSerialManager_TransmissionNonBlocking == mode)
+ {
+ if (NULL != serialReadHandle->callback)
+ {
+ serial_manager_callback_message_t msg;
+ msg.buffer = buffer;
+ msg.length = serialReadHandle->transfer.soFar;
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Success);
+ }
+ }
+ }
+ else
+ {
+ EnableGlobalIRQ(primask);
+ }
+
+ if (kSerialManager_TransmissionBlocking == mode)
+ {
+ while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar)
+ {
+ }
+ }
+ }
+
+ return kStatus_SerialManager_Success;
+}
+
+#else
+
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+ serial_manager_handle_t *handle;
+
+ assert(writeHandle);
+ assert(buffer);
+ assert(length);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+ handle = serialWriteHandle->serialManagerHandle;
+
+ assert(handle);
+
+ return SerialManager_StartWriting(handle, serialWriteHandle, buffer, length);
+}
+
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+ serial_manager_handle_t *handle;
+
+ assert(readHandle);
+ assert(buffer);
+ assert(length);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+ handle = serialReadHandle->serialManagerHandle;
+
+ assert(handle);
+
+ return SerialManager_StartReading(handle, serialReadHandle, buffer, length);
+}
+#endif
+
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ assert(config);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ assert(config->ringBuffer);
+ assert(config->ringBufferSize);
+#endif
+ assert(serialHandle);
+ assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t));
+
+ handle = (serial_manager_handle_t *)serialHandle;
+
+ (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+
+ COMMON_TASK_init();
+
+#else
+ if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)handle->event, true))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)handle->taskId, OSA_TASK(SerialManager_Task), handle))
+ {
+ return kStatus_SerialManager_Error;
+ }
+#endif
+
+#endif
+
+#endif
+
+ handle->type = config->type;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ handle->ringBuffer.ringBuffer = config->ringBuffer;
+ handle->ringBuffer.ringBufferSize = config->ringBufferSize;
+#endif
+
+ switch (config->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if ((serial_manager_status_t)kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UartInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ if ((serial_manager_status_t)kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UartInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_RxCallback, handle);
+ }
+ }
+#endif
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_RxCallback, handle);
+ }
+ }
+#endif
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_SwoInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ }
+#endif
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcVirtualInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcVirtualInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_RxCallback, handle);
+ }
+ }
+#endif
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+
+ return status;
+}
+
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle)
+{
+ serial_manager_handle_t *handle;
+ uint32_t primask;
+
+ assert(serialHandle);
+
+ handle = (serial_manager_handle_t *)serialHandle;
+
+ primask = DisableGlobalIRQ();
+ if ((NULL != handle->openedReadHandleHead) || (0U != handle->openedWriteHandleCount))
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ EnableGlobalIRQ(primask);
+
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ (void)Serial_UartDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ (void)Serial_UsbCdcDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ (void)Serial_UsbCdcVirtualDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ OSA_EventDestroy((osa_event_handle_t)handle->event);
+ OSA_TaskDestroy((osa_task_handle_t)handle->taskId);
+#endif
+
+#endif
+
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_write_handle_t *serialWriteHandle;
+ uint32_t primask;
+
+ assert(serialHandle);
+ assert(writeHandle);
+ assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t));
+
+ handle = (serial_manager_handle_t *)serialHandle;
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+ (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);
+
+ primask = DisableGlobalIRQ();
+ handle->openedWriteHandleCount++;
+ EnableGlobalIRQ(primask);
+
+ serialWriteHandle->serialManagerHandle = handle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG;
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_write_handle_t *serialWriteHandle;
+ uint32_t primask;
+
+ assert(writeHandle);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+ handle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle;
+
+ assert(handle);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ (void)SerialManager_CancelWriting(writeHandle);
+#endif
+ primask = DisableGlobalIRQ();
+ if (handle->openedWriteHandleCount > 0U)
+ {
+ handle->openedWriteHandleCount--;
+ }
+ EnableGlobalIRQ(primask);
+
+ (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_read_handle_t *serialReadHandle;
+ uint32_t primask;
+
+ assert(serialHandle);
+ assert(readHandle);
+ assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t));
+
+ handle = (serial_manager_handle_t *)serialHandle;
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+ primask = DisableGlobalIRQ();
+ if (handle->openedReadHandleHead != NULL)
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ handle->openedReadHandleHead = serialReadHandle;
+ EnableGlobalIRQ(primask);
+
+ (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);
+
+ serialReadHandle->serialManagerHandle = handle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serialReadHandle->tag = SERIAL_MANAGER_READ_TAG;
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_read_handle_t *serialReadHandle;
+ uint32_t primask;
+
+ assert(readHandle);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+ handle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle;
+
+ assert(handle && (handle->openedReadHandleHead == serialReadHandle));
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ (void)SerialManager_CancelReading(readHandle);
+#endif
+
+ primask = DisableGlobalIRQ();
+ handle->openedReadHandleHead = NULL;
+ EnableGlobalIRQ(primask);
+
+ (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking);
+#else
+ return SerialManager_Write(writeHandle, buffer, length);
+#endif
+}
+
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL);
+#else
+ return SerialManager_Read(readHandle, buffer, length);
+#endif
+}
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking);
+}
+
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL);
+}
+
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+ uint32_t primask;
+ uint8_t isNotUsed = 0;
+
+ assert(writeHandle);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+ assert(serialWriteHandle->serialManagerHandle);
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+
+ if ((NULL != serialWriteHandle->transfer.buffer) &&
+ (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ primask = DisableGlobalIRQ();
+ if (serialWriteHandle != (serial_manager_write_handle_t *)(void *)LIST_GetHead(
+ &serialWriteHandle->serialManagerHandle->runningWriteHandleHead))
+ {
+ (void)LIST_RemoveElement(&serialWriteHandle->link);
+ isNotUsed = 1;
+ }
+ EnableGlobalIRQ(primask);
+
+ if (0U != isNotUsed)
+ {
+ serialWriteHandle->transfer.soFar = 0;
+ serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled;
+
+ SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle);
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task;
+ serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = serialWriteHandle->serialManagerHandle;
+ COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg);
+#else
+ (void)OSA_EventSet((osa_event_handle_t)serialWriteHandle->serialManagerHandle->event, SERIAL_EVENT_DATA_SENT);
+#endif
+
+#else
+ SerialManager_Task(serialWriteHandle->serialManagerHandle);
+#endif
+ }
+ else
+ {
+ switch (serialWriteHandle->serialManagerHandle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ (void)Serial_UartCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ (void)Serial_UsbCdcCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ (void)Serial_SwoCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ (void)Serial_UsbCdcVirtualCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+ }
+
+ (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+ serial_manager_callback_message_t msg;
+ uint8_t *buffer;
+ uint32_t primask;
+
+ assert(readHandle);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+
+ if ((NULL != serialReadHandle->transfer.buffer) &&
+ (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ primask = DisableGlobalIRQ();
+ buffer = serialReadHandle->transfer.buffer;
+ serialReadHandle->transfer.buffer = NULL;
+ serialReadHandle->transfer.length = 0;
+ msg.buffer = buffer;
+ msg.length = serialReadHandle->transfer.soFar;
+ EnableGlobalIRQ(primask);
+
+ if (NULL != buffer)
+ {
+ if (NULL != serialReadHandle->callback)
+ {
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Canceled);
+ }
+ }
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ uint32_t *receivedLength)
+{
+ assert(receivedLength);
+
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength);
+}
+
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+
+ assert(writeHandle);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+
+ serialWriteHandle->callbackParam = callbackParam;
+ serialWriteHandle->callback = callback;
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+
+ assert(readHandle);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+
+ serialReadHandle->callbackParam = callbackParam;
+ serialReadHandle->callback = callback;
+
+ return kStatus_SerialManager_Success;
+}
+#endif
+
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ assert(serialHandle);
+
+ handle = (serial_manager_handle_t *)serialHandle;
+
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartEnterLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+ return status;
+}
+
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ assert(serialHandle);
+
+ handle = (serial_manager_handle_t *)serialHandle;
+
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartExitLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+ return status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_manager.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_manager.h new file mode 100644 index 000000000..7cbb6c75a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_manager.h @@ -0,0 +1,553 @@ +/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_MANAGER_H__
+#define __SERIAL_MANAGER_H__
+
+/*!
+ * @addtogroup serialmanager
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
+#endif
+#endif
+
+/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_UART
+#define SERIAL_PORT_TYPE_UART (0U)
+#endif
+
+/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_USBCDC
+#define SERIAL_PORT_TYPE_USBCDC (0U)
+#endif
+
+/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_SWO
+#define SERIAL_PORT_TYPE_SWO (0U)
+#endif
+
+/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL
+#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U)
+#endif
+
+/*! @brief Set serial manager write handle size */
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)
+#else
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#include "serial_port_uart.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for USB CDC.
+#endif
+
+#include "serial_port_usb.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+#include "serial_port_swo.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for USB CDC.
+#endif
+
+#include "serial_port_usb_virtual.h"
+#endif
+
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+
+#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+
+#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+
+#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+
+#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE
+#endif
+
+#endif
+
+/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
+#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
+#else
+#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time.
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U)
+#else
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
+#endif
+
+#define SERIAL_MANAGER_USE_COMMON_TASK (1U)
+#define SERIAL_MANAGER_TASK_PRIORITY (2U)
+#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
+
+typedef void *serial_handle_t;
+typedef void *serial_write_handle_t;
+typedef void *serial_read_handle_t;
+
+/*! @brief serial port type*/
+typedef enum _serial_port_type
+{
+ kSerialPort_Uart = 1U, /*!< Serial port UART */
+ kSerialPort_UsbCdc, /*!< Serial port USB CDC */
+ kSerialPort_Swo, /*!< Serial port SWO */
+ kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */
+} serial_port_type_t;
+
+/*! @brief serial manager config structure*/
+typedef struct _serial_manager_config
+{
+ uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware.
+ Besides, the memory space cannot be free during the lifetime of the serial
+ manager module. */
+ uint32_t ringBufferSize; /*!< The size of the ring buffer */
+ serial_port_type_t type; /*!< Serial port type */
+ void *portConfig; /*!< Serial port configuration */
+} serial_manager_config_t;
+
+/*! @brief serial manager error code*/
+typedef enum _serial_manager_status
+{
+ kStatus_SerialManager_Success = kStatus_Success, /*!< Success */
+ kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
+ kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
+ kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
+ kStatus_SerialManager_Canceled =
+ MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
+ kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
+ kStatus_SerialManager_RingBufferOverflow =
+ MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
+} serial_manager_status_t;
+
+/*! @brief Callback message structure */
+typedef struct _serial_manager_callback_message
+{
+ uint8_t *buffer; /*!< Transferred buffer */
+ uint32_t length; /*!< Transferred data length */
+} serial_manager_callback_message_t;
+
+/*! @brief callback function */
+typedef void (*serial_manager_callback_t)(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
+ *
+ * This function configures the Serial Manager module with user-defined settings. The user can configure the
+ * configuration
+ * structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
+ * allocated by the caller.
+ * The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB
+ * CDC.
+ * Please refer to #serial_port_type_t for serial port setting. These two types can be set by using
+ * #serial_manager_config_t.
+ *
+ * Example below shows how to use this API to configure the Serial Manager.
+ * For UART,
+ * @code
+ * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+ * static uint32_t s_serialHandleBuffer[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];
+ * static serial_handle_t s_serialHandle = (serial_handle_t)&s_serialHandleBuffer[0];
+ * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *
+ * serial_manager_config_t config;
+ * serial_port_uart_config_t uartConfig;
+ * config.type = kSerialPort_Uart;
+ * config.ringBuffer = &s_ringBuffer[0];
+ * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ * uartConfig.instance = 0;
+ * uartConfig.clockRate = 24000000;
+ * uartConfig.baudRate = 115200;
+ * uartConfig.parityMode = kSerialManager_UartParityDisabled;
+ * uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
+ * uartConfig.enableRx = 1;
+ * uartConfig.enableTx = 1;
+ * config.portConfig = &uartConfig;
+ * SerialManager_Init(s_serialHandle, &config);
+ * @endcode
+ * For USB CDC,
+ * @code
+ * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+ * static uint32_t s_serialHandleBuffer[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];
+ * static serial_handle_t s_serialHandle = (serial_handle_t)&s_serialHandleBuffer[0];
+ * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *
+ * serial_manager_config_t config;
+ * serial_port_usb_cdc_config_t usbCdcConfig;
+ * config.type = kSerialPort_UsbCdc;
+ * config.ringBuffer = &s_ringBuffer[0];
+ * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
+ * config.portConfig = &usbCdcConfig;
+ * SerialManager_Init(s_serialHandle, &config);
+ * @endcode
+ *
+ * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @param config Pointer to user-defined configuration structure.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
+ */
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config);
+
+/*!
+ * @brief De-initializes the serial manager module instance.
+ *
+ * This function de-initializes the serial manager module instance. If the opened writing or
+ * reading handle is not closed, the function will return kStatus_SerialManager_Busy.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
+ * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
+ */
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
+
+/*!
+ * @brief Opens a writing handle for the serial manager module.
+ *
+ * This function Opens a writing handle for the serial manager module. If the serial manager needs to
+ * be used in different tasks, the task should open a dedicated write handle for itself by calling
+ * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
+ * handle at the same time, multiple writing handles need to be opened when the multiple transmission
+ * is needed for a task.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @param writeHandle The serial manager module writing handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
+ * @retval kStatus_SerialManager_Success The writing handle is opened.
+ *
+ * Example below shows how to use this API to write data.
+ * For task 1,
+ * @code
+ * static uint32_t s_serialWriteHandleBuffer1[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1) /
+ * sizeof(uitn32_t))]; static serial_write_handle_t s_serialWriteHandle1 =
+ * (serial_write_handle_t)&s_serialWriteHandleBuffer1[0]; static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking
+ * writing log for task1!\r\n"; SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1);
+ * SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1);
+ * SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1);
+ * @endcode
+ * For task 2,
+ * @code
+ * static uint32_t s_serialWriteHandleBuffer2[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1) /
+ * sizeof(uitn32_t))]; static serial_write_handle_t s_serialWriteHandle2 =
+ * (serial_write_handle_t)&s_serialWriteHandleBuffer2[0]; static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking
+ * writing log for task2!\r\n"; SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2);
+ * SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2);
+ * SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1);
+ * @endcode
+ */
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Closes a writing handle for the serial manager module.
+ *
+ * This function Closes a writing handle for the serial manager module.
+ *
+ * @param writeHandle The serial manager module writing handle pointer.
+ * @retval kStatus_SerialManager_Success The writing handle is closed.
+ */
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Opens a reading handle for the serial manager module.
+ *
+ * This function Opens a reading handle for the serial manager module. The reading handle can not be
+ * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
+ * the previous reading handle is not closed. And There can only be one buffer for receiving for the
+ * reading handle at the same time.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @param readHandle The serial manager module reading handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_Success The reading handle is opened.
+ * @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
+ *
+ * Example below shows how to use this API to read data.
+ * @code
+ * static uint32_t s_serialReadHandleBuffer[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1) /
+ * sizeof(uitn32_t))]; static serial_read_handle_t s_serialReadHandle =
+ * (serial_read_handle_t)&s_serialReadHandleBuffer[0]; SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle);
+ * static uint8_t s_nonBlockingBuffer[64];
+ * SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle);
+ * SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer));
+ * @endcode
+ */
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
+
+/*!
+ * @brief Closes a reading for the serial manager module.
+ *
+ * This function Closes a reading for the serial manager module.
+ *
+ * @param readHandle The serial manager module reading handle pointer.
+ * @retval kStatus_SerialManager_Success The reading handle is closed.
+ */
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
+
+/*!
+ * @brief Transmits data with the blocking mode.
+ *
+ * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for transmission for the writing handle at the same time.
+ *
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
+ * cannot be used at the same time.
+ * And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SerialManager_Success Successfully sent all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Reads data with the blocking mode.
+ *
+ * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
+ * cannot be used at the same time.
+ * And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief Transmits data with the non-blocking mode.
+ *
+ * This is a non-blocking function, which returns directly without waiting for all data to be sent.
+ * When all data is sent, the module notifies the upper layer through a TX callback function and passes
+ * the status parameter @ref kStatus_SerialManager_Success.
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for transmission for the writing handle at the same time.
+ *
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
+ * cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SerialManager_Success Successfully sent all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Reads data with the non-blocking mode.
+ *
+ * This is a non-blocking function, which returns directly without waiting for all data to be received.
+ * When all data is received, the module driver notifies the upper layer
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
+ * cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Tries to read data.
+ *
+ * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
+ * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
+ * After the data is copied, the actual data length is passed by the parameter length.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @param receivedLength Length received from the ring buffer directly.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ uint32_t *receivedLength);
+
+/*!
+ * @brief Cancels unfinished send transmission.
+ *
+ * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
+ * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
+ *
+ * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
+ * the function #SerialManager_WriteBlocking.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Get successfully abort the sending.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Cancels unfinished receive transmission.
+ *
+ * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
+ * layer
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
+ *
+ * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
+ * the function #SerialManager_ReadBlocking.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Get successfully abort the receiving.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
+
+/*!
+ * @brief Installs a TX callback and callback parameter.
+ *
+ * This function is used to install the TX callback and callback parameter for the serial manager module.
+ * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_SerialManager_Success Successfully install the callback.
+ */
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Installs a RX callback and callback parameter.
+ *
+ * This function is used to install the RX callback and callback parameter for the serial manager module.
+ * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_SerialManager_Success Successfully install the callback.
+ */
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+
+#endif
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Successful operation.
+ */
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Successful operation.
+ */
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+#endif /* __SERIAL_MANAGER_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_internal.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_internal.h new file mode 100644 index 000000000..004852335 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_internal.h @@ -0,0 +1,99 @@ +/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_INTERNAL_H__
+#define __SERIAL_PORT_INTERNAL_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_UartIsrFunction(serial_handle_t serialHandle);
+#endif
+serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_SwoIsrFunction(serial_handle_t serialHandle);
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+serial_manager_status_t Serial_UsbCdcVirtualInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_UsbCdcVirtualDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcVirtualCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcVirtualInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_UsbCdcVirtualInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_UsbCdcVirtualIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __SERIAL_PORT_INTERNAL_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.c new file mode 100644 index 000000000..799e85ac3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.c @@ -0,0 +1,403 @@ +/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+#include "serial_port_internal.h"
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#include "uart.h"
+
+#include "serial_port_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U
+
+typedef struct _serial_uart_send_state
+{
+ serial_manager_callback_t callback;
+ void *callbackParam;
+ uint8_t *buffer;
+ uint32_t length;
+ volatile uint8_t busy;
+} serial_uart_send_state_t;
+
+typedef struct _serial_uart_recv_state
+{
+ serial_manager_callback_t callback;
+ void *callbackParam;
+ volatile uint8_t busy;
+ uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];
+} serial_uart_recv_state_t;
+#endif
+
+typedef struct _serial_uart_state
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serial_uart_send_state_t tx;
+ serial_uart_recv_state_t rx;
+#endif
+ uint8_t usartHandleBuffer[HAL_UART_HANDLE_SIZE];
+} serial_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/* UART user callback */
+static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)
+{
+ serial_uart_state_t *serialUartHandle;
+ serial_manager_callback_message_t msg;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ hal_uart_transfer_t transfer;
+#endif
+
+ if (NULL == userData)
+ {
+ return;
+ }
+
+ serialUartHandle = (serial_uart_state_t *)userData;
+
+ if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status)
+ {
+ if ((NULL != serialUartHandle->rx.callback))
+ {
+ msg.buffer = &serialUartHandle->rx.readBuffer[0];
+ msg.length = sizeof(serialUartHandle->rx.readBuffer);
+ serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success);
+ }
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ transfer.data = &serialUartHandle->rx.readBuffer[0];
+ transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
+ if (kStatus_HAL_UartSuccess ==
+ HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+ if ((hal_uart_status_t)kStatus_HAL_UartSuccess ==
+ HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
+#endif
+ {
+ serialUartHandle->rx.busy = 1U;
+ }
+ else
+ {
+ serialUartHandle->rx.busy = 0U;
+ }
+ }
+ else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status)
+ {
+ if (0U != serialUartHandle->tx.busy)
+ {
+ serialUartHandle->tx.busy = 0U;
+ if ((NULL != serialUartHandle->tx.callback))
+ {
+ msg.buffer = serialUartHandle->tx.buffer;
+ msg.length = serialUartHandle->tx.length;
+ serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success);
+ }
+ }
+ }
+ else
+ {
+ }
+}
+#endif
+
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)
+{
+ serial_uart_state_t *serialUartHandle;
+ serial_port_uart_config_t *uartConfig;
+ hal_uart_config_t config;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ hal_uart_transfer_t transfer;
+#endif
+#endif
+
+ assert(serialConfig);
+ assert(serialHandle);
+ assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t));
+
+ uartConfig = (serial_port_uart_config_t *)serialConfig;
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ config.baudRate_Bps = uartConfig->baudRate;
+ config.parityMode = (hal_uart_parity_mode_t)uartConfig->parityMode;
+ config.stopBitCount = (hal_uart_stop_bit_count_t)uartConfig->stopBitCount;
+ config.enableRx = uartConfig->enableRx;
+ config.enableTx = uartConfig->enableTx;
+ config.srcClock_Hz = uartConfig->clockRate;
+ config.instance = uartConfig->instance;
+
+ if (kStatus_HAL_UartSuccess != HAL_UartInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &config))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ Serial_UartCallback, serialUartHandle))
+#else
+ if (kStatus_HAL_UartSuccess != HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ Serial_UartCallback, serialUartHandle))
+#endif
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ if (0U != uartConfig->enableRx)
+ {
+ serialUartHandle->rx.busy = 1U;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ transfer.data = &serialUartHandle->rx.readBuffer[0];
+ transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
+#endif
+ {
+ serialUartHandle->rx.busy = 0U;
+ return kStatus_SerialManager_Error;
+ }
+ }
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+ (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+#endif
+ (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serialUartHandle->tx.busy = 0U;
+ serialUartHandle->rx.busy = 0U;
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_uart_state_t *serialUartHandle;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ hal_uart_transfer_t transfer;
+#endif
+
+ assert(serialHandle);
+ assert(buffer);
+ assert(length);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ if (0U != serialUartHandle->tx.busy)
+ {
+ return kStatus_SerialManager_Busy;
+ }
+ serialUartHandle->tx.busy = 1U;
+
+ serialUartHandle->tx.buffer = buffer;
+ serialUartHandle->tx.length = length;
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ transfer.data = buffer;
+ transfer.dataSize = length;
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length))
+#endif
+ {
+ serialUartHandle->tx.busy = 0U;
+ return kStatus_SerialManager_Error;
+ }
+ return kStatus_SerialManager_Success;
+}
+
+#else
+
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+ assert(buffer);
+ assert(length);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ buffer, length);
+}
+
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+ assert(buffer);
+ assert(length);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ return (serial_manager_status_t)HAL_UartReceiveBlocking(
+ ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
+}
+
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+ serial_manager_callback_message_t msg;
+ uint32_t primask;
+ uint8_t isBusy = 0U;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ primask = DisableGlobalIRQ();
+ isBusy = serialUartHandle->tx.busy;
+ serialUartHandle->tx.busy = 0U;
+ EnableGlobalIRQ(primask);
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+ (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+ if (0U != isBusy)
+ {
+ if ((NULL != serialUartHandle->tx.callback))
+ {
+ msg.buffer = serialUartHandle->tx.buffer;
+ msg.length = serialUartHandle->tx.length;
+ serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled);
+ }
+ }
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ serialUartHandle->tx.callback = callback;
+ serialUartHandle->tx.callbackParam = callbackParam;
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ serialUartHandle->rx.callback = callback;
+ serialUartHandle->rx.callbackParam = callbackParam;
+
+ return kStatus_SerialManager_Success;
+}
+
+void Serial_UartIsrFunction(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+}
+#endif
+
+serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ if (kStatus_HAL_UartSuccess != HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ if (kStatus_HAL_UartSuccess != HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ return kStatus_SerialManager_Success;
+}
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.h new file mode 100644 index 000000000..aa412479d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.h @@ -0,0 +1,57 @@ +/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_UART_H__
+#define __SERIAL_PORT_UART_H__
+
+#include "uart.h"
+
+/*!
+ * @addtogroup serial_port_uart
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief serial port uart handle size*/
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_PORT_UART_HANDLE_SIZE (76U + HAL_UART_HANDLE_SIZE)
+#else
+#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE)
+#endif
+
+/*! @brief serial port uart parity mode*/
+typedef enum _serial_port_uart_parity_mode
+{
+ kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
+ kSerialManager_UartParityEven = 0x1U, /*!< Parity even enabled */
+ kSerialManager_UartParityOdd = 0x2U, /*!< Parity odd enabled */
+} serial_port_uart_parity_mode_t;
+
+/*! @brief serial port uart stop bit count*/
+typedef enum _serial_port_uart_stop_bit_count
+{
+ kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
+ kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
+} serial_port_uart_stop_bit_count_t;
+
+/*! @brief serial port uart config struct*/
+typedef struct _serial_port_uart_config
+{
+ uint32_t clockRate; /*!< clock rate */
+ uint32_t baudRate; /*!< baud rate */
+ serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+ serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
+ please refer to the SOC corresponding RM. */
+ uint8_t enableRx; /*!< Enable RX */
+ uint8_t enableTx; /*!< Enable TX */
+} serial_port_uart_config_t;
+/*! @} */
+#endif /* __SERIAL_PORT_UART_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/uart/uart.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/uart/uart.h new file mode 100644 index 000000000..6961883aa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/uart/uart.h @@ -0,0 +1,502 @@ +/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_UART_ADAPTER_H__
+#define __HAL_UART_ADAPTER_H__
+
+#if defined(FSL_RTOS_FREE_RTOS)
+#include "FreeRTOS.h"
+#endif
+
+/*!
+ * @addtogroup UART_Adapter
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
+#else
+#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
+#endif
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+#define HAL_UART_ISR_PRIORITY (25U)
+#else
+#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#else
+/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
+ * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
+ * priority is 3 (2^2 - 1). So, the default value is 3.
+ */
+#define HAL_UART_ISR_PRIORITY (3U)
+#endif
+#endif
+
+#ifndef HAL_UART_ADAPTER_LOWPOWER
+#define HAL_UART_ADAPTER_LOWPOWER (0U)
+#endif /* HAL_UART_ADAPTER_LOWPOWER */
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#define HAL_UART_HANDLE_SIZE (90U + HAL_UART_ADAPTER_LOWPOWER * 16U)
+#else
+#define HAL_UART_HANDLE_SIZE (4U + HAL_UART_ADAPTER_LOWPOWER * 16U)
+#endif
+
+/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
+#define HAL_UART_TRANSFER_MODE (0U)
+
+typedef void *hal_uart_handle_t;
+
+/*! @brief UART status */
+typedef enum _hal_uart_status
+{
+ kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */
+ kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
+ kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
+ kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
+ kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
+ kStatus_HAL_UartBaudrateNotSupport =
+ MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
+ kStatus_HAL_UartProtocolError = MAKE_STATUS(
+ kStatusGroup_HAL_UART,
+ 6), /*!< Error occurs for Noise, Framing, Parity, etc.
+ For transactional transfer, The up layer needs to abort the transfer and then starts again */
+ kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
+} hal_uart_status_t;
+
+/*! @brief UART parity mode. */
+typedef enum _hal_uart_parity_mode
+{
+ kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
+ kHAL_UartParityEven = 0x1U, /*!< Parity even enabled */
+ kHAL_UartParityOdd = 0x2U, /*!< Parity odd enabled */
+} hal_uart_parity_mode_t;
+
+/*! @brief UART stop bit count. */
+typedef enum _hal_uart_stop_bit_count
+{
+ kHAL_UartOneStopBit = 0U, /*!< One stop bit */
+ kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
+} hal_uart_stop_bit_count_t;
+
+/*! @brief UART configuration structure. */
+typedef struct _hal_uart_config
+{
+ uint32_t srcClock_Hz; /*!< Source clock */
+ uint32_t baudRate_Bps; /*!< Baud rate */
+ hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+ hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+ uint8_t enableRx; /*!< Enable RX */
+ uint8_t enableTx; /*!< Enable TX */
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
+ SOC corresponding RM.
+ Invalid instance value will cause initialization failure. */
+} hal_uart_config_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
+
+/*! @brief UART transfer structure. */
+typedef struct _hal_uart_transfer
+{
+ uint8_t *data; /*!< The buffer of data to be transfer.*/
+ size_t dataSize; /*!< The byte count to be transfer. */
+} hal_uart_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance with the UART handle and the user configuration structure.
+ *
+ * This function configures the UART module with user-defined settings. The user can configure the configuration
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
+ * the caller. Example below shows how to use this API to configure the UART.
+ * @code
+ * uint32_t g_UartHandleBuffer[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];
+ * hal_uart_handle_t g_UartHandle = (hal_uart_handle_t)&g_UartHandleBuffer[0];
+ * hal_uart_config_t config;
+ * config.srcClock_Hz = 48000000;
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kHAL_UartParityDisabled;
+ * config.stopBitCount = kHAL_UartOneStopBit;
+ * config.enableRx = 1;
+ * config.enableTx = 1;
+ * config.instance = 0;
+ * HAL_UartInit(g_UartHandle, &config);
+ * @endcode
+ *
+ * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @param config Pointer to user-defined configuration structure.
+ * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_HAL_UartSuccess UART initialization succeed
+ */
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config);
+
+/*!
+ * @brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess UART de-initialization succeed
+ */
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
+
+/*! @}*/
+
+/*!
+ * @name Blocking bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Reads RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the RX register.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ * And, the function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_HAL_UartError An error occurred while receiving data.
+ * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
+ * @retval kStatus_HAL_UartSuccess Successfully received all data.
+ */
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ * And, the function #HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully sent all data.
+ */
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
+
+/*! @}*/
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+/*!
+ * @name Transactional
+ * @note The transactional API and the functional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When any status of the UART changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART driver.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure, see #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure. See #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#else
+
+/*!
+ * @name Functional API with non-blocking mode.
+ * @note The functional API and the transactional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART adapter.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART adapter notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#endif
+#endif
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess Successful operation.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess Successful operation.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle);
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * @param handle UART handle pointer.
+ */
+void HAL_UartIsrFunction(hal_uart_handle_t handle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /* __HAL_UART_ADAPTER_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/uart/usart_adapter.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/uart/usart_adapter.c new file mode 100644 index 000000000..228d90b25 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/uart/usart_adapter.c @@ -0,0 +1,643 @@ +/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_usart.h"
+#include "fsl_flexcomm.h"
+
+#include "uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_receive_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_send_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_send_state_t;
+#endif
+/*! @brief uart state structure. */
+typedef struct _hal_uart_state
+{
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ hal_uart_transfer_callback_t callback;
+ void *callbackParam;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ usart_handle_t hardwareHandle;
+#endif
+ hal_uart_receive_state_t rx;
+ hal_uart_send_state_t tx;
+#endif
+ uint8_t instance;
+} hal_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+/* Array of USART IRQ number. */
+static const IRQn_Type s_UsartIRQ[] = USART_IRQS;
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ hal_uart_status_t uartStatus = kStatus_HAL_UartError;
+ switch (status)
+ {
+ case kStatus_Success:
+ uartStatus = kStatus_HAL_UartSuccess;
+ break;
+ case kStatus_USART_TxBusy:
+ uartStatus = kStatus_HAL_UartTxBusy;
+ break;
+ case kStatus_USART_RxBusy:
+ uartStatus = kStatus_HAL_UartRxBusy;
+ break;
+ case kStatus_USART_TxIdle:
+ uartStatus = kStatus_HAL_UartTxIdle;
+ break;
+ case kStatus_USART_RxIdle:
+ uartStatus = kStatus_HAL_UartRxIdle;
+ break;
+ case kStatus_USART_BaudrateNotSupport:
+ uartStatus = kStatus_HAL_UartBaudrateNotSupport;
+ break;
+ case kStatus_USART_NoiseError:
+ case kStatus_USART_FramingError:
+ case kStatus_USART_ParityError:
+ uartStatus = kStatus_HAL_UartProtocolError;
+ break;
+ default:
+ break;
+ }
+ return uartStatus;
+}
+#else
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ if (kStatus_Success == status)
+ {
+ return kStatus_HAL_UartSuccess;
+ }
+ else
+ {
+ return kStatus_HAL_UartError;
+ }
+}
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+ assert(callbackParam);
+
+ uartHandle = (hal_uart_state_t *)callbackParam;
+
+ if (kStatus_HAL_UartProtocolError == uartStatus)
+ {
+ if (uartHandle->hardwareHandle.rxDataSize)
+ {
+ uartStatus = kStatus_HAL_UartError;
+ }
+ }
+
+ if (uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
+ }
+}
+
+#else
+
+static void HAL_UartInterruptHandle(USART_Type *base, void *handle)
+{
+ hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;
+ uint32_t status;
+ uint8_t instance;
+
+ if (NULL == uartHandle)
+ {
+ return;
+ }
+ instance = uartHandle->instance;
+
+ status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);
+
+ /* Receive data register full */
+ if ((USART_FIFOSTAT_RXNOTEMPTY_MASK & status) &&
+ (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK))
+ {
+ if (uartHandle->rx.buffer)
+ {
+ uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);
+ if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[instance],
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+ uartHandle->rx.buffer = NULL;
+ if (uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+ /* Send data register empty and the interrupt is enabled. */
+ if ((USART_FIFOSTAT_TXNOTFULL_MASK & status) &&
+ (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK))
+ {
+ if (uartHandle->tx.buffer)
+ {
+ USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
+ if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);
+ uartHandle->tx.buffer = NULL;
+ if (uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+#if 1
+ USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);
+#endif
+}
+#endif
+
+#endif
+
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config)
+{
+ hal_uart_state_t *uartHandle;
+ usart_config_t usartConfig;
+ status_t status;
+ assert(handle);
+ assert(config);
+ assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));
+ assert(s_UsartAdapterBase[config->instance]);
+
+ if (HAL_UART_HANDLE_SIZE < sizeof(hal_uart_state_t))
+ {
+ return kStatus_HAL_UartError;
+ }
+
+ USART_GetDefaultConfig(&usartConfig);
+ usartConfig.baudRate_Bps = config->baudRate_Bps;
+
+ if (kHAL_UartParityEven == config->parityMode)
+ {
+ usartConfig.parityMode = kUSART_ParityEven;
+ }
+ else if (kHAL_UartParityOdd == config->parityMode)
+ {
+ usartConfig.parityMode = kUSART_ParityOdd;
+ }
+ else
+ {
+ usartConfig.parityMode = kUSART_ParityDisabled;
+ }
+
+ if (kHAL_UartTwoStopBit == config->stopBitCount)
+ {
+ usartConfig.stopBitCount = kUSART_TwoStopBit;
+ }
+ else
+ {
+ usartConfig.stopBitCount = kUSART_OneStopBit;
+ }
+ usartConfig.enableRx = config->enableRx;
+ usartConfig.enableTx = config->enableTx;
+ usartConfig.txWatermark = kUSART_TxFifo0;
+ usartConfig.rxWatermark = kUSART_RxFifo1;
+
+ status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);
+
+ if (kStatus_Success != status)
+ {
+ return HAL_UartGetStatus(status);
+ }
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartHandle->instance = config->instance;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_callback_t)HAL_UartCallback, handle);
+#else
+ /* Enable interrupt in NVIC. */
+ FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], (flexcomm_irq_handler_t)HAL_UartInterruptHandle,
+ handle);
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[config->instance]);
+#endif
+
+#endif
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+#endif
+
+ status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+#endif
+
+ USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle)
+{
+ assert(handle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle)
+{
+ assert(handle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_t *)transfer, NULL);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_t *)transfer);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status =
+ USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#else
+
+/* None transactional API with non-blocking mode. */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+
+ uartHandle->rx.bufferLength = length;
+ uartHandle->rx.bufferSofar = 0;
+ uartHandle->rx.buffer = data;
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+ uartHandle->tx.bufferLength = length;
+ uartHandle->tx.bufferSofar = 0;
+ uartHandle->tx.buffer = (volatile uint8_t *)data;
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(reCount);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->rx.buffer)
+ {
+ *reCount = uartHandle->rx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(seCount);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->tx.buffer)
+ {
+ *seCount = uartHandle->tx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->rx.buffer)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+ uartHandle->rx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->tx.buffer)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);
+ uartHandle->tx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#endif
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+ USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#else
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+ HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/LPC54018.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/LPC54018.h new file mode 100644 index 000000000..dc9ce2ba0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/LPC54018.h @@ -0,0 +1,21082 @@ +/*
+** ###################################################################
+** Processors: LPC54018JBD208
+** LPC54018JET180
+**
+** Compilers: GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** Keil ARM C/C++ Compiler
+** MCUXpresso Compiler
+**
+** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+** Version: rev. 1.2, 2017-06-08
+** Build: b191118
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for LPC54018
+**
+** Copyright 1997-2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2016-08-12)
+** Initial version.
+** - rev. 1.1 (2016-11-25)
+** Update CANFD and Classic CAN register.
+** Add MAC TIMERSTAMP registers.
+** - rev. 1.2 (2017-06-08)
+** Remove RTC_CTRL_RTC_OSC_BYPASS.
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54018.h
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief CMSIS Peripheral Access Layer for LPC54018
+ *
+ * CMSIS Peripheral Access Layer for LPC54018
+ */
+
+#ifndef _LPC54018_H_
+#define _LPC54018_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
+ DMA0_IRQn = 1, /**< DMA controller */
+ GINT0_IRQn = 2, /**< GPIO group 0 */
+ GINT1_IRQn = 3, /**< GPIO group 1 */
+ PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
+ PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
+ PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
+ PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
+ UTICK0_IRQn = 8, /**< Micro-tick Timer */
+ MRT0_IRQn = 9, /**< Multi-rate timer */
+ CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
+ CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
+ SCT0_IRQn = 12, /**< SCTimer/PWM */
+ CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
+ FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+ FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+ FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+ ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
+ ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
+ ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
+ DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
+ HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
+ USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
+ USB0_IRQn = 28, /**< USB device */
+ RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
+ FLEXCOMM10_IRQn = 30, /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */
+ Reserved47_IRQn = 31, /**< Reserved interrupt */
+ PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
+ PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
+ PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
+ PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
+ CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
+ CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
+ RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
+ SPIFI0_IRQn = 39, /**< SPI flash interface */
+ FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+ SDIO_IRQn = 42, /**< SD/MMC */
+ CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
+ CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
+ CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
+ CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
+ USB1_IRQn = 47, /**< USB1 interrupt */
+ USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
+ ETHERNET_IRQn = 49, /**< Ethernet */
+ ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
+ ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
+ Reserved68_IRQn = 52, /**< Reserved interrupt */
+ LCD_IRQn = 53, /**< LCD interrupt */
+ SHA_IRQn = 54, /**< SHA interrupt */
+ SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
+ SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_LPC54018.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup dma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */
+ kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */
+ kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */
+ kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */
+ kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */
+ kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */
+ kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */
+ kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */
+ kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */
+ kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */
+ kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */
+ kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */
+ kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */
+ kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */
+ kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */
+ kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */
+ kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */
+ kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */
+ kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */
+ kDmaRequestSHA = 19U, /**< Secure Hash Algorithm */
+ kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */
+ kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */
+ kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */
+ kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */
+ kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */
+ kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */
+ kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */
+ kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */
+ kDmaRequestFlexcomm10Rx = 28U, /**< Flexcomm Interface 10 RX */
+ kDmaRequestFlexcomm10Tx = 29U, /**< Flexcomm Interface 10 TX */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #else
+ #pragma push
+ #pragma anon_unions
+ #endif
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
+ __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
+ __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
+ __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
+ uint8_t RESERVED_0[8];
+ __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
+ __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
+ __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
+ __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
+ __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
+ __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
+ __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
+ __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
+ __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
+ __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
+/*! @{ */
+#define ADC_CTRL_CLKDIV_MASK (0xFFU)
+#define ADC_CTRL_CLKDIV_SHIFT (0U)
+/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
+ * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
+ * software should program the smallest value in this field that yields this maximum clock rate or
+ * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
+ * be desirable. This field is ignored in the asynchronous operating mode.
+ */
+#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
+#define ADC_CTRL_ASYNMODE_MASK (0x100U)
+#define ADC_CTRL_ASYNMODE_SHIFT (8U)
+/*! ASYNMODE - Select clock mode.
+ * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
+ * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
+ * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
+ * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
+ * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
+ * pulse.
+ * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
+ */
+#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
+#define ADC_CTRL_RESOL_MASK (0x600U)
+#define ADC_CTRL_RESOL_SHIFT (9U)
+/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
+ * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
+ * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
+ * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
+ * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
+ * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
+ * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
+ * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
+ * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
+ * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
+ * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
+ */
+#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
+#define ADC_CTRL_BYPASSCAL_MASK (0x800U)
+#define ADC_CTRL_BYPASSCAL_SHIFT (11U)
+/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
+ * error is not a concern in the application.
+ * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
+ * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
+ * be warranted periodically - especially if operating conditions have changed.
+ * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
+ * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
+ */
+#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
+#define ADC_CTRL_TSAMP_MASK (0x7000U)
+#define ADC_CTRL_TSAMP_SHIFT (12U)
+/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
+ * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
+ * and the output impedance of the analog source, longer sampling times may be required. See
+ * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
+ * seven, by which the sample period will be extended. The total conversion time will increase by
+ * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
+ * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
+ * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
+ * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
+ * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
+ * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
+ * 22 ADC clocks.
+ */
+#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
+/*! @} */
+
+/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
+/*! @{ */
+#define ADC_INSEL_SEL_MASK (0x3U)
+#define ADC_INSEL_SEL_SHIFT (0U)
+/*! SEL - Selects the input source for channel 0. All other values are reserved.
+ * 0b00..ADC0_IN0 function.
+ * 0b11..Internal temperature sensor.
+ */
+#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
+/*! @{ */
+#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
+#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
+/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
+ * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
+ * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
+ * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
+ * software command, ADC conversions will be performed on each enabled channel, in sequence,
+ * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
+ * is LOW. It is allowed to change this field and set bit 31 in the same write.
+ */
+#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
+#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
+#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
+/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
+ * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
+ * to avoid generating a spurious trigger, it is recommended writing to this field only when
+ * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
+ */
+#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
+#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
+#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
+/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
+ * order to avoid generating a spurious trigger, it is recommended writing to this field only when
+ * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
+ * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
+ * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
+ */
+#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
+#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
+#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
+/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
+ * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
+ * conversion. There are slightly different criteria for whether or not this bit can be set
+ * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
+ * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
+ * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
+ * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
+ * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
+ * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
+ * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
+ * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
+ * maintained for one system clock period.
+ * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
+ * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
+ */
+#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
+#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
+#define ADC_SEQ_CTRL_START_SHIFT (26U)
+/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
+ * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
+ * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
+ * conversion sequence. It will consequently always read back as a zero.
+ */
+#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
+#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
+#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
+/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
+ * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
+ * can be halted by clearing this bit. The sequence currently in progress will be completed before
+ * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
+ */
+#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
+#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
+#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
+/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
+ * single conversion on the next channel in the sequence instead of the default response of
+ * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
+ * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
+ * channel. Interrupt generation will still occur either after each individual conversion or at
+ * the end of the entire sequence, depending on the state of the MODE bit.
+ */
+#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
+#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
+#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
+/*! LOWPRIO - Set priority for sequence A.
+ * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
+ * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
+ * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
+ * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
+ * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
+ * conversion sequence will resume from that point.
+ */
+#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
+#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
+#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
+/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
+ * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
+ * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
+ * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
+ * overrun conditions contribute to an overrun interrupt as described below.
+ * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
+ * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
+ * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
+ * if enabled.
+ * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
+ * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
+ * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
+ * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
+ */
+#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
+#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
+#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
+/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
+ * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
+ * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
+ * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
+ * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
+ * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
+ * triggered immediately upon being enabled.
+ * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
+ * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
+ * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
+ * 0b1..Enabled. Sequence n is enabled.
+ */
+#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
+/*! @} */
+
+/* The count of ADC_SEQ_CTRL */
+#define ADC_SEQ_CTRL_COUNT (2U)
+
+/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
+/*! @{ */
+#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
+#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
+/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
+ * performed under conversion sequence associated with this register. The result is a binary
+ * fraction representing the voltage on the currently-selected input channel as it falls within the
+ * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
+ * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
+ * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
+ * result has not yet been read.
+ */
+#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
+#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
+/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
+ * within the range established by the designated threshold comparison registers (THRn_LOW and
+ * THRn_HIGH).
+ */
+#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
+#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
+/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
+ * crossing of the threshold level established by the designated LOW threshold comparison register
+ * (THRn_LOW) and, if so, in what direction the crossing occurred.
+ */
+#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
+#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
+#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
+/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
+ * identifies channel 0, 0001 channel 1, etc.).
+ */
+#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
+#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
+#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
+/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
+ * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
+ * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
+ * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
+ * to '0' (and if the overrun interrupt is enabled).
+ */
+#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
+#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
+#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
+/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
+ * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
+ * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
+ * sequence is set to 0 (and if the interrupt is enabled).
+ */
+#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
+/*! @} */
+
+/* The count of ADC_SEQ_GDAT */
+#define ADC_SEQ_GDAT_COUNT (2U)
+
+/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
+/*! @{ */
+#define ADC_DAT_RESULT_MASK (0xFFF0U)
+#define ADC_DAT_RESULT_SHIFT (4U)
+/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
+ * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
+ * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
+ * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
+ * the voltage on the input was close to, equal to, or greater than that on VREFP.
+ */
+#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
+#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
+#define ADC_DAT_THCMPRANGE_SHIFT (16U)
+/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
+ * was greater than or equal to the value programmed into the designated LOW threshold register
+ * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
+ * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
+ * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
+ * completed conversion was greater than the value programmed into the designated HIGH threshold
+ * register (THRn_HIGH). 0x3 = Reserved.
+ */
+#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
+#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
+#define ADC_DAT_THCMPCROSS_SHIFT (18U)
+/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
+ * most recent completed conversion on this channel had the same relationship (above or below) to
+ * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
+ * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
+ * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
+ * previous sample on this channel was above the threshold value established by the designated LOW
+ * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
+ * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
+ * - i.e. the previous sample on this channel was below the threshold value established by the
+ * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
+ */
+#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
+#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
+#define ADC_DAT_CHANNEL_SHIFT (26U)
+/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
+ * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
+ * register, etc)
+ */
+#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
+#define ADC_DAT_OVERRUN_MASK (0x40000000U)
+#define ADC_DAT_OVERRUN_SHIFT (30U)
+/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
+ * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
+ * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
+ * the data related to this channel is read from either of the global SEQn_GDAT registers. This
+ * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
+ * the overrun interrupt is enabled. While it is allowed to include the same channels in both
+ * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
+ * data registers associated with any of the channels that are shared between the two sequences. Any
+ * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
+ */
+#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
+#define ADC_DAT_DATAVALID_MASK (0x80000000U)
+#define ADC_DAT_DATAVALID_SHIFT (31U)
+/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
+ * cleared whenever this register is read or when the data related to this channel is read from
+ * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
+ * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
+ * the data registers associated with any of the channels that are shared between the two
+ * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
+ */
+#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
+/*! @} */
+
+/* The count of ADC_DAT */
+#define ADC_DAT_COUNT (12U)
+
+/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+/*! @{ */
+#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
+#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
+/*! THRLOW - Low threshold value against which ADC results will be compared
+ */
+#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
+/*! @} */
+
+/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+/*! @{ */
+#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
+#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
+/*! THRLOW - Low threshold value against which ADC results will be compared
+ */
+#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
+/*! @} */
+
+/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+/*! @{ */
+#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
+#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
+/*! THRHIGH - High threshold value against which ADC results will be compared
+ */
+#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
+/*! @} */
+
+/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+/*! @{ */
+#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
+#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
+/*! THRHIGH - High threshold value against which ADC results will be compared
+ */
+#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
+/*! @} */
+
+/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
+/*! @{ */
+#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
+/*! CH0_THRSEL - Threshold select for channel 0.
+ * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
+ * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
+ */
+#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
+/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
+/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
+/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
+/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
+/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
+/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
+/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
+/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
+/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
+/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
+/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
+/*! @} */
+
+/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
+/*! @{ */
+#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
+#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
+/*! SEQA_INTEN - Sequence A interrupt enable.
+ * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
+ * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
+ * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
+ * conversions, depending on the MODE bit in the SEQA_CTRL register.
+ */
+#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
+#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
+#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
+/*! SEQB_INTEN - Sequence B interrupt enable.
+ * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
+ * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
+ * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
+ * conversions, depending on the MODE bit in the SEQB_CTRL register.
+ */
+#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
+#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
+#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
+/*! OVR_INTEN - Overrun interrupt enable.
+ * 0b0..Disabled. The overrun interrupt is disabled.
+ * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
+ * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
+ * sequence is 0, then an overrun in the global data register for that sequence will also cause this
+ * interrupt/DMA trigger to be asserted.
+ */
+#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
+#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
+#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
+/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
+ * 0b00..Disabled.
+ * 0b01..Outside threshold.
+ * 0b10..Crossing threshold.
+ * 0b11..Reserved
+ */
+#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
+#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
+#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
+/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
+#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
+#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
+/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
+#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
+#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
+/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
+#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
+#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
+/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
+#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
+#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
+/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
+#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
+#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
+/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
+#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
+#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
+/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
+#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
+#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
+/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
+#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
+#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
+/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
+#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
+#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
+/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
+#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
+#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
+/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
+/*! @} */
+
+/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
+/*! @{ */
+#define ADC_FLAGS_THCMP0_MASK (0x1U)
+#define ADC_FLAGS_THCMP0_SHIFT (0U)
+/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
+ * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
+ * writing a 1.
+ */
+#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
+#define ADC_FLAGS_THCMP1_MASK (0x2U)
+#define ADC_FLAGS_THCMP1_SHIFT (1U)
+/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
+#define ADC_FLAGS_THCMP2_MASK (0x4U)
+#define ADC_FLAGS_THCMP2_SHIFT (2U)
+/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
+#define ADC_FLAGS_THCMP3_MASK (0x8U)
+#define ADC_FLAGS_THCMP3_SHIFT (3U)
+/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
+#define ADC_FLAGS_THCMP4_MASK (0x10U)
+#define ADC_FLAGS_THCMP4_SHIFT (4U)
+/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
+#define ADC_FLAGS_THCMP5_MASK (0x20U)
+#define ADC_FLAGS_THCMP5_SHIFT (5U)
+/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
+#define ADC_FLAGS_THCMP6_MASK (0x40U)
+#define ADC_FLAGS_THCMP6_SHIFT (6U)
+/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
+#define ADC_FLAGS_THCMP7_MASK (0x80U)
+#define ADC_FLAGS_THCMP7_SHIFT (7U)
+/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
+#define ADC_FLAGS_THCMP8_MASK (0x100U)
+#define ADC_FLAGS_THCMP8_SHIFT (8U)
+/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
+#define ADC_FLAGS_THCMP9_MASK (0x200U)
+#define ADC_FLAGS_THCMP9_SHIFT (9U)
+/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
+#define ADC_FLAGS_THCMP10_MASK (0x400U)
+#define ADC_FLAGS_THCMP10_SHIFT (10U)
+/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
+#define ADC_FLAGS_THCMP11_MASK (0x800U)
+#define ADC_FLAGS_THCMP11_SHIFT (11U)
+/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
+#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
+#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
+/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
+ */
+#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
+#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
+#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
+/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
+ */
+#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
+#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
+#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
+/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
+ */
+#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
+#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
+#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
+/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
+ */
+#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
+#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
+#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
+/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
+ */
+#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
+#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
+#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
+/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
+ */
+#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
+#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
+#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
+/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
+ */
+#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
+#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
+#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
+/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
+ */
+#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
+#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
+#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
+/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
+ */
+#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
+#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
+#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
+/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
+ */
+#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
+#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
+#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
+/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
+ */
+#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
+#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
+#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
+/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
+ */
+#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
+#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
+#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
+/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
+ */
+#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
+#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
+#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
+/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
+ */
+#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
+#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
+#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
+/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
+ * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
+ * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
+ * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
+ * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
+ * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
+ * register.
+ */
+#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
+#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
+#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
+/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
+ * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
+ * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
+ * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
+ * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
+ * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
+ * register.
+ */
+#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
+#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
+#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
+/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
+ * the lower bits of this register are set to 1 (due to an enabled out-of-range or
+ * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
+ * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
+ * when all of the individual threshold flags are cleared via writing 1s to those bits.
+ */
+#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
+#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
+#define ADC_FLAGS_OVR_INT_SHIFT (31U)
+/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
+ * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
+ * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
+ * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
+ * of the individual overrun bits have been cleared via reading the corresponding data registers.
+ */
+#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
+/*! @} */
+
+/*! @name STARTUP - ADC Startup register. */
+/*! @{ */
+#define ADC_STARTUP_ADC_ENA_MASK (0x1U)
+#define ADC_STARTUP_ADC_ENA_SHIFT (0U)
+/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
+ * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
+ * after the ADC is powered up (typically by altering a system-level ADC power control bit).
+ */
+#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
+#define ADC_STARTUP_ADC_INIT_MASK (0x2U)
+#define ADC_STARTUP_ADC_INIT_SHIFT (1U)
+/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
+ * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
+ * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
+ * required if a calibration is not performed. It will also reload the stored calibration value from
+ * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
+ * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
+ * an ADC dummy conversion cycle is required. It should not be set during the same write that
+ * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
+ * when the 'dummy' conversion cycle completes.
+ */
+#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
+/*! @} */
+
+/*! @name CALIB - ADC Calibration register. */
+/*! @{ */
+#define ADC_CALIB_CALIB_MASK (0x1U)
+#define ADC_CALIB_CALIB_SHIFT (0U)
+/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
+ * only be set to a '1' by software. It is cleared automatically when the calibration cycle
+ * completes.
+ */
+#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
+#define ADC_CALIB_CALREQD_MASK (0x2U)
+#define ADC_CALIB_CALREQD_SHIFT (1U)
+/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
+ * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
+ * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
+ * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
+ * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
+ * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
+ * required for calibration.
+ */
+#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
+#define ADC_CALIB_CALVALUE_MASK (0x1FCU)
+#define ADC_CALIB_CALVALUE_SHIFT (2U)
+/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
+ * during last calibration cycle. This value is not typically of any use to the user.
+ */
+#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x400A0000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
+#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ASYNC_SYSCON Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** ASYNC_SYSCON - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
+ __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
+ __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
+ __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
+ __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
+} ASYNC_SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ASYNC_SYSCON Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
+ * @{
+ */
+
+/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
+/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
+/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
+/*! @} */
+
+/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
+/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
+ * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
+/*! @} */
+
+/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
+/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
+ * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
+/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
+/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
+/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
+ * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
+/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
+ * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
+/*! SEL - Clock source for asynchronous clock source selector A
+ * 0b00..Main clock (main_clk)
+ * 0b01..FRO 12 MHz (fro_12m)
+ * 0b10..Audio PLL clock.(AUDPLL_BYPASS)
+ * 0b11..fc6 fclk (fc6_fclk)
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Register_Masks */
+
+
+/* ASYNC_SYSCON - Peripheral instance base addresses */
+/** Peripheral ASYNC_SYSCON base address */
+#define ASYNC_SYSCON_BASE (0x40040000u)
+/** Peripheral ASYNC_SYSCON base pointer */
+#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
+/** Array initializer of ASYNC_SYSCON peripheral base addresses */
+#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
+/** Array initializer of ASYNC_SYSCON peripheral base pointers */
+#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAN Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[12];
+ __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
+ __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
+ __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
+ __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
+ __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
+ __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
+ __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
+ uint8_t RESERVED_2[16];
+ __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
+ __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
+ __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
+ __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
+ __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
+ __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
+ uint8_t RESERVED_4[32];
+ __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
+ __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
+ __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
+ __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
+ __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
+ __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
+ __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
+ __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
+ __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
+ __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
+ __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
+ __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
+ __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
+ __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
+ __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
+ __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
+ __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
+ __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
+ __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
+ __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
+ __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
+ __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
+ __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
+ __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
+ uint8_t RESERVED_6[8];
+ __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
+ __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
+ __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
+ uint8_t RESERVED_7[260];
+ __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
+ uint8_t RESERVED_8[508];
+ __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
+ uint8_t RESERVED_9[508];
+ __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CAN Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name DBTP - Data Bit Timing Prescaler Register */
+/*! @{ */
+#define CAN_DBTP_DSJW_MASK (0xFU)
+#define CAN_DBTP_DSJW_SHIFT (0U)
+/*! DSJW - Data (re)synchronization jump width.
+ */
+#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
+#define CAN_DBTP_DTSEG2_MASK (0xF0U)
+#define CAN_DBTP_DTSEG2_SHIFT (4U)
+/*! DTSEG2 - Data time segment after sample point.
+ */
+#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
+#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
+#define CAN_DBTP_DTSEG1_SHIFT (8U)
+/*! DTSEG1 - Data time segment before sample point.
+ */
+#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
+#define CAN_DBTP_DBRP_MASK (0x1F0000U)
+#define CAN_DBTP_DBRP_SHIFT (16U)
+/*! DBRP - Data bit rate prescaler.
+ */
+#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
+#define CAN_DBTP_TDC_MASK (0x800000U)
+#define CAN_DBTP_TDC_SHIFT (23U)
+/*! TDC - Transmitter delay compensation.
+ */
+#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
+/*! @} */
+
+/*! @name TEST - Test Register */
+/*! @{ */
+#define CAN_TEST_LBCK_MASK (0x10U)
+#define CAN_TEST_LBCK_SHIFT (4U)
+/*! LBCK - Loop back mode.
+ */
+#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
+#define CAN_TEST_TX_MASK (0x60U)
+#define CAN_TEST_TX_SHIFT (5U)
+/*! TX - Control of transmit pin.
+ */
+#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
+#define CAN_TEST_RX_MASK (0x80U)
+#define CAN_TEST_RX_SHIFT (7U)
+/*! RX - Monitors the actual value of the CAN_RXD.
+ */
+#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
+/*! @} */
+
+/*! @name CCCR - CC Control Register */
+/*! @{ */
+#define CAN_CCCR_INIT_MASK (0x1U)
+#define CAN_CCCR_INIT_SHIFT (0U)
+/*! INIT - Initialization.
+ */
+#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
+#define CAN_CCCR_CCE_MASK (0x2U)
+#define CAN_CCCR_CCE_SHIFT (1U)
+/*! CCE - Configuration change enable.
+ */
+#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
+#define CAN_CCCR_ASM_MASK (0x4U)
+#define CAN_CCCR_ASM_SHIFT (2U)
+/*! ASM - Restricted operational mode.
+ */
+#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
+#define CAN_CCCR_CSA_MASK (0x8U)
+#define CAN_CCCR_CSA_SHIFT (3U)
+/*! CSA - Clock Stop Acknowledge.
+ */
+#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
+#define CAN_CCCR_CSR_MASK (0x10U)
+#define CAN_CCCR_CSR_SHIFT (4U)
+/*! CSR - Clock Stop Request.
+ */
+#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
+#define CAN_CCCR_MON_MASK (0x20U)
+#define CAN_CCCR_MON_SHIFT (5U)
+/*! MON - Bus monitoring mode.
+ */
+#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
+#define CAN_CCCR_DAR_MASK (0x40U)
+#define CAN_CCCR_DAR_SHIFT (6U)
+/*! DAR - Disable automatic retransmission.
+ */
+#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
+#define CAN_CCCR_TEST_MASK (0x80U)
+#define CAN_CCCR_TEST_SHIFT (7U)
+/*! TEST - Test mode enable.
+ */
+#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
+#define CAN_CCCR_FDOE_MASK (0x100U)
+#define CAN_CCCR_FDOE_SHIFT (8U)
+/*! FDOE - CAN FD operation enable.
+ */
+#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
+#define CAN_CCCR_BRSE_MASK (0x200U)
+#define CAN_CCCR_BRSE_SHIFT (9U)
+/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.
+ */
+#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
+#define CAN_CCCR_PXHD_MASK (0x1000U)
+#define CAN_CCCR_PXHD_SHIFT (12U)
+/*! PXHD - Protocol exception handling disable.
+ */
+#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
+#define CAN_CCCR_EFBI_MASK (0x2000U)
+#define CAN_CCCR_EFBI_SHIFT (13U)
+/*! EFBI - Edge filtering during bus integration.
+ */
+#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
+#define CAN_CCCR_TXP_MASK (0x4000U)
+#define CAN_CCCR_TXP_SHIFT (14U)
+/*! TXP - Transmit pause.
+ */
+#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
+#define CAN_CCCR_NISO_MASK (0x8000U)
+#define CAN_CCCR_NISO_SHIFT (15U)
+/*! NISO - Non ISO operation.
+ */
+#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
+/*! @} */
+
+/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
+/*! @{ */
+#define CAN_NBTP_NTSEG2_MASK (0x7FU)
+#define CAN_NBTP_NTSEG2_SHIFT (0U)
+/*! NTSEG2 - Nominal time segment after sample point.
+ */
+#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
+#define CAN_NBTP_NTSEG1_MASK (0xFF00U)
+#define CAN_NBTP_NTSEG1_SHIFT (8U)
+/*! NTSEG1 - Nominal time segment before sample point.
+ */
+#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
+#define CAN_NBTP_NBRP_MASK (0x1FF0000U)
+#define CAN_NBTP_NBRP_SHIFT (16U)
+/*! NBRP - Nominal bit rate prescaler.
+ */
+#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
+#define CAN_NBTP_NSJW_MASK (0xFE000000U)
+#define CAN_NBTP_NSJW_SHIFT (25U)
+/*! NSJW - Nominal (re)synchronization jump width.
+ */
+#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
+/*! @} */
+
+/*! @name TSCC - Timestamp Counter Configuration */
+/*! @{ */
+#define CAN_TSCC_TSS_MASK (0x3U)
+#define CAN_TSCC_TSS_SHIFT (0U)
+/*! TSS - Timestamp select.
+ */
+#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
+#define CAN_TSCC_TCP_MASK (0xF0000U)
+#define CAN_TSCC_TCP_SHIFT (16U)
+/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
+ */
+#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
+/*! @} */
+
+/*! @name TSCV - Timestamp Counter Value */
+/*! @{ */
+#define CAN_TSCV_TSC_MASK (0xFFFFU)
+#define CAN_TSCV_TSC_SHIFT (0U)
+/*! TSC - Timestamp counter.
+ */
+#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
+/*! @} */
+
+/*! @name TOCC - Timeout Counter Configuration */
+/*! @{ */
+#define CAN_TOCC_ETOC_MASK (0x1U)
+#define CAN_TOCC_ETOC_SHIFT (0U)
+/*! ETOC - Enable timeout counter.
+ */
+#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
+#define CAN_TOCC_TOS_MASK (0x6U)
+#define CAN_TOCC_TOS_SHIFT (1U)
+/*! TOS - Timeout select.
+ */
+#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
+#define CAN_TOCC_TOP_MASK (0xFFFF0000U)
+#define CAN_TOCC_TOP_SHIFT (16U)
+/*! TOP - Timeout period.
+ */
+#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
+/*! @} */
+
+/*! @name TOCV - Timeout Counter Value */
+/*! @{ */
+#define CAN_TOCV_TOC_MASK (0xFFFFU)
+#define CAN_TOCV_TOC_SHIFT (0U)
+/*! TOC - Timeout counter.
+ */
+#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
+/*! @} */
+
+/*! @name ECR - Error Counter Register */
+/*! @{ */
+#define CAN_ECR_TEC_MASK (0xFFU)
+#define CAN_ECR_TEC_SHIFT (0U)
+/*! TEC - Transmit error counter.
+ */
+#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
+#define CAN_ECR_REC_MASK (0x7F00U)
+#define CAN_ECR_REC_SHIFT (8U)
+/*! REC - Receive error counter.
+ */
+#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
+#define CAN_ECR_RP_MASK (0x8000U)
+#define CAN_ECR_RP_SHIFT (15U)
+/*! RP - Receive error passive.
+ */
+#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
+#define CAN_ECR_CEL_MASK (0xFF0000U)
+#define CAN_ECR_CEL_SHIFT (16U)
+/*! CEL - CAN error logging.
+ */
+#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
+/*! @} */
+
+/*! @name PSR - Protocol Status Register */
+/*! @{ */
+#define CAN_PSR_LEC_MASK (0x7U)
+#define CAN_PSR_LEC_SHIFT (0U)
+/*! LEC - Last error code.
+ */
+#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
+#define CAN_PSR_ACT_MASK (0x18U)
+#define CAN_PSR_ACT_SHIFT (3U)
+/*! ACT - Activity.
+ */
+#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
+#define CAN_PSR_EP_MASK (0x20U)
+#define CAN_PSR_EP_SHIFT (5U)
+/*! EP - Error Passive.
+ */
+#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
+#define CAN_PSR_EW_MASK (0x40U)
+#define CAN_PSR_EW_SHIFT (6U)
+/*! EW - Warning status.
+ */
+#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
+#define CAN_PSR_BO_MASK (0x80U)
+#define CAN_PSR_BO_SHIFT (7U)
+/*! BO - Bus Off Status.
+ */
+#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
+#define CAN_PSR_DLEC_MASK (0x700U)
+#define CAN_PSR_DLEC_SHIFT (8U)
+/*! DLEC - Data phase last error code.
+ */
+#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
+#define CAN_PSR_RESI_MASK (0x800U)
+#define CAN_PSR_RESI_SHIFT (11U)
+/*! RESI - ESI flag of the last received CAN FD message.
+ */
+#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
+#define CAN_PSR_RBRS_MASK (0x1000U)
+#define CAN_PSR_RBRS_SHIFT (12U)
+/*! RBRS - BRS flag of last received CAN FD message.
+ */
+#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
+#define CAN_PSR_RFDF_MASK (0x2000U)
+#define CAN_PSR_RFDF_SHIFT (13U)
+/*! RFDF - Received a CAN FD message.
+ */
+#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
+#define CAN_PSR_PXE_MASK (0x4000U)
+#define CAN_PSR_PXE_SHIFT (14U)
+/*! PXE - Protocol exception event.
+ */
+#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
+#define CAN_PSR_TDCV_MASK (0x7F0000U)
+#define CAN_PSR_TDCV_SHIFT (16U)
+/*! TDCV - Transmitter delay compensation value.
+ */
+#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
+/*! @} */
+
+/*! @name TDCR - Transmitter Delay Compensator Register */
+/*! @{ */
+#define CAN_TDCR_TDCF_MASK (0x7FU)
+#define CAN_TDCR_TDCF_SHIFT (0U)
+/*! TDCF - Transmitter delay compensation filter window length.
+ */
+#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
+#define CAN_TDCR_TDCO_MASK (0x7F00U)
+#define CAN_TDCR_TDCO_SHIFT (8U)
+/*! TDCO - Transmitter delay compensation offset.
+ */
+#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
+/*! @} */
+
+/*! @name IR - Interrupt Register */
+/*! @{ */
+#define CAN_IR_RF0N_MASK (0x1U)
+#define CAN_IR_RF0N_SHIFT (0U)
+/*! RF0N - Rx FIFO 0 new message.
+ */
+#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
+#define CAN_IR_RF0W_MASK (0x2U)
+#define CAN_IR_RF0W_SHIFT (1U)
+/*! RF0W - Rx FIFO 0 watermark reached.
+ */
+#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
+#define CAN_IR_RF0F_MASK (0x4U)
+#define CAN_IR_RF0F_SHIFT (2U)
+/*! RF0F - Rx FIFO 0 full.
+ */
+#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
+#define CAN_IR_RF0L_MASK (0x8U)
+#define CAN_IR_RF0L_SHIFT (3U)
+/*! RF0L - Rx FIFO 0 message lost.
+ */
+#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
+#define CAN_IR_RF1N_MASK (0x10U)
+#define CAN_IR_RF1N_SHIFT (4U)
+/*! RF1N - Rx FIFO 1 new message.
+ */
+#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
+#define CAN_IR_RF1W_MASK (0x20U)
+#define CAN_IR_RF1W_SHIFT (5U)
+/*! RF1W - Rx FIFO 1 watermark reached.
+ */
+#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
+#define CAN_IR_RF1F_MASK (0x40U)
+#define CAN_IR_RF1F_SHIFT (6U)
+/*! RF1F - Rx FIFO 1 full.
+ */
+#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
+#define CAN_IR_RF1L_MASK (0x80U)
+#define CAN_IR_RF1L_SHIFT (7U)
+/*! RF1L - Rx FIFO 1 message lost.
+ */
+#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
+#define CAN_IR_HPM_MASK (0x100U)
+#define CAN_IR_HPM_SHIFT (8U)
+/*! HPM - High priority message.
+ */
+#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
+#define CAN_IR_TC_MASK (0x200U)
+#define CAN_IR_TC_SHIFT (9U)
+/*! TC - Transmission completed.
+ */
+#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
+#define CAN_IR_TCF_MASK (0x400U)
+#define CAN_IR_TCF_SHIFT (10U)
+/*! TCF - Transmission cancellation finished.
+ */
+#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
+#define CAN_IR_TFE_MASK (0x800U)
+#define CAN_IR_TFE_SHIFT (11U)
+/*! TFE - Tx FIFO empty.
+ */
+#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
+#define CAN_IR_TEFN_MASK (0x1000U)
+#define CAN_IR_TEFN_SHIFT (12U)
+/*! TEFN - Tx event FIFO new entry.
+ */
+#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
+#define CAN_IR_TEFW_MASK (0x2000U)
+#define CAN_IR_TEFW_SHIFT (13U)
+/*! TEFW - Tx event FIFO watermark reached.
+ */
+#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
+#define CAN_IR_TEFF_MASK (0x4000U)
+#define CAN_IR_TEFF_SHIFT (14U)
+/*! TEFF - Tx event FIFO full.
+ */
+#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
+#define CAN_IR_TEFL_MASK (0x8000U)
+#define CAN_IR_TEFL_SHIFT (15U)
+/*! TEFL - Tx event FIFO element lost.
+ */
+#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
+#define CAN_IR_TSW_MASK (0x10000U)
+#define CAN_IR_TSW_SHIFT (16U)
+/*! TSW - Timestamp wraparound.
+ */
+#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
+#define CAN_IR_MRAF_MASK (0x20000U)
+#define CAN_IR_MRAF_SHIFT (17U)
+/*! MRAF - Message RAM access failure.
+ */
+#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
+#define CAN_IR_TOO_MASK (0x40000U)
+#define CAN_IR_TOO_SHIFT (18U)
+/*! TOO - Timeout occurred.
+ */
+#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
+#define CAN_IR_DRX_MASK (0x80000U)
+#define CAN_IR_DRX_SHIFT (19U)
+/*! DRX - Message stored in dedicated Rx buffer.
+ */
+#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
+#define CAN_IR_BEC_MASK (0x100000U)
+#define CAN_IR_BEC_SHIFT (20U)
+/*! BEC - Bit error corrected.
+ */
+#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
+#define CAN_IR_BEU_MASK (0x200000U)
+#define CAN_IR_BEU_SHIFT (21U)
+/*! BEU - Bit error uncorrected.
+ */
+#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
+#define CAN_IR_ELO_MASK (0x400000U)
+#define CAN_IR_ELO_SHIFT (22U)
+/*! ELO - Error logging overflow.
+ */
+#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
+#define CAN_IR_EP_MASK (0x800000U)
+#define CAN_IR_EP_SHIFT (23U)
+/*! EP - Error passive.
+ */
+#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
+#define CAN_IR_EW_MASK (0x1000000U)
+#define CAN_IR_EW_SHIFT (24U)
+/*! EW - Warning status.
+ */
+#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
+#define CAN_IR_BO_MASK (0x2000000U)
+#define CAN_IR_BO_SHIFT (25U)
+/*! BO - Bus_Off Status.
+ */
+#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
+#define CAN_IR_WDI_MASK (0x4000000U)
+#define CAN_IR_WDI_SHIFT (26U)
+/*! WDI - Watchdog interrupt.
+ */
+#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
+#define CAN_IR_PEA_MASK (0x8000000U)
+#define CAN_IR_PEA_SHIFT (27U)
+/*! PEA - Protocol error in arbitration phase.
+ */
+#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
+#define CAN_IR_PED_MASK (0x10000000U)
+#define CAN_IR_PED_SHIFT (28U)
+/*! PED - Protocol error in data phase.
+ */
+#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
+#define CAN_IR_ARA_MASK (0x20000000U)
+#define CAN_IR_ARA_SHIFT (29U)
+/*! ARA - Access to reserved address.
+ */
+#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
+/*! @} */
+
+/*! @name IE - Interrupt Enable */
+/*! @{ */
+#define CAN_IE_RF0NE_MASK (0x1U)
+#define CAN_IE_RF0NE_SHIFT (0U)
+/*! RF0NE - Rx FIFO 0 new message interrupt enable.
+ */
+#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
+#define CAN_IE_RF0WE_MASK (0x2U)
+#define CAN_IE_RF0WE_SHIFT (1U)
+/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.
+ */
+#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
+#define CAN_IE_RF0FE_MASK (0x4U)
+#define CAN_IE_RF0FE_SHIFT (2U)
+/*! RF0FE - Rx FIFO 0 full interrupt enable.
+ */
+#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
+#define CAN_IE_RF0LE_MASK (0x8U)
+#define CAN_IE_RF0LE_SHIFT (3U)
+/*! RF0LE - Rx FIFO 0 message lost interrupt enable.
+ */
+#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
+#define CAN_IE_RF1NE_MASK (0x10U)
+#define CAN_IE_RF1NE_SHIFT (4U)
+/*! RF1NE - Rx FIFO 1 new message interrupt enable.
+ */
+#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
+#define CAN_IE_RF1WE_MASK (0x20U)
+#define CAN_IE_RF1WE_SHIFT (5U)
+/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.
+ */
+#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
+#define CAN_IE_RF1FE_MASK (0x40U)
+#define CAN_IE_RF1FE_SHIFT (6U)
+/*! RF1FE - Rx FIFO 1 full interrupt enable.
+ */
+#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
+#define CAN_IE_RF1LE_MASK (0x80U)
+#define CAN_IE_RF1LE_SHIFT (7U)
+/*! RF1LE - Rx FIFO 1 message lost interrupt enable.
+ */
+#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
+#define CAN_IE_HPME_MASK (0x100U)
+#define CAN_IE_HPME_SHIFT (8U)
+/*! HPME - High priority message interrupt enable.
+ */
+#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
+#define CAN_IE_TCE_MASK (0x200U)
+#define CAN_IE_TCE_SHIFT (9U)
+/*! TCE - Transmission completed interrupt enable.
+ */
+#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
+#define CAN_IE_TCFE_MASK (0x400U)
+#define CAN_IE_TCFE_SHIFT (10U)
+/*! TCFE - Transmission cancellation finished interrupt enable.
+ */
+#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
+#define CAN_IE_TFEE_MASK (0x800U)
+#define CAN_IE_TFEE_SHIFT (11U)
+/*! TFEE - Tx FIFO empty interrupt enable.
+ */
+#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
+#define CAN_IE_TEFNE_MASK (0x1000U)
+#define CAN_IE_TEFNE_SHIFT (12U)
+/*! TEFNE - Tx event FIFO new entry interrupt enable.
+ */
+#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
+#define CAN_IE_TEFWE_MASK (0x2000U)
+#define CAN_IE_TEFWE_SHIFT (13U)
+/*! TEFWE - Tx event FIFO watermark reached interrupt enable.
+ */
+#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
+#define CAN_IE_TEFFE_MASK (0x4000U)
+#define CAN_IE_TEFFE_SHIFT (14U)
+/*! TEFFE - Tx event FIFO full interrupt enable.
+ */
+#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
+#define CAN_IE_TEFLE_MASK (0x8000U)
+#define CAN_IE_TEFLE_SHIFT (15U)
+/*! TEFLE - Tx event FIFO element lost interrupt enable.
+ */
+#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
+#define CAN_IE_TSWE_MASK (0x10000U)
+#define CAN_IE_TSWE_SHIFT (16U)
+/*! TSWE - Timestamp wraparound interrupt enable.
+ */
+#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
+#define CAN_IE_MRAFE_MASK (0x20000U)
+#define CAN_IE_MRAFE_SHIFT (17U)
+/*! MRAFE - Message RAM access failure interrupt enable.
+ */
+#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
+#define CAN_IE_TOOE_MASK (0x40000U)
+#define CAN_IE_TOOE_SHIFT (18U)
+/*! TOOE - Timeout occurred interrupt enable.
+ */
+#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
+#define CAN_IE_DRXE_MASK (0x80000U)
+#define CAN_IE_DRXE_SHIFT (19U)
+/*! DRXE - Message stored in dedicated Rx buffer interrupt enable.
+ */
+#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
+#define CAN_IE_BECE_MASK (0x100000U)
+#define CAN_IE_BECE_SHIFT (20U)
+/*! BECE - Bit error corrected interrupt enable.
+ */
+#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
+#define CAN_IE_BEUE_MASK (0x200000U)
+#define CAN_IE_BEUE_SHIFT (21U)
+/*! BEUE - Bit error uncorrected interrupt enable.
+ */
+#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
+#define CAN_IE_ELOE_MASK (0x400000U)
+#define CAN_IE_ELOE_SHIFT (22U)
+/*! ELOE - Error logging overflow interrupt enable.
+ */
+#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
+#define CAN_IE_EPE_MASK (0x800000U)
+#define CAN_IE_EPE_SHIFT (23U)
+/*! EPE - Error passive interrupt enable.
+ */
+#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
+#define CAN_IE_EWE_MASK (0x1000000U)
+#define CAN_IE_EWE_SHIFT (24U)
+/*! EWE - Warning status interrupt enable.
+ */
+#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
+#define CAN_IE_BOE_MASK (0x2000000U)
+#define CAN_IE_BOE_SHIFT (25U)
+/*! BOE - Bus_Off Status interrupt enable.
+ */
+#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
+#define CAN_IE_WDIE_MASK (0x4000000U)
+#define CAN_IE_WDIE_SHIFT (26U)
+/*! WDIE - Watchdog interrupt enable.
+ */
+#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
+#define CAN_IE_PEAE_MASK (0x8000000U)
+#define CAN_IE_PEAE_SHIFT (27U)
+/*! PEAE - Protocol error in arbitration phase interrupt enable.
+ */
+#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
+#define CAN_IE_PEDE_MASK (0x10000000U)
+#define CAN_IE_PEDE_SHIFT (28U)
+/*! PEDE - Protocol error in data phase interrupt enable.
+ */
+#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
+#define CAN_IE_ARAE_MASK (0x20000000U)
+#define CAN_IE_ARAE_SHIFT (29U)
+/*! ARAE - Access to reserved address interrupt enable.
+ */
+#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
+/*! @} */
+
+/*! @name ILS - Interrupt Line Select */
+/*! @{ */
+#define CAN_ILS_RF0NL_MASK (0x1U)
+#define CAN_ILS_RF0NL_SHIFT (0U)
+/*! RF0NL - Rx FIFO 0 new message interrupt line.
+ */
+#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
+#define CAN_ILS_RF0WL_MASK (0x2U)
+#define CAN_ILS_RF0WL_SHIFT (1U)
+/*! RF0WL - Rx FIFO 0 watermark reached interrupt line.
+ */
+#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
+#define CAN_ILS_RF0FL_MASK (0x4U)
+#define CAN_ILS_RF0FL_SHIFT (2U)
+/*! RF0FL - Rx FIFO 0 full interrupt line.
+ */
+#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
+#define CAN_ILS_RF0LL_MASK (0x8U)
+#define CAN_ILS_RF0LL_SHIFT (3U)
+/*! RF0LL - Rx FIFO 0 message lost interrupt line.
+ */
+#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
+#define CAN_ILS_RF1NL_MASK (0x10U)
+#define CAN_ILS_RF1NL_SHIFT (4U)
+/*! RF1NL - Rx FIFO 1 new message interrupt line.
+ */
+#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
+#define CAN_ILS_RF1WL_MASK (0x20U)
+#define CAN_ILS_RF1WL_SHIFT (5U)
+/*! RF1WL - Rx FIFO 1 watermark reached interrupt line.
+ */
+#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
+#define CAN_ILS_RF1FL_MASK (0x40U)
+#define CAN_ILS_RF1FL_SHIFT (6U)
+/*! RF1FL - Rx FIFO 1 full interrupt line.
+ */
+#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
+#define CAN_ILS_RF1LL_MASK (0x80U)
+#define CAN_ILS_RF1LL_SHIFT (7U)
+/*! RF1LL - Rx FIFO 1 message lost interrupt line.
+ */
+#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
+#define CAN_ILS_HPML_MASK (0x100U)
+#define CAN_ILS_HPML_SHIFT (8U)
+/*! HPML - High priority message interrupt line.
+ */
+#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
+#define CAN_ILS_TCL_MASK (0x200U)
+#define CAN_ILS_TCL_SHIFT (9U)
+/*! TCL - Transmission completed interrupt line.
+ */
+#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
+#define CAN_ILS_TCFL_MASK (0x400U)
+#define CAN_ILS_TCFL_SHIFT (10U)
+/*! TCFL - Transmission cancellation finished interrupt line.
+ */
+#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
+#define CAN_ILS_TFEL_MASK (0x800U)
+#define CAN_ILS_TFEL_SHIFT (11U)
+/*! TFEL - Tx FIFO empty interrupt line.
+ */
+#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
+#define CAN_ILS_TEFNL_MASK (0x1000U)
+#define CAN_ILS_TEFNL_SHIFT (12U)
+/*! TEFNL - Tx event FIFO new entry interrupt line.
+ */
+#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
+#define CAN_ILS_TEFWL_MASK (0x2000U)
+#define CAN_ILS_TEFWL_SHIFT (13U)
+/*! TEFWL - Tx event FIFO watermark reached interrupt line.
+ */
+#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
+#define CAN_ILS_TEFFL_MASK (0x4000U)
+#define CAN_ILS_TEFFL_SHIFT (14U)
+/*! TEFFL - Tx event FIFO full interrupt line.
+ */
+#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
+#define CAN_ILS_TEFLL_MASK (0x8000U)
+#define CAN_ILS_TEFLL_SHIFT (15U)
+/*! TEFLL - Tx event FIFO element lost interrupt line.
+ */
+#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
+#define CAN_ILS_TSWL_MASK (0x10000U)
+#define CAN_ILS_TSWL_SHIFT (16U)
+/*! TSWL - Timestamp wraparound interrupt line.
+ */
+#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
+#define CAN_ILS_MRAFL_MASK (0x20000U)
+#define CAN_ILS_MRAFL_SHIFT (17U)
+/*! MRAFL - Message RAM access failure interrupt line.
+ */
+#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
+#define CAN_ILS_TOOL_MASK (0x40000U)
+#define CAN_ILS_TOOL_SHIFT (18U)
+/*! TOOL - Timeout occurred interrupt line.
+ */
+#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
+#define CAN_ILS_DRXL_MASK (0x80000U)
+#define CAN_ILS_DRXL_SHIFT (19U)
+/*! DRXL - Message stored in dedicated Rx buffer interrupt line.
+ */
+#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
+#define CAN_ILS_BECL_MASK (0x100000U)
+#define CAN_ILS_BECL_SHIFT (20U)
+/*! BECL - Bit error corrected interrupt line.
+ */
+#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
+#define CAN_ILS_BEUL_MASK (0x200000U)
+#define CAN_ILS_BEUL_SHIFT (21U)
+/*! BEUL - Bit error uncorrected interrupt line.
+ */
+#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
+#define CAN_ILS_ELOL_MASK (0x400000U)
+#define CAN_ILS_ELOL_SHIFT (22U)
+/*! ELOL - Error logging overflow interrupt line.
+ */
+#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
+#define CAN_ILS_EPL_MASK (0x800000U)
+#define CAN_ILS_EPL_SHIFT (23U)
+/*! EPL - Error passive interrupt line.
+ */
+#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
+#define CAN_ILS_EWL_MASK (0x1000000U)
+#define CAN_ILS_EWL_SHIFT (24U)
+/*! EWL - Warning status interrupt line.
+ */
+#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
+#define CAN_ILS_BOL_MASK (0x2000000U)
+#define CAN_ILS_BOL_SHIFT (25U)
+/*! BOL - Bus_Off Status interrupt line.
+ */
+#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
+#define CAN_ILS_WDIL_MASK (0x4000000U)
+#define CAN_ILS_WDIL_SHIFT (26U)
+/*! WDIL - Watchdog interrupt line.
+ */
+#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
+#define CAN_ILS_PEAL_MASK (0x8000000U)
+#define CAN_ILS_PEAL_SHIFT (27U)
+/*! PEAL - Protocol error in arbitration phase interrupt line.
+ */
+#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
+#define CAN_ILS_PEDL_MASK (0x10000000U)
+#define CAN_ILS_PEDL_SHIFT (28U)
+/*! PEDL - Protocol error in data phase interrupt line.
+ */
+#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
+#define CAN_ILS_ARAL_MASK (0x20000000U)
+#define CAN_ILS_ARAL_SHIFT (29U)
+/*! ARAL - Access to reserved address interrupt line.
+ */
+#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
+/*! @} */
+
+/*! @name ILE - Interrupt Line Enable */
+/*! @{ */
+#define CAN_ILE_EINT0_MASK (0x1U)
+#define CAN_ILE_EINT0_SHIFT (0U)
+/*! EINT0 - Enable interrupt line 0.
+ */
+#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
+#define CAN_ILE_EINT1_MASK (0x2U)
+#define CAN_ILE_EINT1_SHIFT (1U)
+/*! EINT1 - Enable interrupt line 1.
+ */
+#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
+/*! @} */
+
+/*! @name GFC - Global Filter Configuration */
+/*! @{ */
+#define CAN_GFC_RRFE_MASK (0x1U)
+#define CAN_GFC_RRFE_SHIFT (0U)
+/*! RRFE - Reject remote frames extended.
+ */
+#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
+#define CAN_GFC_RRFS_MASK (0x2U)
+#define CAN_GFC_RRFS_SHIFT (1U)
+/*! RRFS - Reject remote frames standard.
+ */
+#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
+#define CAN_GFC_ANFE_MASK (0xCU)
+#define CAN_GFC_ANFE_SHIFT (2U)
+/*! ANFE - Accept non-matching frames extended.
+ */
+#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
+#define CAN_GFC_ANFS_MASK (0x30U)
+#define CAN_GFC_ANFS_SHIFT (4U)
+/*! ANFS - Accept non-matching frames standard.
+ */
+#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
+/*! @} */
+
+/*! @name SIDFC - Standard ID Filter Configuration */
+/*! @{ */
+#define CAN_SIDFC_FLSSA_MASK (0xFFFCU)
+#define CAN_SIDFC_FLSSA_SHIFT (2U)
+/*! FLSSA - Filter list standard start address.
+ */
+#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
+#define CAN_SIDFC_LSS_MASK (0xFF0000U)
+#define CAN_SIDFC_LSS_SHIFT (16U)
+/*! LSS - List size standard 0 = No standard message ID filter.
+ */
+#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
+/*! @} */
+
+/*! @name XIDFC - Extended ID Filter Configuration */
+/*! @{ */
+#define CAN_XIDFC_FLESA_MASK (0xFFFCU)
+#define CAN_XIDFC_FLESA_SHIFT (2U)
+/*! FLESA - Filter list extended start address.
+ */
+#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
+#define CAN_XIDFC_LSE_MASK (0xFF0000U)
+#define CAN_XIDFC_LSE_SHIFT (16U)
+/*! LSE - List size extended 0 = No extended message ID filter.
+ */
+#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
+/*! @} */
+
+/*! @name XIDAM - Extended ID AND Mask */
+/*! @{ */
+#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)
+#define CAN_XIDAM_EIDM_SHIFT (0U)
+/*! EIDM - Extended ID mask.
+ */
+#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
+/*! @} */
+
+/*! @name HPMS - High Priority Message Status */
+/*! @{ */
+#define CAN_HPMS_BIDX_MASK (0x3FU)
+#define CAN_HPMS_BIDX_SHIFT (0U)
+/*! BIDX - Buffer index.
+ */
+#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
+#define CAN_HPMS_MSI_MASK (0xC0U)
+#define CAN_HPMS_MSI_SHIFT (6U)
+/*! MSI - Message storage indicator.
+ */
+#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
+#define CAN_HPMS_FIDX_MASK (0x7F00U)
+#define CAN_HPMS_FIDX_SHIFT (8U)
+/*! FIDX - Filter index.
+ */
+#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
+#define CAN_HPMS_FLST_MASK (0x8000U)
+#define CAN_HPMS_FLST_SHIFT (15U)
+/*! FLST - Filter list.
+ */
+#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
+/*! @} */
+
+/*! @name NDAT1 - New Data 1 */
+/*! @{ */
+#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)
+#define CAN_NDAT1_ND_SHIFT (0U)
+/*! ND - New Data.
+ */
+#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
+/*! @} */
+
+/*! @name NDAT2 - New Data 2 */
+/*! @{ */
+#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)
+#define CAN_NDAT2_ND_SHIFT (0U)
+/*! ND - New Data.
+ */
+#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
+/*! @} */
+
+/*! @name RXF0C - Rx FIFO 0 Configuration */
+/*! @{ */
+#define CAN_RXF0C_F0SA_MASK (0xFFFCU)
+#define CAN_RXF0C_F0SA_SHIFT (2U)
+/*! F0SA - Rx FIFO 0 start address.
+ */
+#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
+#define CAN_RXF0C_F0S_MASK (0x7F0000U)
+#define CAN_RXF0C_F0S_SHIFT (16U)
+/*! F0S - Rx FIFO 0 size.
+ */
+#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
+#define CAN_RXF0C_F0WM_MASK (0x7F000000U)
+#define CAN_RXF0C_F0WM_SHIFT (24U)
+/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
+ */
+#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
+#define CAN_RXF0C_F0OM_MASK (0x80000000U)
+#define CAN_RXF0C_F0OM_SHIFT (31U)
+/*! F0OM - FIFO 0 operation mode.
+ */
+#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
+/*! @} */
+
+/*! @name RXF0S - Rx FIFO 0 Status */
+/*! @{ */
+#define CAN_RXF0S_F0FL_MASK (0x7FU)
+#define CAN_RXF0S_F0FL_SHIFT (0U)
+/*! F0FL - Rx FIFO 0 fill level.
+ */
+#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
+#define CAN_RXF0S_F0GI_MASK (0x3F00U)
+#define CAN_RXF0S_F0GI_SHIFT (8U)
+/*! F0GI - Rx FIFO 0 get index.
+ */
+#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
+#define CAN_RXF0S_F0PI_MASK (0x3F0000U)
+#define CAN_RXF0S_F0PI_SHIFT (16U)
+/*! F0PI - Rx FIFO 0 put index.
+ */
+#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
+#define CAN_RXF0S_F0F_MASK (0x1000000U)
+#define CAN_RXF0S_F0F_SHIFT (24U)
+/*! F0F - Rx FIFO 0 full.
+ */
+#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
+#define CAN_RXF0S_RF0L_MASK (0x2000000U)
+#define CAN_RXF0S_RF0L_SHIFT (25U)
+/*! RF0L - Rx FIFO 0 message lost.
+ */
+#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
+/*! @} */
+
+/*! @name RXF0A - Rx FIFO 0 Acknowledge */
+/*! @{ */
+#define CAN_RXF0A_F0AI_MASK (0x3FU)
+#define CAN_RXF0A_F0AI_SHIFT (0U)
+/*! F0AI - Rx FIFO 0 acknowledge index.
+ */
+#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
+/*! @} */
+
+/*! @name RXBC - Rx Buffer Configuration */
+/*! @{ */
+#define CAN_RXBC_RBSA_MASK (0xFFFCU)
+#define CAN_RXBC_RBSA_SHIFT (2U)
+/*! RBSA - Rx buffer start address.
+ */
+#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
+/*! @} */
+
+/*! @name RXF1C - Rx FIFO 1 Configuration */
+/*! @{ */
+#define CAN_RXF1C_F1SA_MASK (0xFFFCU)
+#define CAN_RXF1C_F1SA_SHIFT (2U)
+/*! F1SA - Rx FIFO 1 start address.
+ */
+#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
+#define CAN_RXF1C_F1S_MASK (0x7F0000U)
+#define CAN_RXF1C_F1S_SHIFT (16U)
+/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.
+ */
+#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
+#define CAN_RXF1C_F1WM_MASK (0x7F000000U)
+#define CAN_RXF1C_F1WM_SHIFT (24U)
+/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
+ */
+#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
+#define CAN_RXF1C_F1OM_MASK (0x80000000U)
+#define CAN_RXF1C_F1OM_SHIFT (31U)
+/*! F1OM - FIFO 1 operation mode.
+ */
+#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
+/*! @} */
+
+/*! @name RXF1S - Rx FIFO 1 Status */
+/*! @{ */
+#define CAN_RXF1S_F1FL_MASK (0x7FU)
+#define CAN_RXF1S_F1FL_SHIFT (0U)
+/*! F1FL - Rx FIFO 1 fill level.
+ */
+#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
+#define CAN_RXF1S_F1GI_MASK (0x3F00U)
+#define CAN_RXF1S_F1GI_SHIFT (8U)
+/*! F1GI - Rx FIFO 1 get index.
+ */
+#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
+#define CAN_RXF1S_F1PI_MASK (0x3F0000U)
+#define CAN_RXF1S_F1PI_SHIFT (16U)
+/*! F1PI - Rx FIFO 1 put index.
+ */
+#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
+#define CAN_RXF1S_F1F_MASK (0x1000000U)
+#define CAN_RXF1S_F1F_SHIFT (24U)
+/*! F1F - Rx FIFO 1 full.
+ */
+#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
+#define CAN_RXF1S_RF1L_MASK (0x2000000U)
+#define CAN_RXF1S_RF1L_SHIFT (25U)
+/*! RF1L - Rx FIFO 1 message lost.
+ */
+#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
+/*! @} */
+
+/*! @name RXF1A - Rx FIFO 1 Acknowledge */
+/*! @{ */
+#define CAN_RXF1A_F1AI_MASK (0x3FU)
+#define CAN_RXF1A_F1AI_SHIFT (0U)
+/*! F1AI - Rx FIFO 1 acknowledge index.
+ */
+#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
+/*! @} */
+
+/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
+/*! @{ */
+#define CAN_RXESC_F0DS_MASK (0x7U)
+#define CAN_RXESC_F0DS_SHIFT (0U)
+/*! F0DS - Rx FIFO 0 data field size.
+ */
+#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
+#define CAN_RXESC_F1DS_MASK (0x70U)
+#define CAN_RXESC_F1DS_SHIFT (4U)
+/*! F1DS - Rx FIFO 1 data field size.
+ */
+#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
+#define CAN_RXESC_RBDS_MASK (0x700U)
+#define CAN_RXESC_RBDS_SHIFT (8U)
+/*! RBDS - .
+ */
+#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
+/*! @} */
+
+/*! @name TXBC - Tx Buffer Configuration */
+/*! @{ */
+#define CAN_TXBC_TBSA_MASK (0xFFFCU)
+#define CAN_TXBC_TBSA_SHIFT (2U)
+/*! TBSA - Tx buffers start address.
+ */
+#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
+#define CAN_TXBC_NDTB_MASK (0x3F0000U)
+#define CAN_TXBC_NDTB_SHIFT (16U)
+/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
+ */
+#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
+#define CAN_TXBC_TFQS_MASK (0x3F000000U)
+#define CAN_TXBC_TFQS_SHIFT (24U)
+/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.
+ */
+#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
+#define CAN_TXBC_TFQM_MASK (0x40000000U)
+#define CAN_TXBC_TFQM_SHIFT (30U)
+/*! TFQM - Tx FIFO/queue mode.
+ */
+#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
+/*! @} */
+
+/*! @name TXFQS - Tx FIFO/Queue Status */
+/*! @{ */
+#define CAN_TXFQS_TFGI_MASK (0x1F00U)
+#define CAN_TXFQS_TFGI_SHIFT (8U)
+/*! TFGI - Tx FIFO get index.
+ */
+#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
+#define CAN_TXFQS_TFQPI_MASK (0x1F0000U)
+#define CAN_TXFQS_TFQPI_SHIFT (16U)
+/*! TFQPI - Tx FIFO/queue put index.
+ */
+#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
+#define CAN_TXFQS_TFQF_MASK (0x200000U)
+#define CAN_TXFQS_TFQF_SHIFT (21U)
+/*! TFQF - Tx FIFO/queue full.
+ */
+#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
+/*! @} */
+
+/*! @name TXESC - Tx Buffer Element Size Configuration */
+/*! @{ */
+#define CAN_TXESC_TBDS_MASK (0x7U)
+#define CAN_TXESC_TBDS_SHIFT (0U)
+/*! TBDS - Tx buffer data field size.
+ */
+#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
+/*! @} */
+
+/*! @name TXBRP - Tx Buffer Request Pending */
+/*! @{ */
+#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)
+#define CAN_TXBRP_TRP_SHIFT (0U)
+/*! TRP - Transmission request pending.
+ */
+#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
+/*! @} */
+
+/*! @name TXBAR - Tx Buffer Add Request */
+/*! @{ */
+#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)
+#define CAN_TXBAR_AR_SHIFT (0U)
+/*! AR - Add request.
+ */
+#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
+/*! @} */
+
+/*! @name TXBCR - Tx Buffer Cancellation Request */
+/*! @{ */
+#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)
+#define CAN_TXBCR_CR_SHIFT (0U)
+/*! CR - Cancellation request.
+ */
+#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
+/*! @} */
+
+/*! @name TXBTO - Tx Buffer Transmission Occurred */
+/*! @{ */
+#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)
+#define CAN_TXBTO_TO_SHIFT (0U)
+/*! TO - Transmission occurred.
+ */
+#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
+/*! @} */
+
+/*! @name TXBCF - Tx Buffer Cancellation Finished */
+/*! @{ */
+#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)
+#define CAN_TXBCF_TO_SHIFT (0U)
+/*! TO - Cancellation finished.
+ */
+#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
+/*! @} */
+
+/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
+/*! @{ */
+#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)
+#define CAN_TXBTIE_TIE_SHIFT (0U)
+/*! TIE - Transmission interrupt enable.
+ */
+#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
+/*! @} */
+
+/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
+/*! @{ */
+#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)
+#define CAN_TXBCIE_CFIE_SHIFT (0U)
+/*! CFIE - Cancellation finished interrupt enable.
+ */
+#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
+/*! @} */
+
+/*! @name TXEFC - Tx Event FIFO Configuration */
+/*! @{ */
+#define CAN_TXEFC_EFSA_MASK (0xFFFCU)
+#define CAN_TXEFC_EFSA_SHIFT (2U)
+/*! EFSA - Event FIFO start address.
+ */
+#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
+#define CAN_TXEFC_EFS_MASK (0x3F0000U)
+#define CAN_TXEFC_EFS_SHIFT (16U)
+/*! EFS - Event FIFO size 0 = Tx event FIFO disabled.
+ */
+#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
+#define CAN_TXEFC_EFWM_MASK (0x3F000000U)
+#define CAN_TXEFC_EFWM_SHIFT (24U)
+/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.
+ */
+#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
+/*! @} */
+
+/*! @name TXEFS - Tx Event FIFO Status */
+/*! @{ */
+#define CAN_TXEFS_EFFL_MASK (0x3FU)
+#define CAN_TXEFS_EFFL_SHIFT (0U)
+/*! EFFL - Event FIFO fill level.
+ */
+#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
+#define CAN_TXEFS_EFGI_MASK (0x1F00U)
+#define CAN_TXEFS_EFGI_SHIFT (8U)
+/*! EFGI - Event FIFO get index.
+ */
+#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
+#define CAN_TXEFS_EFPI_MASK (0x3F0000U)
+#define CAN_TXEFS_EFPI_SHIFT (16U)
+/*! EFPI - Event FIFO put index.
+ */
+#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
+#define CAN_TXEFS_EFF_MASK (0x1000000U)
+#define CAN_TXEFS_EFF_SHIFT (24U)
+/*! EFF - Event FIFO full.
+ */
+#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
+#define CAN_TXEFS_TEFL_MASK (0x2000000U)
+#define CAN_TXEFS_TEFL_SHIFT (25U)
+/*! TEFL - Tx event FIFO element lost.
+ */
+#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
+/*! @} */
+
+/*! @name TXEFA - Tx Event FIFO Acknowledge */
+/*! @{ */
+#define CAN_TXEFA_EFAI_MASK (0x1FU)
+#define CAN_TXEFA_EFAI_SHIFT (0U)
+/*! EFAI - Event FIFO acknowledge index.
+ */
+#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
+/*! @} */
+
+/*! @name MRBA - CAN Message RAM Base Address */
+/*! @{ */
+#define CAN_MRBA_BA_MASK (0xFFFF0000U)
+#define CAN_MRBA_BA_SHIFT (16U)
+/*! BA - Base address for the message RAM in the chip memory map.
+ */
+#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
+/*! @} */
+
+/*! @name ETSCC - External Timestamp Counter Configuration */
+/*! @{ */
+#define CAN_ETSCC_ETCP_MASK (0x7FFU)
+#define CAN_ETSCC_ETCP_SHIFT (0U)
+/*! ETCP - External timestamp prescaler value.
+ */
+#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
+#define CAN_ETSCC_ETCE_MASK (0x80000000U)
+#define CAN_ETSCC_ETCE_SHIFT (31U)
+/*! ETCE - External timestamp counter enable.
+ */
+#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
+/*! @} */
+
+/*! @name ETSCV - External Timestamp Counter Value */
+/*! @{ */
+#define CAN_ETSCV_ETSC_MASK (0xFFFFU)
+#define CAN_ETSCV_ETSC_SHIFT (0U)
+/*! ETSC - External timestamp counter.
+ */
+#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE (0x4009D000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0 ((CAN_Type *)CAN0_BASE)
+/** Peripheral CAN1 base address */
+#define CAN1_BASE (0x4009E000u)
+/** Peripheral CAN1 base pointer */
+#define CAN1 ((CAN_Type *)CAN1_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS { CAN0, CAN1 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
+ __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
+ union { /* offset: 0x8 */
+ __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
+ __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
+ };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - CRC mode register */
+/*! @{ */
+#define CRC_MODE_CRC_POLY_MASK (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT (0U)
+/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
+ */
+#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
+/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
+ */
+#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+#define CRC_MODE_CMPL_WR_MASK (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT (3U)
+/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
+ */
+#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
+/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
+ */
+#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+#define CRC_MODE_CMPL_SUM_MASK (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT (5U)
+/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
+ */
+#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+/*! @} */
+
+/*! @name SEED - CRC seed register */
+/*! @{ */
+#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT (0U)
+/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
+ * selected bit order and 1's complement pre-processes. A write access to this register will
+ * overrule the CRC calculation in progresses.
+ */
+#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+/*! @} */
+
+/*! @name SUM - CRC checksum register */
+/*! @{ */
+#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT (0U)
+/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
+ */
+#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+/*! @} */
+
+/*! @name WR_DATA - CRC data register */
+/*! @{ */
+#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
+/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
+ * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
+ * accept back-to-back transactions.
+ */
+#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC_ENGINE base address */
+#define CRC_ENGINE_BASE (0x40095000u)
+/** Peripheral CRC_ENGINE base pointer */
+#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS { CRC_ENGINE }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CTIMER Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
+ __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
+ __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
+ __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
+ __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
+ __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
+ __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
+ __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
+ __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
+ __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
+ uint8_t RESERVED_0[48];
+ __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
+ __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
+ __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CTIMER Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+/*! @{ */
+#define CTIMER_IR_MR0INT_MASK (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT (0U)
+/*! MR0INT - Interrupt flag for match channel 0.
+ */
+#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+#define CTIMER_IR_MR1INT_MASK (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT (1U)
+/*! MR1INT - Interrupt flag for match channel 1.
+ */
+#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+#define CTIMER_IR_MR2INT_MASK (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT (2U)
+/*! MR2INT - Interrupt flag for match channel 2.
+ */
+#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+#define CTIMER_IR_MR3INT_MASK (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT (3U)
+/*! MR3INT - Interrupt flag for match channel 3.
+ */
+#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+#define CTIMER_IR_CR0INT_MASK (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT (4U)
+/*! CR0INT - Interrupt flag for capture channel 0 event.
+ */
+#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+#define CTIMER_IR_CR1INT_MASK (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT (5U)
+/*! CR1INT - Interrupt flag for capture channel 1 event.
+ */
+#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+#define CTIMER_IR_CR2INT_MASK (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT (6U)
+/*! CR2INT - Interrupt flag for capture channel 2 event.
+ */
+#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+#define CTIMER_IR_CR3INT_MASK (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT (7U)
+/*! CR3INT - Interrupt flag for capture channel 3 event.
+ */
+#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+/*! @} */
+
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+/*! @{ */
+#define CTIMER_TCR_CEN_MASK (0x1U)
+#define CTIMER_TCR_CEN_SHIFT (0U)
+/*! CEN - Counter enable.
+ * 0b0..Disabled.The counters are disabled.
+ * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
+ */
+#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+#define CTIMER_TCR_CRST_MASK (0x2U)
+#define CTIMER_TCR_CRST_SHIFT (1U)
+/*! CRST - Counter reset.
+ * 0b0..Disabled. Do nothing.
+ * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
+ * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
+ */
+#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+/*! @} */
+
+/*! @name TC - Timer Counter */
+/*! @{ */
+#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT (0U)
+/*! TCVAL - Timer counter value.
+ */
+#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+/*! @} */
+
+/*! @name PR - Prescale Register */
+/*! @{ */
+#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT (0U)
+/*! PRVAL - Prescale counter value.
+ */
+#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+/*! @} */
+
+/*! @name PC - Prescale Counter */
+/*! @{ */
+#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT (0U)
+/*! PCVAL - Prescale counter value.
+ */
+#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+/*! @} */
+
+/*! @name MCR - Match Control Register */
+/*! @{ */
+#define CTIMER_MCR_MR0I_MASK (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT (0U)
+/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+#define CTIMER_MCR_MR0R_MASK (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT (1U)
+/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
+ */
+#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+#define CTIMER_MCR_MR0S_MASK (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT (2U)
+/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
+ */
+#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+#define CTIMER_MCR_MR1I_MASK (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT (3U)
+/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+#define CTIMER_MCR_MR1R_MASK (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT (4U)
+/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
+ */
+#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+#define CTIMER_MCR_MR1S_MASK (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT (5U)
+/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
+ */
+#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+#define CTIMER_MCR_MR2I_MASK (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT (6U)
+/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+#define CTIMER_MCR_MR2R_MASK (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT (7U)
+/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
+ */
+#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+#define CTIMER_MCR_MR2S_MASK (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT (8U)
+/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
+ */
+#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+#define CTIMER_MCR_MR3I_MASK (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT (9U)
+/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+#define CTIMER_MCR_MR3R_MASK (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT (10U)
+/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
+ */
+#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+#define CTIMER_MCR_MR3S_MASK (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT (11U)
+/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
+ */
+#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT (24U)
+/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
+ * (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT (25U)
+/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
+ * (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT (26U)
+/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
+ * (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT (27U)
+/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
+ * (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+/*! @} */
+
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+/*! @{ */
+#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT (0U)
+/*! MATCH - Timer counter match value.
+ */
+#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+/*! @} */
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT (4U)
+
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+/*! @{ */
+#define CTIMER_CCR_CAP0RE_MASK (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT (0U)
+/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
+ * the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+#define CTIMER_CCR_CAP0FE_MASK (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT (1U)
+/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
+ * the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+#define CTIMER_CCR_CAP0I_MASK (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT (2U)
+/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+#define CTIMER_CCR_CAP1RE_MASK (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT (3U)
+/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
+ * the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+#define CTIMER_CCR_CAP1FE_MASK (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT (4U)
+/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
+ * the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+#define CTIMER_CCR_CAP1I_MASK (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT (5U)
+/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+#define CTIMER_CCR_CAP2RE_MASK (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT (6U)
+/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
+ * the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+#define CTIMER_CCR_CAP2FE_MASK (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT (7U)
+/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
+ * the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+#define CTIMER_CCR_CAP2I_MASK (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT (8U)
+/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+#define CTIMER_CCR_CAP3RE_MASK (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT (9U)
+/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
+ * the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+#define CTIMER_CCR_CAP3FE_MASK (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT (10U)
+/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
+ * the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+#define CTIMER_CCR_CAP3I_MASK (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT (11U)
+/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+/*! @} */
+
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
+/*! @{ */
+#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT (0U)
+/*! CAP - Timer counter capture value.
+ */
+#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+/*! @} */
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT (4U)
+
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
+/*! @{ */
+#define CTIMER_EMR_EM0_MASK (0x1U)
+#define CTIMER_EMR_EM0_SHIFT (0U)
+/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
+ * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
+ * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
+ * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+#define CTIMER_EMR_EM1_MASK (0x2U)
+#define CTIMER_EMR_EM1_SHIFT (1U)
+/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
+ * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
+ * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
+ * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+#define CTIMER_EMR_EM2_MASK (0x4U)
+#define CTIMER_EMR_EM2_SHIFT (2U)
+/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
+ * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
+ * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
+ * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+#define CTIMER_EMR_EM3_MASK (0x8U)
+#define CTIMER_EMR_EM3_SHIFT (3U)
+/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
+ * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
+ * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
+ * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+#define CTIMER_EMR_EMC0_MASK (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT (4U)
+/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
+ * 0b00..Do Nothing.
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+#define CTIMER_EMR_EMC1_MASK (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT (6U)
+/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
+ * 0b00..Do Nothing.
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+#define CTIMER_EMR_EMC2_MASK (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT (8U)
+/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
+ * 0b00..Do Nothing.
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+#define CTIMER_EMR_EMC3_MASK (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT (10U)
+/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
+ * 0b00..Do Nothing.
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+/*! @} */
+
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+/*! @{ */
+#define CTIMER_CTCR_CTMODE_MASK (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT (0U)
+/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
+ * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
+ * is incremented when the Prescale Counter matches the Prescale Register.
+ * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
+ * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
+ * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
+ * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
+ */
+#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+#define CTIMER_CTCR_CINSEL_MASK (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT (2U)
+/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
+ * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
+ * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
+ * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
+ * same timer.
+ * 0b00..Channel 0. CAPn.0 for CTIMERn
+ * 0b01..Channel 1. CAPn.1 for CTIMERn
+ * 0b10..Channel 2. CAPn.2 for CTIMERn
+ * 0b11..Channel 3. CAPn.3 for CTIMERn
+ */
+#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+#define CTIMER_CTCR_ENCC_MASK (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT (4U)
+/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
+ * capture-edge event specified in bits 7:5 occurs.
+ */
+#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+#define CTIMER_CTCR_SELCC_MASK (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT (5U)
+/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
+ * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
+ * 0x3 and 0x6 to 0x7 are reserved.
+ * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ */
+#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+/*! @} */
+
+/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
+/*! @{ */
+#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
+/*! PWMEN0 - PWM mode enable for channel0.
+ * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
+ */
+#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
+/*! PWMEN1 - PWM mode enable for channel1.
+ * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
+ */
+#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
+/*! PWMEN2 - PWM mode enable for channel2.
+ * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
+ */
+#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
+/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
+ * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
+ * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
+ */
+#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+/*! @} */
+
+/*! @name MSR - Match Shadow Register */
+/*! @{ */
+#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
+#define CTIMER_MSR_SHADOWW_SHIFT (0U)
+/*! SHADOWW - Timer counter match shadow value.
+ */
+#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
+/*! @} */
+
+/* The count of CTIMER_MSR */
+#define CTIMER_MSR_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE (0x40008000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE (0x40009000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE (0x40028000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
+/** Peripheral CTIMER3 base address */
+#define CTIMER3_BASE (0x40048000u)
+/** Peripheral CTIMER3 base pointer */
+#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
+/** Peripheral CTIMER4 base address */
+#define CTIMER4_BASE (0x40049000u)
+/** Peripheral CTIMER4 base pointer */
+#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
+ __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
+ __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
+ uint8_t RESERVED_0[20];
+ struct { /* offset: 0x20, array step: 0x5C */
+ __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
+ uint8_t RESERVED_0[4];
+ __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
+ uint8_t RESERVED_1[4];
+ __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
+ uint8_t RESERVED_2[4];
+ __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
+ uint8_t RESERVED_5[4];
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
+ uint8_t RESERVED_6[4];
+ __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
+ uint8_t RESERVED_7[4];
+ __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
+ uint8_t RESERVED_8[4];
+ __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
+ uint8_t RESERVED_9[4];
+ __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
+ uint8_t RESERVED_10[4];
+ __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
+ } COMMON[1];
+ uint8_t RESERVED_1[900];
+ struct { /* offset: 0x400, array step: 0x10 */
+ __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
+ __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
+ __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } CHANNEL[32];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control. */
+/*! @{ */
+#define DMA_CTRL_ENABLE_MASK (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT (0U)
+/*! ENABLE - DMA controller master enable.
+ * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
+ * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
+ * 0b1..Enabled. The DMA controller is enabled.
+ */
+#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt status. */
+/*! @{ */
+#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
+/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
+ * 0b0..Not pending. No enabled interrupts are pending.
+ * 0b1..Pending. At least one enabled interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
+/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
+ * 0b0..Not pending. No error interrupts are pending.
+ * 0b1..Pending. At least one error interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+/*! @} */
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */
+/*! @{ */
+#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
+/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
+ * table must begin on a 512 byte boundary.
+ */
+#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+/*! @} */
+
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
+/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
+ * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
+/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
+ * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
+ * are reserved.
+ */
+#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
+/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
+ * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
+ */
+#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
+/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
+ * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
+ */
+#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
+/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
+ * not active. 1 = error interrupt is active.
+ */
+#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
+/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
+ * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
+ * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
+/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
+ * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
+ * reserved.
+ */
+#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTA_IA_SHIFT (0U)
+/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
+ * interrupt A is not active. 1 = the DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTB_IB_SHIFT (0U)
+/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
+ * interrupt B is not active. 1 = the DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
+/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
+ * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
+ * VALIDPENDING control bit for DMA channel n
+ */
+#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
+/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
+ * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
+ * sets the TRIG bit for DMA channel n.
+ */
+#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
+/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
+ * 1 = aborts DMA operations on channel n.
+ */
+#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
+/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
+ * move, any peripheral DMA request associated with that channel can be disabled to prevent any
+ * interaction between the peripheral and the DMA controller.
+ * 0b0..Disabled. Peripheral DMA requests are disabled.
+ * 0b1..Enabled. Peripheral DMA requests are enabled.
+ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
+/*! HWTRIGEN - Hardware Triggering Enable for this channel.
+ * 0b0..Disabled. Hardware triggering is not used.
+ * 0b1..Enabled. Use hardware triggering.
+ */
+#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
+/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
+ * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
+ * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
+ */
+#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
+/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
+ * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
+ * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
+ * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
+ * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
+ * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
+ * current BURSTPOWER length are completed.
+ */
+#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
+/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
+ * 0b0..Single transfer. Hardware trigger causes a single transfer.
+ * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
+ * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
+ * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
+ * complete.
+ */
+#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
+/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
+ * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
+ * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
+ * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
+ * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
+ * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
+ * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
+ * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
+ * multiple of the burst size.
+ */
+#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
+/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
+ * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
+ * could be used to read several sequential registers from a peripheral for each DMA burst,
+ * reading the same registers again for each burst.
+ * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
+ * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
+/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
+ * 'wrapped', meaning that the destination address range for each burst will be the same. As an
+ * example, this could be used to write several sequential registers to a peripheral for each DMA
+ * burst, writing the same registers again for each burst.
+ * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
+ * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
+/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
+ * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
+ */
+#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CFG */
+#define DMA_CHANNEL_CFG_COUNT (32U)
+
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
+/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
+ * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
+ * 0b0..No effect. No effect on DMA operation.
+ * 0b1..Valid pending.
+ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
+/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
+ * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
+ * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
+ * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
+ */
+#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CTLSTAT */
+#define DMA_CHANNEL_CTLSTAT_COUNT (32U)
+
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
+/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
+ * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
+ * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
+ * 0b1..Valid. The current channel descriptor is considered valid.
+ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
+/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
+ * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
+ * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
+ * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
+/*! SWTRIG - Software Trigger.
+ * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
+ * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
+ * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
+ * be used with level triggering when TRIGBURST = 0.
+ */
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
+/*! CLRTRIG - Clear Trigger.
+ * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
+ * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
+ */
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
+/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
+ * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
+ * convention, interrupt A may be used when only one interrupt flag is needed.
+ * 0b0..No effect.
+ * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
+/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
+ * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
+ * convention, interrupt A may be used when only one interrupt flag is needed.
+ * 0b0..No effect.
+ * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
+/*! WIDTH - Transfer width used for this DMA channel.
+ * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
+ * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
+ * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
+ * 0b11..Reserved. Reserved setting, do not use.
+ */
+#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
+/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
+ * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
+ * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
+ * the usual case when the source is memory.
+ * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
+ * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
+ */
+#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
+/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
+ * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
+ * the destination is a peripheral device.
+ * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
+ * This is the usual case when the destination is memory.
+ * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
+ * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
+ */
+#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
+/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
+ * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
+ * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
+ * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
+ * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
+ * 1,024 transfers will be performed.
+ */
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_XFERCFG */
+#define DMA_CHANNEL_XFERCFG_COUNT (32U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE (0x40082000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0 ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_IRQS { DMA0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMIC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
+ * @{
+ */
+
+/** DMIC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x100 */
+ __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
+ __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
+ __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
+ __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
+ __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
+ uint8_t RESERVED_0[108];
+ __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
+ __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
+ __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
+ __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
+ __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
+ uint8_t RESERVED_1[108];
+ } CHANNEL[2];
+ uint8_t RESERVED_0[3328];
+ __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */
+ uint8_t RESERVED_1[8];
+ __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */
+ __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */
+ uint8_t RESERVED_2[108];
+ __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */
+ __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */
+ __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */
+ __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */
+ __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */
+ __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */
+ __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */
+ uint8_t RESERVED_3[96];
+ __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */
+} DMIC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMIC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_OSR - Oversample Rate register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
+#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
+/*! OSR - Selects the oversample rate for the related input channel.
+ */
+#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_OSR */
+#define DMIC_CHANNEL_OSR_COUNT (2U)
+
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
+/*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by
+ * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =
+ * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =
+ * reserved.
+ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DIVHFCLK */
+#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)
+
+/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
+/*! @{ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
+/*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16
+ * 2 = Compensation = 15 3 = Compensation = 13
+ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)
+
+/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
+/*! @{ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
+/*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16
+ * 2 = Compensation = 15 3 = Compensation = 13
+ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)
+
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
+/*! @{ */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
+/*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.
+ */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_GAINSHIFT */
+#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)
+
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
+/*! ENABLE - FIFO enable.
+ * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
+ * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
+ * period when the data was not needed.
+ * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
+/*! RESETN - FIFO reset.
+ * 0b0..Reset the FIFO.
+ * 0b1..Normal operation
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
+/*! INTEN - Interrupt enable.
+ * 0b0..FIFO level interrupts are not enabled.
+ * 0b1..FIFO level interrupts are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
+/*! DMAEN - DMA enable
+ * 0b0..DMA requests are not enabled.
+ * 0b1..DMA requests based on FIFO level are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
+/*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If
+ * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then
+ * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =
+ * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has
+ * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_CTRL */
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)
+
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
+/*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL
+ * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC
+ * subsystem must be running in order for an interrupt to occur.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
+/*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one
+ * to this bit clears the flag. This flag does not cause an interrupt.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
+/*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_STATUS */
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)
+
+/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
+/*! DATA - Data from the top of the input filter FIFO.
+ */
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_DATA */
+#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)
+
+/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
+/*! PHY_FALL - Capture PDM_DATA
+ * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
+ * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
+/*! PHY_HALF - Half rate sampling
+ * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
+ * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PHY_CTRL */
+#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)
+
+/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
+/*! DCPOLE - DC block filter
+ * 0b00..Flat response, no filter.
+ * 0b01..155 Hz.
+ * 0b10..78 Hz.
+ * 0b11..39 Hz
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
+/*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
+/*! SATURATEAT16BIT - Selects 16-bit saturation.
+ * 0b0..Results roll over if out range and do not saturate.
+ * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
+ */
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DC_CTRL */
+#define DMIC_CHANNEL_DC_CTRL_COUNT (2U)
+
+/*! @name CHANEN - Channel Enable register */
+/*! @{ */
+#define DMIC_CHANEN_EN_CH0_MASK (0x1U)
+#define DMIC_CHANEN_EN_CH0_SHIFT (0U)
+/*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.
+ */
+#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
+#define DMIC_CHANEN_EN_CH1_MASK (0x2U)
+#define DMIC_CHANEN_EN_CH1_SHIFT (1U)
+/*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.
+ */
+#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
+/*! @} */
+
+/*! @name IOCFG - I/O Configuration register */
+/*! @{ */
+#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)
+#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)
+/*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides
+ * for the possibility of an external codec taking over the PDM bus.
+ */
+#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
+#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)
+#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)
+/*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides
+ * for the possibility of an external codec taking over the PDM bus.
+ */
+#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
+#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)
+#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)
+/*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a
+ * configuration that supports a single stereo digital microphone.
+ */
+#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
+/*! @} */
+
+/*! @name USE2FS - Use 2FS register */
+/*! @{ */
+#define DMIC_USE2FS_USE2FS_MASK (0x1U)
+#define DMIC_USE2FS_USE2FS_SHIFT (0U)
+/*! USE2FS - Use 2FS register
+ * 0b0..Use 1FS output for PCM data.
+ * 0b1..Use 2FS output for PCM data.
+ */
+#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
+/*! @} */
+
+/*! @name HWVADGAIN - HWVAD input gain register */
+/*! @{ */
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
+/*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04
+ * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10
+ * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.
+ */
+#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
+/*! @} */
+
+/*! @name HWVADHPFS - HWVAD filter control register */
+/*! @{ */
+#define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
+#define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
+/*! HPFS - High pass filter
+ * 0b00..First filter by-pass.
+ * 0b01..High pass filter with -3dB cut-off at 1750Hz.
+ * 0b10..High pass filter with -3dB cut-off at 215Hz.
+ * 0b11..Reserved.
+ */
+#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
+/*! @} */
+
+/*! @name HWVADST10 - HWVAD control register */
+/*! @{ */
+#define DMIC_HWVADST10_ST10_MASK (0x1U)
+#define DMIC_HWVADST10_ST10_SHIFT (0U)
+/*! ST10 - Stage 0
+ * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
+ * 0b1..Reset internal interrupt flag by writing a '1' pulse.
+ */
+#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
+/*! @} */
+
+/*! @name HWVADRSTT - HWVAD filter reset register */
+/*! @{ */
+#define DMIC_HWVADRSTT_RSTT_MASK (0x1U)
+#define DMIC_HWVADRSTT_RSTT_SHIFT (0U)
+/*! RSTT - Writing a 1 resets all filter values
+ */
+#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
+/*! @} */
+
+/*! @name HWVADTHGN - HWVAD noise estimator gain register */
+/*! @{ */
+#define DMIC_HWVADTHGN_THGN_MASK (0xFU)
+#define DMIC_HWVADTHGN_THGN_SHIFT (0U)
+/*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.
+ */
+#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
+/*! @} */
+
+/*! @name HWVADTHGS - HWVAD signal estimator gain register */
+/*! @{ */
+#define DMIC_HWVADTHGS_THGS_MASK (0xFU)
+#define DMIC_HWVADTHGS_THGS_SHIFT (0U)
+/*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.
+ */
+#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
+/*! @} */
+
+/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
+/*! @{ */
+#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
+/*! LOWZ - Noise envelope estimator value.
+ */
+#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
+/*! @} */
+
+/*! @name ID - Module Identification register */
+/*! @{ */
+#define DMIC_ID_ID_MASK (0xFFFFFFFFU)
+#define DMIC_ID_ID_SHIFT (0U)
+/*! ID - Indicates module ID and the number of channels in this DMIC interface.
+ */
+#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DMIC_Register_Masks */
+
+
+/* DMIC - Peripheral instance base addresses */
+/** Peripheral DMIC0 base address */
+#define DMIC0_BASE (0x40090000u)
+/** Peripheral DMIC0 base pointer */
+#define DMIC0 ((DMIC_Type *)DMIC0_BASE)
+/** Array initializer of DMIC peripheral base addresses */
+#define DMIC_BASE_ADDRS { DMIC0_BASE }
+/** Array initializer of DMIC peripheral base pointers */
+#define DMIC_BASE_PTRS { DMIC0 }
+/** Interrupt vectors for the DMIC peripheral type */
+#define DMIC_IRQS { DMIC0_IRQn }
+#define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
+ * @{
+ */
+
+/** EMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */
+ __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */
+ __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */
+ uint8_t RESERVED_0[20];
+ __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */
+ __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */
+ __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */
+ __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */
+ __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */
+ __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */
+ __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */
+ __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */
+ __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */
+ __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */
+ __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */
+ __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */
+ __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */
+ uint8_t RESERVED_2[36];
+ __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */
+ uint8_t RESERVED_3[124];
+ struct { /* offset: 0x100, array step: 0x20 */
+ __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
+ __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
+ uint8_t RESERVED_0[24];
+ } DYNAMIC[4];
+ uint8_t RESERVED_4[128];
+ struct { /* offset: 0x200, array step: 0x20 */
+ __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
+ __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
+ __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
+ __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
+ __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
+ __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
+ __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
+ uint8_t RESERVED_0[4];
+ } STATIC[4];
+} EMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- EMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Register_Masks EMC Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Controls operation of the memory controller */
+/*! @{ */
+#define EMC_CONTROL_E_MASK (0x1U)
+#define EMC_CONTROL_E_SHIFT (0U)
+/*! E - EMC Enable.
+ */
+#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
+#define EMC_CONTROL_M_MASK (0x2U)
+#define EMC_CONTROL_M_SHIFT (1U)
+/*! M - Address mirror.
+ */
+#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
+#define EMC_CONTROL_L_MASK (0x4U)
+#define EMC_CONTROL_L_SHIFT (2U)
+/*! L - Low-power mode.
+ */
+#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
+/*! @} */
+
+/*! @name STATUS - Provides EMC status information */
+/*! @{ */
+#define EMC_STATUS_B_MASK (0x1U)
+#define EMC_STATUS_B_SHIFT (0U)
+/*! B - Busy.
+ */
+#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
+#define EMC_STATUS_S_MASK (0x2U)
+#define EMC_STATUS_S_SHIFT (1U)
+/*! S - Write buffer status.
+ */
+#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
+#define EMC_STATUS_SA_MASK (0x4U)
+#define EMC_STATUS_SA_SHIFT (2U)
+/*! SA - Self-refresh acknowledge.
+ */
+#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
+/*! @} */
+
+/*! @name CONFIG - Configures operation of the memory controller */
+/*! @{ */
+#define EMC_CONFIG_EM_MASK (0x1U)
+#define EMC_CONFIG_EM_SHIFT (0U)
+/*! EM - Endian mode.
+ */
+#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
+#define EMC_CONFIG_CLKR_MASK (0x100U)
+#define EMC_CONFIG_CLKR_SHIFT (8U)
+/*! CLKR - This bit must contain 0 for proper operation of the EMC.
+ */
+#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
+/*! @} */
+
+/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
+/*! @{ */
+#define EMC_DYNAMICCONTROL_CE_MASK (0x1U)
+#define EMC_DYNAMICCONTROL_CE_SHIFT (0U)
+/*! CE - Dynamic memory clock enable.
+ */
+#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
+#define EMC_DYNAMICCONTROL_CS_MASK (0x2U)
+#define EMC_DYNAMICCONTROL_CS_SHIFT (1U)
+/*! CS - Dynamic memory clock control.
+ */
+#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
+#define EMC_DYNAMICCONTROL_SR_MASK (0x4U)
+#define EMC_DYNAMICCONTROL_SR_SHIFT (2U)
+/*! SR - Self-refresh request, EMCSREFREQ.
+ */
+#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
+#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U)
+#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U)
+/*! MMC - Memory clock control.
+ */
+#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
+#define EMC_DYNAMICCONTROL_I_MASK (0x180U)
+#define EMC_DYNAMICCONTROL_I_SHIFT (7U)
+/*! I - SDRAM initialization.
+ */
+#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
+/*! @} */
+
+/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
+/*! @{ */
+#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)
+#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)
+/*! REFRESH - Refresh timer.
+ */
+#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
+/*! @} */
+
+/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
+/*! @{ */
+#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)
+#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)
+/*! RD - Read data strategy.
+ */
+#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
+/*! @} */
+
+/*! @name DYNAMICRP - Precharge command period */
+/*! @{ */
+#define EMC_DYNAMICRP_TRP_MASK (0xFU)
+#define EMC_DYNAMICRP_TRP_SHIFT (0U)
+/*! TRP - Precharge command period.
+ */
+#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
+/*! @} */
+
+/*! @name DYNAMICRAS - Active to precharge command period */
+/*! @{ */
+#define EMC_DYNAMICRAS_TRAS_MASK (0xFU)
+#define EMC_DYNAMICRAS_TRAS_SHIFT (0U)
+/*! TRAS - Active to precharge command period.
+ */
+#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
+/*! @} */
+
+/*! @name DYNAMICSREX - Self-refresh exit time */
+/*! @{ */
+#define EMC_DYNAMICSREX_TSREX_MASK (0xFU)
+#define EMC_DYNAMICSREX_TSREX_SHIFT (0U)
+/*! TSREX - Self-refresh exit time.
+ */
+#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
+/*! @} */
+
+/*! @name DYNAMICAPR - Last-data-out to active command time */
+/*! @{ */
+#define EMC_DYNAMICAPR_TAPR_MASK (0xFU)
+#define EMC_DYNAMICAPR_TAPR_SHIFT (0U)
+/*! TAPR - Last-data-out to active command time.
+ */
+#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
+/*! @} */
+
+/*! @name DYNAMICDAL - Data-in to active command time */
+/*! @{ */
+#define EMC_DYNAMICDAL_TDAL_MASK (0xFU)
+#define EMC_DYNAMICDAL_TDAL_SHIFT (0U)
+/*! TDAL - Data-in to active command.
+ */
+#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
+/*! @} */
+
+/*! @name DYNAMICWR - Write recovery time */
+/*! @{ */
+#define EMC_DYNAMICWR_TWR_MASK (0xFU)
+#define EMC_DYNAMICWR_TWR_SHIFT (0U)
+/*! TWR - Write recovery time.
+ */
+#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
+/*! @} */
+
+/*! @name DYNAMICRC - Selects the active to active command period */
+/*! @{ */
+#define EMC_DYNAMICRC_TRC_MASK (0x1FU)
+#define EMC_DYNAMICRC_TRC_SHIFT (0U)
+/*! TRC - Active to active command period.
+ */
+#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
+/*! @} */
+
+/*! @name DYNAMICRFC - Selects the auto-refresh period */
+/*! @{ */
+#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU)
+#define EMC_DYNAMICRFC_TRFC_SHIFT (0U)
+/*! TRFC - Auto-refresh period and auto-refresh to active command period.
+ */
+#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
+/*! @} */
+
+/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
+/*! @{ */
+#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU)
+#define EMC_DYNAMICXSR_TXSR_SHIFT (0U)
+/*! TXSR - Exit self-refresh to active command time.
+ */
+#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
+/*! @} */
+
+/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
+/*! @{ */
+#define EMC_DYNAMICRRD_TRRD_MASK (0xFU)
+#define EMC_DYNAMICRRD_TRRD_SHIFT (0U)
+/*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
+ */
+#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
+/*! @} */
+
+/*! @name DYNAMICMRD - Time for load mode register to active command */
+/*! @{ */
+#define EMC_DYNAMICMRD_TMRD_MASK (0xFU)
+#define EMC_DYNAMICMRD_TMRD_SHIFT (0U)
+/*! TMRD - Load mode register to active command time.
+ */
+#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
+/*! @} */
+
+/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
+/*! @{ */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
+/*! EXTENDEDWAIT - Extended wait time out.
+ */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
+/*! @} */
+
+/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
+/*! @{ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)
+/*! MD - Memory device.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)
+/*! AM0 - See Table 933.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)
+/*! AM1 - See Table 933.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)
+/*! B - Buffer enable.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)
+/*! P - Write protect.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
+/*! @} */
+
+/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
+#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)
+
+/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
+/*! @{ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)
+/*! RAS - RAS latency (active to read/write delay).
+ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)
+/*! CAS - CAS latency.
+ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
+/*! @} */
+
+/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
+#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)
+
+/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)
+#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)
+/*! MW - Memory width.
+ */
+#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
+#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)
+#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)
+/*! PM - Page mode.
+ */
+#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
+#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)
+#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)
+/*! PC - Chip select polarity.
+ */
+#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
+#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)
+#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)
+/*! PB - Byte lane state.
+ */
+#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
+#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)
+#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)
+/*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write
+ * transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
+ */
+#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
+#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)
+#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U)
+/*! B - Buffer enable [2].
+ */
+#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
+#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)
+#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U)
+/*! P - Write protect.
+ */
+#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICCONFIG */
+#define EMC_STATIC_STATICCONFIG_COUNT (4U)
+
+/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
+/*! @{ */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)
+/*! WAITWEN - Wait write enable.
+ */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITWEN */
+#define EMC_STATIC_STATICWAITWEN_COUNT (4U)
+
+/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
+/*! @{ */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)
+/*! WAITOEN - Wait output enable.
+ */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITOEN */
+#define EMC_STATIC_STATICWAITOEN_COUNT (4U)
+
+/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
+/*! @{ */
+#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)
+#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)
+/*! WAITRD - .
+ */
+#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITRD */
+#define EMC_STATIC_STATICWAITRD_COUNT (4U)
+
+/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
+/*! WAITPAGE - Asynchronous page mode read after the first read wait states.
+ */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITPAGE */
+#define EMC_STATIC_STATICWAITPAGE_COUNT (4U)
+
+/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
+/*! @{ */
+#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)
+#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)
+/*! WAITWR - Write wait states.
+ */
+#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITWR */
+#define EMC_STATIC_STATICWAITWR_COUNT (4U)
+
+/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
+/*! WAITTURN - Bus turn-around cycles.
+ */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITTURN */
+#define EMC_STATIC_STATICWAITTURN_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group EMC_Register_Masks */
+
+
+/* EMC - Peripheral instance base addresses */
+/** Peripheral EMC base address */
+#define EMC_BASE (0x40081000u)
+/** Peripheral EMC base pointer */
+#define EMC ((EMC_Type *)EMC_BASE)
+/** Array initializer of EMC peripheral base addresses */
+#define EMC_BASE_ADDRS { EMC_BASE }
+/** Array initializer of EMC peripheral base pointers */
+#define EMC_BASE_PTRS { EMC }
+
+/*!
+ * @}
+ */ /* end of group EMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ENET Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */
+ __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */
+ __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */
+ __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */
+ uint8_t RESERVED_0[64];
+ __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[4];
+ __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */
+ __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */
+ __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */
+ uint8_t RESERVED_6[4];
+ __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */
+ __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */
+ uint8_t RESERVED_7[8];
+ __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */
+ __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */
+ __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */
+ __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */
+ uint8_t RESERVED_8[48];
+ __I uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */
+ __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */
+ uint8_t RESERVED_9[4];
+ __I uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
+ uint8_t RESERVED_10[216];
+ __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */
+ __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */
+ uint8_t RESERVED_11[248];
+ __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */
+ __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */
+ uint8_t RESERVED_12[2040];
+ __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */
+ __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */
+ __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */
+ __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */
+ __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */
+ __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */
+ __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */
+ __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */
+ __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */
+ uint8_t RESERVED_13[12];
+ __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
+ __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */
+ uint8_t RESERVED_14[32];
+ __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
+ __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
+ uint8_t RESERVED_15[160];
+ __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */
+ uint8_t RESERVED_16[28];
+ __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */
+ uint8_t RESERVED_17[12];
+ __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
+ uint8_t RESERVED_18[204];
+ struct { /* offset: 0xD00, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
+ __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
+ __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
+ __I uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */
+ __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
+ __I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
+ __I uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
+ __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
+ } MTL_QUEUE[2];
+ uint8_t RESERVED_19[640];
+ __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */
+ __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */
+ __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */
+ __I uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */
+ uint8_t RESERVED_20[240];
+ struct { /* offset: 0x1100, array step: 0x80 */
+ __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
+ __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
+ __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */
+ __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */
+ __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */
+ __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
+ __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
+ __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
+ __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
+ uint8_t RESERVED_3[4];
+ __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
+ uint8_t RESERVED_4[4];
+ __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */
+ uint8_t RESERVED_5[4];
+ __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
+ __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
+ uint8_t RESERVED_7[8];
+ __IO uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channelx missed frame count., array offset: 0x116C, array step: 0x80 */
+ uint8_t RESERVED_8[16];
+ } DMA_CH[2];
+} ENET_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ENET Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/*! @name MAC_CONFIG - MAC configuration register */
+/*! @{ */
+#define ENET_MAC_CONFIG_RE_MASK (0x1U)
+#define ENET_MAC_CONFIG_RE_SHIFT (0U)
+/*! RE - Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for
+ * receiving frames from the MII.
+ */
+#define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
+#define ENET_MAC_CONFIG_TE_MASK (0x2U)
+#define ENET_MAC_CONFIG_TE_SHIFT (1U)
+/*! TE - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII.
+ */
+#define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
+#define ENET_MAC_CONFIG_PRELEN_MASK (0xCU)
+#define ENET_MAC_CONFIG_PRELEN_SHIFT (2U)
+/*! PRELEN - Preamble Length for Transmit packets These bits control the number of preamble bytes
+ * that are added to the beginning of every Tx packet.
+ */
+#define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
+#define ENET_MAC_CONFIG_DC_MASK (0x10U)
+#define ENET_MAC_CONFIG_DC_SHIFT (4U)
+/*! DC - Deferral Check When this bit is set, the deferral check function is enabled in the MAC.
+ */
+#define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
+#define ENET_MAC_CONFIG_BL_MASK (0x60U)
+#define ENET_MAC_CONFIG_BL_SHIFT (5U)
+/*! BL - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time
+ * delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before
+ * rescheduling a transmission attempt during retries after a collision.
+ */
+#define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
+#define ENET_MAC_CONFIG_DR_MASK (0x100U)
+#define ENET_MAC_CONFIG_DR_SHIFT (8U)
+/*! DR - Disable Retry When this bit is set, the MAC will attempt only one transmission.
+ */
+#define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
+#define ENET_MAC_CONFIG_DCRS_MASK (0x200U)
+#define ENET_MAC_CONFIG_DCRS_SHIFT (9U)
+/*! DCRS - Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter
+ * ignores the MII CRS signal during packet transmission in the half-duplex mode.
+ */
+#define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
+#define ENET_MAC_CONFIG_DO_MASK (0x400U)
+#define ENET_MAC_CONFIG_DO_SHIFT (10U)
+/*! DO - Disable Receive Own When this bit is set, the MAC disables the reception of frames when the
+ * gmii_txen_o is asserted in Half-Duplex mode.
+ */
+#define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
+#define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U)
+#define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U)
+/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the
+ * MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode.
+ */
+#define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
+#define ENET_MAC_CONFIG_LM_MASK (0x1000U)
+#define ENET_MAC_CONFIG_LM_SHIFT (12U)
+/*! LM - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII.
+ */
+#define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
+#define ENET_MAC_CONFIG_DM_MASK (0x2000U)
+#define ENET_MAC_CONFIG_DM_SHIFT (13U)
+/*! DM - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can
+ * transmit and receive simultaneously.
+ */
+#define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
+#define ENET_MAC_CONFIG_FES_MASK (0x4000U)
+#define ENET_MAC_CONFIG_FES_SHIFT (14U)
+/*! FES - Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by
+ * default and is enabled only when RMII/SMII is enabled during configuration.
+ */
+#define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
+#define ENET_MAC_CONFIG_PS_MASK (0x8000U)
+#define ENET_MAC_CONFIG_PS_SHIFT (15U)
+/*! PS - Portselect.
+ */
+#define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
+#define ENET_MAC_CONFIG_JE_MASK (0x10000U)
+#define ENET_MAC_CONFIG_JE_SHIFT (16U)
+/*! JE - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022
+ * bytes for tagged frames) without reporting a giant frame error in the receive frame status.
+ */
+#define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
+#define ENET_MAC_CONFIG_JD_MASK (0x20000U)
+#define ENET_MAC_CONFIG_JD_SHIFT (17U)
+/*! JD - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter,
+ * and can transfer frames of up to 16,384 bytes.
+ */
+#define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
+#define ENET_MAC_CONFIG_BE_MASK (0x40000U)
+#define ENET_MAC_CONFIG_BE_SHIFT (18U)
+/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
+ * transmission in the MII half-duplex mode.
+ */
+#define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
+#define ENET_MAC_CONFIG_WD_MASK (0x80000U)
+#define ENET_MAC_CONFIG_WD_SHIFT (19U)
+/*! WD - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver,
+ * and can receive frames of up to 16,384 bytes.
+ */
+#define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
+#define ENET_MAC_CONFIG_ACS_MASK (0x100000U)
+#define ENET_MAC_CONFIG_ACS_SHIFT (20U)
+/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
+ * on the incoming packets only if the value of the length field is less than 1,536 bytes.
+ */
+#define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
+#define ENET_MAC_CONFIG_CST_MASK (0x200000U)
+#define ENET_MAC_CONFIG_CST_SHIFT (21U)
+/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
+ * packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
+ * the packet to the application.
+ */
+#define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
+#define ENET_MAC_CONFIG_S2KP_MASK (0x400000U)
+#define ENET_MAC_CONFIG_S2KP_SHIFT (22U)
+/*! S2KP - IEEE 802.
+ */
+#define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
+#define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U)
+#define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U)
+/*! GPSLCE - Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the
+ * value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet.
+ */
+#define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
+#define ENET_MAC_CONFIG_IPG_MASK (0x7000000U)
+#define ENET_MAC_CONFIG_IPG_SHIFT (24U)
+/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
+ */
+#define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
+#define ENET_MAC_CONFIG_IPC_MASK (0x8000000U)
+#define ENET_MAC_CONFIG_IPC_SHIFT (27U)
+/*! IPC - Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or
+ * IPv6 TCP, UDP, or ICMP payload checksum checking.
+ */
+#define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
+/*! @} */
+
+/*! @name MAC_EXT_CONFIG - */
+/*! @{ */
+#define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU)
+#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U)
+/*! GPSL - Giant Packet Size Limit If the received packet size is greater than the value programmed
+ * in this field in units of bytes, the MAC declares the received packet as Giant packet.
+ */
+#define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
+#define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U)
+#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U)
+/*! DCRCC - Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does
+ * not check the CRC field in the received packets.
+ */
+#define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
+#define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U)
+#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U)
+/*! SPEN - Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol
+ * packets (Ether Type 0x8809) and provides the Rx status.
+ */
+#define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
+#define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U)
+#define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U)
+/*! USP - Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow
+ * Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and
+ * MAC Address Low Table 748 registers.
+ */
+#define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
+/*! @} */
+
+/*! @name MAC_FRAME_FILTER - MAC frame filter register */
+/*! @{ */
+#define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U)
+#define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U)
+/*! PR - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames
+ * regardless of its destination or source address.
+ */
+#define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
+#define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U)
+#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U)
+/*! DAIF - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse
+ * filtering mode for the DA address comparison for both unicast and multicast frames.
+ */
+#define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
+#define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U)
+#define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U)
+/*! PM - Pass All Multicast When set, this bit indicates that all received frames with a multicast
+ * destination address (first bit in the destination address field is '1') are passed.
+ */
+#define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
+#define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U)
+#define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U)
+/*! DBF - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames.
+ */
+#define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
+#define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U)
+#define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U)
+/*! PCF - Pass Control Frames These bits control the forwarding of all control frames (including
+ * unicast and multicast PAUSE frames).
+ */
+#define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
+#define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U)
+#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U)
+/*! SAIF - SA Inverse Filtering When this bit is set, the Address Check block operates in the
+ * inverse filtering mode for SA address comparison.
+ */
+#define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
+#define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U)
+#define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U)
+/*! SAF - Source Address Filter Enable When this bit is set, the MAC compares the SA field of the
+ * received packets with the values programmed in the enabled SA registers.
+ */
+#define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
+#define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U)
+#define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U)
+/*! RA - Receive all When this bit is set, the MAC Receiver module passes to the Application all
+ * frames received irrespective of whether they pass the address filter.
+ */
+#define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
+/*! @} */
+
+/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
+/*! @{ */
+#define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU)
+#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U)
+/*! WTO - Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register
+ * Table 722 is reset, this field is used as watchdog timeout for a received packet.
+ */
+#define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
+#define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U)
+#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U)
+/*! PWE - Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration
+ * register Table 722 is reset, the WTO field is used as watchdog timeout for a received packet.
+ */
+#define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
+/*! @} */
+
+/*! @name MAC_VLAN_TAG - MAC vlan tag register */
+/*! @{ */
+#define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU)
+#define ENET_MAC_VLAN_TAG_VL_SHIFT (0U)
+/*! VL - VLAN Tag Identifier for Receive Packets.
+ */
+#define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
+#define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U)
+#define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U)
+/*! ETV - Enable 12-Bit VLAN Tag Comparison.
+ */
+#define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
+#define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U)
+#define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U)
+/*! VTIM - VLAN Tag Inverse Match Enable.
+ */
+#define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
+#define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U)
+#define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U)
+/*! ESVL - Enable S-VLAN.
+ */
+#define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
+#define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U)
+#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)
+/*! ERSVLM - Enable Receive S-VLAN Match.
+ */
+#define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
+#define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U)
+#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)
+/*! DOVLTC - Disable VLAN Type Check.
+ */
+#define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
+#define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U)
+#define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U)
+/*! EVLS - Enable VLAN Tag Stripping on Receive.
+ */
+#define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
+#define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U)
+#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)
+/*! EVLRXS - Enable VLAN Tag in Rx status.
+ */
+#define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
+#define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U)
+#define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U)
+/*! VTHM - Disable VLAN Type Check.
+ */
+#define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
+#define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U)
+#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U)
+/*! EDVLP - Enable Double VLAN Processing.
+ */
+#define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
+#define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U)
+#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U)
+/*! ERIVLT - Enable Inner VLAN Tag.
+ */
+#define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
+#define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U)
+#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U)
+/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive.
+ */
+#define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
+#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U)
+#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U)
+/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status.
+ */
+#define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
+/*! @} */
+
+/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
+/*! @{ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U)
+/*! FCB - Flow Control Busy/Backpressure Activate This register field can be read by the application
+ * (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is
+ * cleared to 0 by the core (Self Clear).
+ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)
+/*! TFE - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables
+ * the flow control operation to transmit Pause frames.
+ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)
+/*! PLT - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the
+ * input flow control signal is checked for automatic retransmission of PAUSE Frame.
+ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)
+/*! DZPQ - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of
+ * Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer.
+ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)
+/*! PT - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame.
+ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
+/*! @} */
+
+/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
+#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U)
+
+/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
+/*! @{ */
+#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)
+#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
+/*! RFE - Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex
+ * mode, the MAC decodes the received Pause packet and disables its transmitter for a specified
+ * (Pause) time.
+ */
+#define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
+#define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)
+#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
+/*! UP - Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast
+ * address specified in the IEEE 802.
+ */
+#define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
+/*! @} */
+
+/*! @name MAC_TXQ_PRIO_MAP - */
+/*! @{ */
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U)
+/*! PSTQ0 - Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software.
+ */
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U)
+/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
+ */
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
+/*! @} */
+
+/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
+/*! @{ */
+#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)
+#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)
+/*! AVCPQ - AV Untagged Control Packets Queue.
+ */
+#define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)
+#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)
+/*! PSRQ0 - Priorities Selected in the Receive Queue 0.
+ */
+#define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)
+/*! RXQ0EN - Receive Queue 0 Enable.
+ */
+#define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)
+/*! RXQ1EN - Receive Queue 1 Enable.
+ */
+#define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U)
+/*! AVPTPQ - AV PTP Packets Queue.
+ */
+#define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)
+#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)
+/*! PSRQ1 - Priorities Selected in the Receive Queue 1.
+ */
+#define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
+#define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)
+#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U)
+/*! UPQ - Untagged Packet Queue.
+ */
+#define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)
+#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)
+/*! MCBCQ - Multicast and Broadcast Queue.
+ */
+#define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)
+#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)
+/*! PSRQ2 - Priorities Selected in the Receive Queue 2.
+ */
+#define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)
+/*! MCBCQEN - Multicast and Broadcast Queue Enable.
+ */
+#define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)
+#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)
+/*! PSRQ3 - Priorities Selected in the Receive Queue 3.
+ */
+#define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
+/*! @} */
+
+/* The count of ENET_MAC_RXQ_CTRL */
+#define ENET_MAC_RXQ_CTRL_COUNT (3U)
+
+/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
+/*! @{ */
+#define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U)
+#define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U)
+/*! PHYIS - PHY Interrupt.
+ */
+#define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
+#define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U)
+#define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U)
+/*! PMTIS - PMT Interrupt Status.
+ */
+#define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
+#define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U)
+#define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U)
+/*! LPIIS - LPI Interrupt Status.
+ */
+#define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
+#define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U)
+#define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U)
+/*! TSIS - Timestamp interrupt status.
+ */
+#define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
+#define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U)
+#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U)
+/*! TXSTSIS - Transmit Status Interrupt.
+ */
+#define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
+#define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U)
+#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U)
+/*! RXSTSIS - Receive Status Interrupt.
+ */
+#define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
+/*! @} */
+
+/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
+/*! @{ */
+#define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U)
+#define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U)
+/*! PHYIE - PHY Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
+#define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U)
+#define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U)
+/*! PMTIE - PMT Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
+#define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U)
+#define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U)
+/*! LPIIE - LPI Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
+#define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U)
+#define ENET_MAC_INTR_EN_TSIE_SHIFT (12U)
+/*! TSIE - Timestamp Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
+#define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U)
+#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U)
+/*! TXSTSIE - Transmit Status Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
+#define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U)
+#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U)
+/*! RXSTSIS - Receive Status Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
+/*! @} */
+
+/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
+/*! @{ */
+#define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U)
+#define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U)
+/*! TJT - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
+ * signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731.
+ */
+#define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
+#define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U)
+#define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U)
+/*! NCARR - No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this
+ * bit indicates that the carrier signal from the PHY is not present at the end of preamble
+ * transmission.
+ */
+#define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
+#define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U)
+#define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U)
+/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
+ * this bit indicates that the loss of carrier occurred during packet transmission, that is, the
+ * PHY Carrier signal was inactive for one or more transmission clock periods during packet
+ * transmission.
+ */
+#define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
+#define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U)
+#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U)
+/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table
+ * 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that
+ * the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when
+ * Jumbo packet is enabled).
+ */
+#define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
+#define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U)
+#define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U)
+/*! LCOL - Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
+ * this bit indicates that the packet transmission aborted because a collision occurred after the
+ * collision window (64 bytes including Preamble in MII mode).
+ */
+#define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
+#define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U)
+#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U)
+/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table
+ * 758, this bit indicates that the transmission aborted after 16 successive collisions while
+ * attempting to transmit the current packet.
+ */
+#define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
+#define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U)
+#define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U)
+/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
+ * bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
+ * MAC Configuration register Table 722.
+ */
+#define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
+/*! @} */
+
+/*! @name MAC_PMT_CRTL_STAT - */
+/*! @{ */
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U)
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U)
+/*! PWRDWN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
+ * entered the LPI state because of the setting of the LPIEN bit.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U)
+/*! MGKPKTEN - Magic Packet Enable.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U)
+/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
+ * generated when the MAC receives a remote wake-up packet.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U)
+/*! MGKPRCVD - Magic Packet Received.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U)
+/*! RWKPRCVD - Remote Wake-Up Packet Received.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U)
+/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
+ * address recognition is detected as a remote wake-up packet.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U)
+/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
+ * MAC receiver drops all received frames until it receives the expected wake-up frame.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U)
+/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote
+ * Wake-up Packet Filter register pointer.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U)
+/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
+ * remote wake-up packet filter register pointer is reset to 3'b000.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
+/*! @} */
+
+/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
+/*! @{ */
+#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU)
+#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U)
+/*! ADDR - WKUPFMFILTER address.
+ */
+#define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
+/*! @} */
+
+/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
+/*! @{ */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U)
+/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
+ * entered the LPI state because of the setting of the LPIEN bit.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U)
+/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
+ * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U)
+/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
+ * an LPI pattern and entered the LPI state.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U)
+/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
+ * receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal
+ * reception.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U)
+/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U)
+/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U)
+/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U)
+#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U)
+/*! PLS - PHY Link Status This bit indicates the link status of the PHY.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U)
+/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
+ * out of the LPI mode on the Transmit side.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U)
+/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U)
+/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts LPI Tx Clock Gating
+ * Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be
+ * stopped.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
+/*! @} */
+
+/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
+/*! @{ */
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU)
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U)
+/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
+ * waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
+ * transmission.
+ */
+#define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
+#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U)
+#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U)
+/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
+ * status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
+ */
+#define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
+/*! @} */
+
+/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
+/*! @{ */
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U)
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U)
+/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter
+ * LPI mode, after it has transmitted all the frames.
+ */
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
+/*! @} */
+
+/*! @name MAC_1US_TIC_COUNTR - */
+/*! @{ */
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
+/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
+ */
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
+/*! @} */
+
+/*! @name MAC_VERSION - MAC version register */
+/*! @{ */
+#define ENET_MAC_VERSION_SNPVER_MASK (0xFFU)
+#define ENET_MAC_VERSION_SNPVER_SHIFT (0U)
+/*! SNPVER - NXP defined version.
+ */
+#define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
+#define ENET_MAC_VERSION_USERVER_MASK (0xFF00U)
+#define ENET_MAC_VERSION_USERVER_SHIFT (8U)
+/*! USERVER - User defined version.
+ */
+#define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
+/*! @} */
+
+/*! @name MAC_DBG - MAC debug register */
+/*! @{ */
+#define ENET_MAC_DBG_REPESTS_MASK (0x1U)
+#define ENET_MAC_DBG_REPESTS_SHIFT (0U)
+/*! REPESTS - MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC
+ * MII receive protocol engine is actively receiving data, and it is not in the Idle state.
+ */
+#define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
+#define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U)
+#define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U)
+/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
+ * the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
+ * Controller module.
+ */
+#define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
+#define ENET_MAC_DBG_TPESTS_MASK (0x10000U)
+#define ENET_MAC_DBG_TPESTS_SHIFT (16U)
+/*! TPESTS - MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC
+ * or MII transmit protocol engine is actively transmitting data, and it is not in the Idle
+ * state.
+ */
+#define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
+#define ENET_MAC_DBG_TFCSTS_MASK (0x60000U)
+#define ENET_MAC_DBG_TFCSTS_SHIFT (17U)
+/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
+ */
+#define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
+/*! @} */
+
+/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
+/*! @{ */
+#define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U)
+#define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U)
+/*! MIISEL - 10 or 100 Mbps Support.
+ */
+#define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)
+/*! RXFIFOSIZE - MTL Receive FIFO Size.
+ */
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
+#define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU)
+#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U)
+/*! RXQCNT - Number of MTL Receive Queues.
+ */
+#define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
+#define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U)
+#define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U)
+/*! HDSEL - Half-duplex Support.
+ */
+#define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
+#define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U)
+#define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U)
+/*! VLHASH - Hash Table Based Filtering option.
+ */
+#define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
+#define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U)
+#define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U)
+/*! SMASEL - SMA (MDIO) Interface.
+ */
+#define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
+#define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U)
+#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U)
+/*! RWKSEL - PMT Remote Wake-up Packet Detection.
+ */
+#define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)
+/*! TXFIFOSIZE - MTL Transmit FIFO Size.
+ */
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
+#define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)
+#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U)
+/*! TXQCNT - Number of MTL Transmit Queues.
+ */
+#define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
+#define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U)
+#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U)
+/*! MGKSEL - PMT magic packet detection.
+ */
+#define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
+#define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U)
+#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U)
+/*! MMCSEL - RMON Module Enable.
+ */
+#define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)
+/*! ARPOFFSEL - ARP Offload Enabled.
+ */
+#define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
+#define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U)
+#define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U)
+/*! OSTEN - One-Step Timestamping Feature.
+ */
+#define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
+#define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U)
+#define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U)
+/*! PTOEN - PTP OffLoad Feature.
+ */
+#define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
+#define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)
+#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)
+/*! RXCHCNT - Number of DMA Receive Channels.
+ */
+#define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
+#define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U)
+#define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U)
+/*! TSSEL - IEEE 1588-2008 Timestamp support .
+ */
+#define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
+#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)
+#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)
+/*! ADVTHWORD - IEEE 1588 High Word Register Feature.
+ */
+#define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
+#define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U)
+#define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U)
+/*! EEESEL - Energy Efficient Ethernet Support .
+ */
+#define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
+#define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U)
+#define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U)
+/*! ADDR64 - Address width.
+ */
+#define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
+#define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)
+#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)
+/*! TXCOESEL - Transmit Checksum Offload Support.
+ */
+#define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
+#define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U)
+#define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U)
+/*! DCBEN - Data Center Bridging feature.
+ */
+#define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
+#define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)
+#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)
+/*! RXCOESEL - Receive Checksum Offload Support.
+ */
+#define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
+#define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U)
+#define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U)
+/*! SPEN - Split Header Structure feature.
+ */
+#define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
+#define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U)
+#define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U)
+/*! TSOEN - TCP Segment Offload Feature.
+ */
+#define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
+#define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)
+#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)
+/*! TXCHCNT - Number of DMA Transmit Channels.
+ */
+#define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
+#define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)
+#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)
+/*! DBGMEMA - DMA Debug Register Feature.
+ */
+#define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
+#define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U)
+#define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U)
+/*! AVSEL - Audio Video Bridging Feature.
+ */
+#define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
+#define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U)
+#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U)
+/*! LPMODEEN - Low Power Mode Feature Support .
+ */
+#define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)
+/*! HASHTBLSZ - Hash Table Size.
+ */
+#define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)
+/*! PPSOUTNUM - Number of PPS Outputs.
+ */
+#define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
+#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)
+#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)
+/*! TSSTSSEL - Timestamp System Time Source.
+ */
+#define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U)
+/*! L3_L4_FILTER - Total Number of L3 and L4 Filters .
+ */
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)
+/*! ACTPHYSEL - Active PHY Selected.
+ */
+#define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)
+/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs.
+ */
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
+/*! @} */
+
+/* The count of ENET_MAC_HW_FEAT */
+#define ENET_MAC_HW_FEAT_COUNT (3U)
+
+/*! @name MAC_MDIO_ADDR - MIDO address Register */
+/*! @{ */
+#define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U)
+#define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U)
+/*! MB - MII busy.
+ */
+#define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
+#define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU)
+#define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U)
+/*! MOC - MII Operation Command.
+ */
+#define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
+#define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U)
+#define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U)
+/*! CR - CSR Clock Range.
+ */
+#define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
+#define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U)
+#define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U)
+/*! NTC - Number of Training Clocks This field controls the number of trailing clock cycles
+ * generated on MDC after the end of transmission of MDIO frame.
+ */
+#define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
+#define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U)
+#define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U)
+/*! RDA - Register/Device Address These bits select the PHY register in selected PHY device.
+ */
+#define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
+#define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U)
+#define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U)
+/*! PA - Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing.
+ */
+#define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
+#define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U)
+#define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U)
+/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
+ * the MAC will inform the completion of a read or write command at the end of frame transfer
+ * (before the trailing clocks are transmitted).
+ */
+#define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
+#define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U)
+#define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U)
+/*! PSE - Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit
+ * preamble and transmit MDIO frames with only 1 preamble bit.
+ */
+#define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
+/*! @} */
+
+/*! @name MAC_MDIO_DATA - MDIO Data register */
+/*! @{ */
+#define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU)
+#define ENET_MAC_MDIO_DATA_MD_SHIFT (0U)
+/*! MD - MII Data This field contains the 16-bit data value read from the PHY after a Management
+ * Read operation or the 16-bit data value to be written to the PHY before a Management Write
+ * operation.
+ */
+#define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
+/*! @} */
+
+/*! @name MAC_ADDR_HIGH - MAC address0 high register */
+/*! @{ */
+#define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU)
+#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U)
+/*! A47_32 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address.
+ */
+#define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
+#define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U)
+#define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U)
+/*! DCS - DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose
+ * DA matches the MAC Address content is routed.
+ */
+#define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
+#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U)
+#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U)
+/*! AE - Address Enable.
+ */
+#define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
+/*! @} */
+
+/*! @name MAC_ADDR_LOW - MAC address0 low register */
+/*! @{ */
+#define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU)
+#define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U)
+/*! A31_0 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address.
+ */
+#define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
+/*! @} */
+
+/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
+/*! @{ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U)
+/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U)
+/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U)
+/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
+ * with the value specified in the MAC Register 80 (System Time Seconds Update.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U)
+/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
+ * with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time
+ * Nanoseconds Update Table 754.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U)
+/*! TSTRIG - Enable Timestamp Interrupt Trigger When this bit is set, the timestamp interrupt is
+ * generated when the System Time becomes greater than the value written in the Target Time register.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U)
+/*! TADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
+ * register is updated in the PTP block for fine correction.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U)
+/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
+ * enabled for all packets received by the MAC.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U)
+/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
+ * register rolls over after 0x3B9AC9FF value (that is, 1 nanosecond accuracy) and increments
+ * the timestamp (High) seconds.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U)
+/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
+ * 1588 version 2 format is used to process the PTP packets.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U)
+/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
+ * processes the PTP packets encapsulated directly in the Ethernet packets.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U)
+/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set, the MAC
+ * receiver processes the PTP packets encapsulated in IPv6-UDP packets.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U)
+/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
+ * receiver processes the PTP packets encapsulated in IPv4-UDP packets.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U)
+/*! TSEVTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
+ * snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U)
+/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
+ * is taken only for the messages that are relevant to the master node.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
+/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
+ * decide the set of PTP packet types for which snapshot needs to be taken.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
+/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
+ * address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
+ * directly sent over Ethernet.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U)
+/*! TXTTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
+ * transmit timestamp status even if it is not read by the software.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
+/*! AV8021ASMEN - AV 802.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
+/*! @} */
+
+/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
+/*! @{ */
+#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U)
+#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U)
+/*! SSINC - Sub-second increment value.
+ */
+#define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIME_SCND - System time seconds register */
+/*! @{ */
+#define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U)
+/*! TSS - Time stamp second The value in this field indicates the current value in seconds of the
+ * System Time maintained by the MAC.
+ */
+#define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
+/*! @{ */
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU)
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U)
+/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
+ */
+#define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIME_SCND_UPD - */
+/*! @{ */
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U)
+/*! TSS - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time.
+ */
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIME_NSCND_UPD - */
+/*! @{ */
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U)
+/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
+ */
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
+/*! ADDSUB - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register.
+ */
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
+/*! @{ */
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U)
+/*! TSAR - Time stamp addend This register indicates the 32-bit time value to be added to the
+ * Accumulator register to achieve time synchronization.
+ */
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIME_HWORD_SCND - */
+/*! @{ */
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU)
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
+/*! TSHWR - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value.
+ */
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
+/*! @{ */
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U)
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U)
+/*! TSSOVF - Time stamp seconds overflow When set, indicates that the seconds value of the Time
+ * stamp has overflowed beyond 0xFFFF_FFFF.
+ */
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
+/*! @} */
+
+/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
+/*! @{ */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
+/*! TXTSSTSLO - Transmit timestamp status low.
+ */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
+/*! TXTSSTSMIS - Transmit timestamp status missed.
+ */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
+/*! @} */
+
+/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
+/*! @{ */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
+/*! TXTSSTSHI - Transmit timestamp status high.
+ */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
+/*! @} */
+
+/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
+/*! @{ */
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
+/*! TSIC - Transmit ingress correction.
+ */
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
+/*! @} */
+
+/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
+/*! @{ */
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
+/*! TSEC - Transmit egress correction.
+ */
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
+/*! @} */
+
+/*! @name MTL_OP_MODE - MTL Operation Mode Register */
+/*! @{ */
+#define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U)
+#define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U)
+/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
+ */
+#define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
+#define ENET_MTL_OP_MODE_RAA_MASK (0x4U)
+#define ENET_MTL_OP_MODE_RAA_SHIFT (2U)
+/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
+ */
+#define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
+#define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U)
+#define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U)
+/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR
+ * algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm.
+ */
+#define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
+#define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U)
+#define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U)
+/*! CNTPRST - Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and
+ * MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0.
+ */
+#define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
+#define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U)
+#define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U)
+/*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
+ */
+#define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
+/*! @} */
+
+/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
+/*! @{ */
+#define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U)
+#define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U)
+/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
+ */
+#define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
+#define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U)
+#define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U)
+/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
+ */
+#define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
+/*! @} */
+
+/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
+/*! @{ */
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U)
+/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
+ * in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
+ * Q0DDMACH field is reset.
+ */
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U)
+/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
+ * the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
+ * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
+ * Ethernet DA address.
+ */
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U)
+/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
+ * in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
+ * Q1DDMACH field is reset.
+ */
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U)
+/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
+ * the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
+ * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
+ * Ethernet DA address.
+ */
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
+/*! @} */
+
+/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
+/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
+/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
+/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
+/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
+/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
+/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
+ * controller because of Tx Queue Underflow.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
+/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
+ * Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
+/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
+ * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
+ * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
+ * when PFC is enabled - Reception of 802.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
+/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read
+ * Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10:
+ * Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the
+ * Packet Abort request from the MAC.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
+/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
+ * Queue Write Controller is active, and it is transferring the data to the Tx Queue.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
+/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
+ * is not empty and some data is left for transmission.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
+/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U)
+/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
+/*! STSXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
+ * number of status in the Tx Status FIFO of this queue.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
+/*! AVALG - AV Algorithm.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
+/*! CC - Credit Control.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
+/*! SLC - Credit Control.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
+/*! ABS - Average Bits per Slot.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
+/*! ISCQW - Average Bits per Slot.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
+/*! SSC - sendSlopeCredit.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
+/*! HC - hiCredit.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
+/*! LC - loCredit.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
+/*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
+ * had an underflow while transmitting the packet.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
+/*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
+/*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
+/*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
+ * interrupt when the average bits per slot status is updated.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
+/*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
+ * an overflow while receiving the packet.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
+/*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
+/*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
+ * (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the
+ * application or DMA when the packet size within the MTL Rx queue is larger than the threshold.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
+/*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
+ * good packets (packets with no error and length less than 64 bytes), including pad-bytes and
+ * CRC.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
+/*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
+ * (CRC error, Mll_ER, watchdog timeout, or overflow).
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
+/*! RSF - Receive Queue Store and Forward When this bit is set, the ethernet block on this chip
+ * reads a packet from the Rx queue only after the complete packet has been written to it, ignoring
+ * the RTC field of this register.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
+/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
+ * does not drop the packets which only have the errors detected by the Receive Checksum Offload
+ * engine.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
+/*! RQS - This field indicates the size of the allocated Receive queues in blocks of 256 bytes.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
+/*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
+ * Ethernet block because of Receive queue overflow.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
+/*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
+ * Overflow Packet Counter field crossed the maximum limit.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
+/*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
+ * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
+/*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read
+ * controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11:
+ * Flushing the packet data and status.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
+/*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx
+ * Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold
+ * 0x2: Rx Queue fill-level above flow-control activate threshold 0x3: Rx Queue full.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U)
+/*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
+/*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
+/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the The ethernet block
+ * drives the packet data to the ARI interface such that the entire packet data of
+ * currently-selected queue is transmitted before switching to other queue.
+ */
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U)
+
+/*! @name DMA_MODE - DMA mode register */
+/*! @{ */
+#define ENET_DMA_MODE_SWR_MASK (0x1U)
+#define ENET_DMA_MODE_SWR_SHIFT (0U)
+/*! SWR - Software Reset When this bit is set, the MAC and the OMA controller reset the logic and
+ * all internal registers of the OMA, MTL, and MAC.
+ */
+#define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
+#define ENET_DMA_MODE_DA_MASK (0x2U)
+#define ENET_DMA_MODE_DA_SHIFT (1U)
+/*! DA - DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the
+ * Transmit and Receive paths of all channels: The Tx path has priority over the Rx path when the TXPR
+ * bit is set.
+ */
+#define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
+#define ENET_DMA_MODE_TAA_MASK (0x1CU)
+#define ENET_DMA_MODE_TAA_SHIFT (2U)
+/*! TAA - Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for
+ * the Transmit side when multiple Tx DMAs are selected.
+ */
+#define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
+#define ENET_DMA_MODE_TXPR_MASK (0x800U)
+#define ENET_DMA_MODE_TXPR_SHIFT (11U)
+/*! TXPR - Transmit Priority When set, this bit indicates that the Tx DMA has higher priority than
+ * the Rx DMA during arbitration for the system-side bus.
+ */
+#define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
+#define ENET_DMA_MODE_PR_MASK (0x7000U)
+#define ENET_DMA_MODE_PR_SHIFT (12U)
+/*! PR - Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA.
+ */
+#define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
+/*! @} */
+
+/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
+/*! @{ */
+#define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U)
+#define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U)
+/*! FB - Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers
+ * of specified length (INCRx or SINGLE).
+ */
+#define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
+#define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)
+#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
+/*! AAL - Address-Aligned Beats When this bit is set to 1, the AHB master performs address-aligned
+ * burst transfers on Read and Write channels.
+ */
+#define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
+#define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U)
+#define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U)
+/*! MB - Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs
+ * undefined bursts transfers (INCR) for burst length of 16 or more.
+ */
+#define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
+#define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U)
+#define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U)
+/*! RB - Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or
+ * EarlyBurst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any
+ * initiated burst transfer with INCRx and SINGLEtransfers.
+ */
+#define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
+/*! @} */
+
+/*! @name DMA_INTR_STAT - DMA Interrupt status */
+/*! @{ */
+#define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U)
+#define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U)
+/*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
+ */
+#define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
+#define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U)
+#define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U)
+/*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
+ */
+#define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
+#define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U)
+#define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U)
+/*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
+ */
+#define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
+#define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U)
+#define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U)
+/*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
+ */
+#define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
+/*! @} */
+
+/*! @name DMA_DBG_STAT - DMA Debug Status */
+/*! @{ */
+#define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U)
+#define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U)
+/*! AHSTS - AHB Master Status When high, this bit indicates that the AHB master FSMs are in the non-idle state.
+ */
+#define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
+#define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U)
+#define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U)
+/*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel
+ * 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer )
+ * 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended (Rx Unavailable) 0x5: Running
+ * (Closing the Rx) 0x6: Timestamp write state 0x7: Running (Transferring the received packet
+ * data from the Rx buffer to the system memory) This field does not generate an interrupt.
+ */
+#define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
+#define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U)
+#define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U)
+/*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for
+ * Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer)
+ * 0x2: Running (Waiting for status) 0x3: Running (Reading Data from system memory buffer and
+ * queuing it to the Tx buffer (Tx FIFO)) 0x4: Timestamp write state 0x5: Reserved for future use
+ * 0x6: Suspended (Tx Unavailable or Tx Buffer Underflow) 0x7: Running (Closing Tx ) This field
+ * does not generate an interrupt.
+ */
+#define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
+#define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U)
+#define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U)
+/*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
+ */
+#define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
+#define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U)
+#define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U)
+/*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
+ */
+#define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
+/*! @} */
+
+/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U)
+/*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA Channel
+ * Transmit Control Table 780 is multiplied eight times.
+ */
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U)
+/*! DSL - Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32- bit,
+ * 64-bit, or 128-bit bus) to skip between two unchained s.
+ */
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U)
+/*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
+ */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U)
+/*! TCW - Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel.
+ */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)
+/*! OSF - Operate on Second Frame When this bit is set, it instructs the DMA to process the second
+ * packet of the Transmit data even before the status for the first packet is obtained.
+ */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)
+/*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
+ * transferred in one DMA data transfer.
+ */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U)
+/*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the from the receive
+ * list and processes the incoming packets.
+ */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U)
+/*! RBSZ - Receive Buffer size This field indicates the size of the Rx buffers specified in bytes.
+ */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)
+/*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
+ * transferred in one DMA data transfer.
+ */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)
+/*! RPF - DMA Rx Channel 0 Packet Flush When this bit is set to 1, the DMA will automatically flush
+ * the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is
+ * stopped after a system bus error has occurred.
+ */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
+/*! STL - Start of transmit list This field contains the base address of the first in the Transmit list.
+ */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
+/*! SRL - Start of receive list This field contains the base address of the First in the Receive list.
+ */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
+/*! TDTP - Transmit Tail Pointer This field contains the tail pointer for the Tx ring.
+ */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
+/*! RDTP - Receive Tail Pointer This field contains the tail pointer for the Rx ring.
+ */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
+/*! TDRL - Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring.
+ */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
+/*! RDRL - Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring.
+ */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U)
+/*! TIE - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit
+ * 16 in this register), Transmit Interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U)
+/*! TSE - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
+ * 15 in this register), Transmission Stopped Interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U)
+/*! TBUE - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary
+ * Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U)
+/*! RIE - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16
+ * in this register), Receive Interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U)
+/*! RBUE - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary
+ * Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U)
+/*! RSE - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
+ * 15 in this register), Receive Stopped Interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U)
+/*! RWTE - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary
+ * Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U)
+/*! ETIE - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary
+ * Enable (bit 15 in this register), Early Transmit Interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U)
+/*! ERIE - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable
+ * (bit 16 in this register), Early Receive Interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U)
+/*! FBEE - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit
+ * 15 in this register), the Fatal Bus Error Interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U)
+/*! AIE - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt summary is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U)
+/*! NIE - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled.
+ */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)
+/*! RIWT - Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles
+ * multiplied by 256 for which the watchdog timer is set.
+ */
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
+/*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
+ * programmed in the Tx descriptor with the current reference given in the RSN field.
+ */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
+/*! ASC - Advance Slot Check When set, this bit enables the D MA to fetch the data from the buffer
+ * when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot
+ * number given in the RSN field or, ahead of the reference slot number by up to two slots This
+ * bit is applicable only when the ESC bit is set.
+ */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
+/*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA.
+ */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)
+/*! HTD - Host Transmit descriptor Address Pointer Cleared on Reset.
+ */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)
+/*! HRD - Host Receive descriptor Address Pointer Cleared on Reset.
+ */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)
+/*! HTB - Host Transmit Buffer Address Pointer Cleared on Reset.
+ */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)
+/*! HRB - Host Receive Buffer Address Pointer Cleared on Reset.
+ */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U)
+/*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U)
+/*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U)
+/*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
+ * descriptor in the transmit list, and the DMA cannot acquire it.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U)
+/*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U)
+/*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next in the
+ * receive list, and the DMA cannot acquire it.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U)
+/*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U)
+/*! RWT - Receive Watchdog time out This bit is asserted when a packet with length greater than
+ * 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U)
+/*! ETI - Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U)
+/*! ERI - Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U)
+/*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U)
+/*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
+ * following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable
+ * register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8:
+ * Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked
+ * bits affect the Abnormal Interrupt Summary bit.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U)
+/*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
+ * following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt
+ * Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6:
+ * Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which
+ * interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal
+ * Interrupt Summary bit.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U)
+/*! EB - DMA Error Bits This field indicates the type of error that caused a Bus Error.
+ */
+#define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_STAT */
+#define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_MISS_FRAME_CNT - Channelx missed frame count. */
+/*! @{ */
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
+/*! MFC - Dropped packet counters.
+ */
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
+/*! MFCO - Overflow status of the MFC counter.
+ */
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
+/*! @} */
+
+/* The count of ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT */
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_COUNT (2U)
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE (0x40092000u)
+/** Peripheral ENET base pointer */
+#define ENET ((ENET_Type *)ENET_BASE)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_IRQS { ETHERNET_IRQn }
+#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn }
+#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLEXCOMM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXCOMM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[4088];
+ __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
+ __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
+} FLEXCOMM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FLEXCOMM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
+ * @{
+ */
+
+/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
+/*! @{ */
+#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
+#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
+/*! PERSEL - Peripheral Select. This field is writable by software.
+ * 0b000..No peripheral selected.
+ * 0b001..USART function selected.
+ * 0b010..SPI function selected.
+ * 0b011..I2C function selected.
+ * 0b100..I2S transmit function selected.
+ * 0b101..I2S receive function selected.
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
+#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
+#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
+/*! LOCK - Lock the peripheral select. This field is writable by software.
+ * 0b0..Peripheral select can be changed by software.
+ * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.
+ */
+#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
+/*! USARTPRESENT - USART present indicator. This field is Read-only.
+ * 0b0..This Flexcomm does not include the USART function.
+ * 0b1..This Flexcomm includes the USART function.
+ */
+#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
+/*! SPIPRESENT - SPI present indicator. This field is Read-only.
+ * 0b0..This Flexcomm does not include the SPI function.
+ * 0b1..This Flexcomm includes the SPI function.
+ */
+#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
+/*! I2CPRESENT - I2C present indicator. This field is Read-only.
+ * 0b0..This Flexcomm does not include the I2C function.
+ * 0b1..This Flexcomm includes the I2C function.
+ */
+#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
+/*! I2SPRESENT - I 2S present indicator. This field is Read-only.
+ * 0b0..This Flexcomm does not include the I2S function.
+ * 0b1..This Flexcomm includes the I2S function.
+ */
+#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
+#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
+#define FLEXCOMM_PSELID_ID_SHIFT (12U)
+/*! ID - Flexcomm ID.
+ */
+#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
+/*! @} */
+
+/*! @name PID - Peripheral identification register. */
+/*! @{ */
+#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)
+#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)
+/*! Minor_Rev - Minor revision of module implementation.
+ */
+#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
+#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)
+#define FLEXCOMM_PID_Major_Rev_SHIFT (12U)
+/*! Major_Rev - Major revision of module implementation.
+ */
+#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
+#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
+#define FLEXCOMM_PID_ID_SHIFT (16U)
+/*! ID - Module identifier for the selected function.
+ */
+#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Register_Masks */
+
+
+/* FLEXCOMM - Peripheral instance base addresses */
+/** Peripheral FLEXCOMM0 base address */
+#define FLEXCOMM0_BASE (0x40086000u)
+/** Peripheral FLEXCOMM0 base pointer */
+#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+/** Peripheral FLEXCOMM1 base address */
+#define FLEXCOMM1_BASE (0x40087000u)
+/** Peripheral FLEXCOMM1 base pointer */
+#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+/** Peripheral FLEXCOMM2 base address */
+#define FLEXCOMM2_BASE (0x40088000u)
+/** Peripheral FLEXCOMM2 base pointer */
+#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+/** Peripheral FLEXCOMM3 base address */
+#define FLEXCOMM3_BASE (0x40089000u)
+/** Peripheral FLEXCOMM3 base pointer */
+#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+/** Peripheral FLEXCOMM4 base address */
+#define FLEXCOMM4_BASE (0x4008A000u)
+/** Peripheral FLEXCOMM4 base pointer */
+#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+/** Peripheral FLEXCOMM5 base address */
+#define FLEXCOMM5_BASE (0x40096000u)
+/** Peripheral FLEXCOMM5 base pointer */
+#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+/** Peripheral FLEXCOMM6 base address */
+#define FLEXCOMM6_BASE (0x40097000u)
+/** Peripheral FLEXCOMM6 base pointer */
+#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+/** Peripheral FLEXCOMM7 base address */
+#define FLEXCOMM7_BASE (0x40098000u)
+/** Peripheral FLEXCOMM7 base pointer */
+#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+/** Peripheral FLEXCOMM8 base address */
+#define FLEXCOMM8_BASE (0x40099000u)
+/** Peripheral FLEXCOMM8 base pointer */
+#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
+/** Peripheral FLEXCOMM9 base address */
+#define FLEXCOMM9_BASE (0x4009A000u)
+/** Peripheral FLEXCOMM9 base pointer */
+#define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
+/** Peripheral FLEXCOMM10 base address */
+#define FLEXCOMM10_BASE (0x4009F000u)
+/** Peripheral FLEXCOMM10 base pointer */
+#define FLEXCOMM10 ((FLEXCOMM_Type *)FLEXCOMM10_BASE)
+/** Array initializer of FLEXCOMM peripheral base addresses */
+#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE }
+/** Array initializer of FLEXCOMM peripheral base pointers */
+#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10 }
+/** Interrupt vectors for the FLEXCOMM peripheral type */
+#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GINT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
+ * @{
+ */
+
+/** GINT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
+} GINT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GINT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Register_Masks GINT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - GPIO grouped interrupt control register */
+/*! @{ */
+#define GINT_CTRL_INT_MASK (0x1U)
+#define GINT_CTRL_INT_SHIFT (0U)
+/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
+ * 0b0..No request. No interrupt request is pending.
+ * 0b1..Request active. Interrupt request is active.
+ */
+#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
+#define GINT_CTRL_COMB_MASK (0x2U)
+#define GINT_CTRL_COMB_SHIFT (1U)
+/*! COMB - Combine enabled inputs for group interrupt
+ * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
+ * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
+ */
+#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
+#define GINT_CTRL_TRIG_MASK (0x4U)
+#define GINT_CTRL_TRIG_SHIFT (2U)
+/*! TRIG - Group interrupt trigger
+ * 0b0..Edge-triggered.
+ * 0b1..Level-triggered.
+ */
+#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
+/*! @} */
+
+/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
+/*! @{ */
+#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)
+#define GINT_PORT_POL_POL_SHIFT (0U)
+/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n
+ * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to
+ * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin
+ * contributes to the group interrupt.
+ */
+#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
+/*! @} */
+
+/* The count of GINT_PORT_POL */
+#define GINT_PORT_POL_COUNT (2U)
+
+/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
+/*! @{ */
+#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)
+#define GINT_PORT_ENA_ENA_SHIFT (0U)
+/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the
+ * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is
+ * enabled and contributes to the grouped interrupt.
+ */
+#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
+/*! @} */
+
+/* The count of GINT_PORT_ENA */
+#define GINT_PORT_ENA_COUNT (2U)
+
+
+/*!
+ * @}
+ */ /* end of group GINT_Register_Masks */
+
+
+/* GINT - Peripheral instance base addresses */
+/** Peripheral GINT0 base address */
+#define GINT0_BASE (0x40002000u)
+/** Peripheral GINT0 base pointer */
+#define GINT0 ((GINT_Type *)GINT0_BASE)
+/** Peripheral GINT1 base address */
+#define GINT1_BASE (0x40003000u)
+/** Peripheral GINT1 base pointer */
+#define GINT1 ((GINT_Type *)GINT1_BASE)
+/** Array initializer of GINT peripheral base addresses */
+#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }
+/** Array initializer of GINT peripheral base pointers */
+#define GINT_BASE_PTRS { GINT0, GINT1 }
+/** Interrupt vectors for the GINT peripheral type */
+#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group GINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
+ uint8_t RESERVED_0[3904];
+ __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
+ uint8_t RESERVED_1[3328];
+ __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
+ uint8_t RESERVED_2[104];
+ __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
+ uint8_t RESERVED_3[104];
+ __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
+ uint8_t RESERVED_4[104];
+ __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
+ uint8_t RESERVED_5[104];
+ __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
+ uint8_t RESERVED_6[104];
+ __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
+ uint8_t RESERVED_7[104];
+ __O uint32_t NOT[6]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
+ uint8_t RESERVED_8[104];
+ __O uint32_t DIRSET[6]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
+ uint8_t RESERVED_9[104];
+ __O uint32_t DIRCLR[6]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
+ uint8_t RESERVED_10[104];
+ __O uint32_t DIRNOT[6]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
+/*! @{ */
+#define GPIO_B_PBYTE_MASK (0x1U)
+#define GPIO_B_PBYTE_SHIFT (0U)
+/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
+ * except that pins configured as analog I/O always read as 0. One register for each port pin.
+ * Supported pins depends on the specific device and package. Write: loads the pin's output bit.
+ * One register for each port pin. Supported pins depends on the specific device and package.
+ */
+#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
+/*! @} */
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT (6U)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT2 (32U)
+
+/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
+/*! @{ */
+#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
+#define GPIO_W_PWORD_SHIFT (0U)
+/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
+ * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
+ * read. Writing any value other than 0 will set the output bit. One register for each port pin.
+ * Supported pins depends on the specific device and package.
+ */
+#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
+/*! @} */
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT (6U)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT2 (32U)
+
+/*! @name DIR - Direction registers */
+/*! @{ */
+#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)
+#define GPIO_DIR_DIRP_SHIFT (0U)
+/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
+ * pins depends on the specific device and package. 0 = input. 1 = output.
+ */
+#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIR */
+#define GPIO_DIR_COUNT (6U)
+
+/*! @name MASK - Mask register */
+/*! @{ */
+#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)
+#define GPIO_MASK_MASKP_SHIFT (0U)
+/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
+ * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
+ * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
+ * not affected.
+ */
+#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
+/*! @} */
+
+/* The count of GPIO_MASK */
+#define GPIO_MASK_COUNT (6U)
+
+/*! @name PIN - Port pin register */
+/*! @{ */
+#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)
+#define GPIO_PIN_PORT_SHIFT (0U)
+/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
+ * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
+ * 1 = Read: pin is high; write: set output bit.
+ */
+#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
+/*! @} */
+
+/* The count of GPIO_PIN */
+#define GPIO_PIN_COUNT (6U)
+
+/*! @name MPIN - Masked port register */
+/*! @{ */
+#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)
+#define GPIO_MPIN_MPORTP_SHIFT (0U)
+/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
+ * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
+ * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
+ * if the corresponding bit in the MASK register is 0.
+ */
+#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
+/*! @} */
+
+/* The count of GPIO_MPIN */
+#define GPIO_MPIN_COUNT (6U)
+
+/*! @name SET - Write: Set register for port Read: output bits for port */
+/*! @{ */
+#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
+#define GPIO_SET_SETP_SHIFT (0U)
+/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
+ * bit; write: set output bit.
+ */
+#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
+/*! @} */
+
+/* The count of GPIO_SET */
+#define GPIO_SET_COUNT (6U)
+
+/*! @name CLR - Clear port */
+/*! @{ */
+#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)
+#define GPIO_CLR_CLRP_SHIFT (0U)
+/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
+ * specific device and package. 0 = No operation. 1 = Clear output bit.
+ */
+#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
+/*! @} */
+
+/* The count of GPIO_CLR */
+#define GPIO_CLR_COUNT (6U)
+
+/*! @name NOT - Toggle port */
+/*! @{ */
+#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)
+#define GPIO_NOT_NOTP_SHIFT (0U)
+/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
+ * specific device and package. 0 = no operation. 1 = Toggle output bit.
+ */
+#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
+/*! @} */
+
+/* The count of GPIO_NOT */
+#define GPIO_NOT_COUNT (6U)
+
+/*! @name DIRSET - Set pin direction bits for port */
+/*! @{ */
+#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)
+#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
+/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ * the specific device and package. 0 = No operation. 1 = Set direction bit.
+ */
+#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRSET */
+#define GPIO_DIRSET_COUNT (6U)
+
+/*! @name DIRCLR - Clear pin direction bits for port */
+/*! @{ */
+#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)
+#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
+/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
+ * the specific device and package. 0 = No operation. 1 = Clear direction bit.
+ */
+#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRCLR */
+#define GPIO_DIRCLR_COUNT (6U)
+
+/*! @name DIRNOT - Toggle pin direction bits for port */
+/*! @{ */
+#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
+#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
+/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
+ * on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
+ */
+#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRNOT */
+#define GPIO_DIRNOT_COUNT (6U)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIO base address */
+#define GPIO_BASE (0x4008C000u)
+/** Peripheral GPIO base pointer */
+#define GPIO ((GPIO_Type *)GPIO_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { GPIO_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { GPIO }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[2048];
+ __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */
+ __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */
+ __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */
+ __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
+ __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */
+ __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */
+ __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */
+ uint8_t RESERVED_2[20];
+ __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */
+ __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
+ __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */
+ __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */
+ uint8_t RESERVED_3[36];
+ __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */
+ uint8_t RESERVED_4[1912];
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration for shared functions. */
+/*! @{ */
+#define I2C_CFG_MSTEN_MASK (0x1U)
+#define I2C_CFG_MSTEN_SHIFT (0U)
+/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
+ * changed, but the Master function is internally reset.
+ * 0b0..Disabled. The I2C Master function is disabled.
+ * 0b1..Enabled. The I2C Master function is enabled.
+ */
+#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
+#define I2C_CFG_SLVEN_MASK (0x2U)
+#define I2C_CFG_SLVEN_SHIFT (1U)
+/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
+ * changed, but the Slave function is internally reset.
+ * 0b0..Disabled. The I2C slave function is disabled.
+ * 0b1..Enabled. The I2C slave function is enabled.
+ */
+#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
+#define I2C_CFG_MONEN_MASK (0x4U)
+#define I2C_CFG_MONEN_SHIFT (2U)
+/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
+ * changed, but the Monitor function is internally reset.
+ * 0b0..Disabled. The I2C Monitor function is disabled.
+ * 0b1..Enabled. The I2C Monitor function is enabled.
+ */
+#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
+#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
+#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
+/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
+ * 0b0..Disabled. Time-out function is disabled.
+ * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
+ * interrupts if they are enabled. Typically, only one time-out will be used in a system.
+ */
+#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
+#define I2C_CFG_MONCLKSTR_MASK (0x10U)
+#define I2C_CFG_MONCLKSTR_SHIFT (4U)
+/*! MONCLKSTR - Monitor function Clock Stretching.
+ * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
+ * to read data provided by the Monitor function before it is overwritten. This mode may be used when
+ * non-invasive monitoring is critical.
+ * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
+ * read all incoming data supplied by the Monitor function.
+ */
+#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
+#define I2C_CFG_HSCAPABLE_MASK (0x20U)
+#define I2C_CFG_HSCAPABLE_SHIFT (5U)
+/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive
+ * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies
+ * to all functions: Master, Slave, and Monitor.
+ * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the
+ * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls,
+ * such as changing the drive strength or filtering, must be made by software via the IOCON register associated
+ * with each I2C pin,
+ * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support
+ * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more
+ * information.
+ */
+#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
+/*! @} */
+
+/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
+/*! @{ */
+#define I2C_STAT_MSTPENDING_MASK (0x1U)
+#define I2C_STAT_MSTPENDING_SHIFT (0U)
+/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
+ * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
+ * type of software service if any the master expects. This flag will cause an interrupt when set
+ * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
+ * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
+ * state, and no communication is needed, mask this interrupt.
+ * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
+ * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
+ * idle state, it is waiting to receive or transmit data or the NACK bit.
+ */
+#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
+#define I2C_STAT_MSTSTATE_MASK (0xEU)
+#define I2C_STAT_MSTSTATE_SHIFT (1U)
+/*! MSTSTATE - Master State code. The master state code reflects the master state when the
+ * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
+ * indicates a specific required service for the Master function. All other values are reserved. See
+ * Table 400 for details of state values and appropriate responses.
+ * 0b000..Idle. The Master function is available to be used for a new transaction.
+ * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
+ * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
+ * 0b011..NACK Address. Slave NACKed address.
+ * 0b100..NACK Data. Slave NACKed transmitted data.
+ */
+#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
+#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
+#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
+/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
+ * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
+ * 0b0..No Arbitration Loss has occurred.
+ * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
+ * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
+ * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
+ */
+#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
+#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
+#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
+/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
+ * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
+ * 0b0..No Start/Stop Error has occurred.
+ * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is
+ * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an
+ * idle state, no action is required. A request for a Start could be made, or software could attempt to insure
+ * that the bus has not stalled.
+ */
+#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
+#define I2C_STAT_SLVPENDING_MASK (0x100U)
+#define I2C_STAT_SLVPENDING_SHIFT (8U)
+/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
+ * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
+ * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
+ * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is
+ * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time
+ * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section
+ * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are
+ * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must
+ * also be detected automatically, since the address must be acknowledged before the clock can be
+ * stretched.
+ * 0b0..In progress. The Slave function does not currently need service.
+ * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
+ */
+#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
+#define I2C_STAT_SLVSTATE_MASK (0x600U)
+#define I2C_STAT_SLVSTATE_SHIFT (9U)
+/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
+ * the Slave function. All other values are reserved. See Table 401 for state values and actions.
+ * note that the occurrence of some states and how they are handled are affected by DMA mode and
+ * Automatic Operation modes.
+ * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
+ * 0b01..Slave receive. Received data is available (Slave Receiver mode).
+ * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
+ */
+#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
+#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
+#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
+/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
+ * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
+ * operation. This read-only flag reflects the slave function status in real time.
+ * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
+ * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
+ * Power-down mode could be entered at this time.
+ */
+#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
+#define I2C_STAT_SLVIDX_MASK (0x3000U)
+#define I2C_STAT_SLVIDX_SHIFT (12U)
+/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
+ * selected by receiving an address that matches one of the slave addresses defined by any enabled
+ * slave address registers, and provides an identification of the address that was matched. It is
+ * possible that more than one address could be matched, but only one match can be reported here.
+ * 0b00..Address 0. Slave address 0 was matched.
+ * 0b01..Address 1. Slave address 1 was matched.
+ * 0b10..Address 2. Slave address 2 was matched.
+ * 0b11..Address 3. Slave address 3 was matched.
+ */
+#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
+#define I2C_STAT_SLVSEL_MASK (0x4000U)
+#define I2C_STAT_SLVSEL_SHIFT (14U)
+/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
+ * function to acknowledge the address, or when the address has been automatically acknowledged.
+ * It is cleared when another address cycle presents an address that does not match an enabled
+ * address on the Slave function, when slave software decides to NACK a matched address, when
+ * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of
+ * Automatic Operation. SLVSEL is not cleared if software NACKs data.
+ * 0b0..Not selected. The Slave function is not currently selected.
+ * 0b1..Selected. The Slave function is currently selected.
+ */
+#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
+#define I2C_STAT_SLVDESEL_MASK (0x8000U)
+#define I2C_STAT_SLVDESEL_SHIFT (15U)
+/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
+ * INTENSET. This flag can be cleared by writing a 1 to this bit.
+ * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
+ * selected. That information can be found in the SLVSEL flag.
+ * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
+ * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
+ */
+#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
+#define I2C_STAT_MONRDY_MASK (0x10000U)
+#define I2C_STAT_MONRDY_SHIFT (16U)
+/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
+ * 0b0..No data. The Monitor function does not currently have data available.
+ * 0b1..Data waiting. The Monitor function has data waiting to be read.
+ */
+#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
+#define I2C_STAT_MONOV_MASK (0x20000U)
+#define I2C_STAT_MONOV_SHIFT (17U)
+/*! MONOV - Monitor Overflow flag.
+ * 0b0..No overrun. Monitor data has not overrun.
+ * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
+ * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
+ */
+#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
+#define I2C_STAT_MONACTIVE_MASK (0x40000U)
+#define I2C_STAT_MONACTIVE_SHIFT (18U)
+/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
+ * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
+ * more recently than a bus Stop.
+ * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
+ * 0b1..Active. The Monitor function considers the I2C bus to be active.
+ */
+#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
+#define I2C_STAT_MONIDLE_MASK (0x80000U)
+#define I2C_STAT_MONIDLE_SHIFT (19U)
+/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
+ * from active to inactive. This can be used by software to decide when to process data
+ * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
+ * INTENSET register. The flag can be cleared by writing a 1 to this bit.
+ * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
+ * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
+ */
+#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
+#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
+#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
+/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
+ * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
+ * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
+ * is idle.
+ * 0b0..No time-out. I2C bus events have not caused a time-out.
+ * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
+ */
+#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
+#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
+#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
+/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
+ * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
+ * 0b0..No time-out. SCL low time has not caused a time-out.
+ * 0b1..Time-out. SCL low time has caused a time-out.
+ */
+#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable Set and read register. */
+/*! @{ */
+#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
+/*! MSTPENDINGEN - Master Pending interrupt Enable.
+ * 0b0..Disabled. The MstPending interrupt is disabled.
+ * 0b1..Enabled. The MstPending interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
+#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
+/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
+ * 0b0..Disabled. The MstArbLoss interrupt is disabled.
+ * 0b1..Enabled. The MstArbLoss interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
+#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
+/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
+ * 0b0..Disabled. The MstStStpErr interrupt is disabled.
+ * 0b1..Enabled. The MstStStpErr interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
+#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
+/*! SLVPENDINGEN - Slave Pending interrupt Enable.
+ * 0b0..Disabled. The SlvPending interrupt is disabled.
+ * 0b1..Enabled. The SlvPending interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
+#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
+/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
+ * 0b0..Disabled. The SlvNotStr interrupt is disabled.
+ * 0b1..Enabled. The SlvNotStr interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
+#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
+#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
+/*! SLVDESELEN - Slave Deselect interrupt Enable.
+ * 0b0..Disabled. The SlvDeSel interrupt is disabled.
+ * 0b1..Enabled. The SlvDeSel interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
+#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
+#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
+/*! MONRDYEN - Monitor data Ready interrupt Enable.
+ * 0b0..Disabled. The MonRdy interrupt is disabled.
+ * 0b1..Enabled. The MonRdy interrupt is enabled.
+ */
+#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
+#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
+#define I2C_INTENSET_MONOVEN_SHIFT (17U)
+/*! MONOVEN - Monitor Overrun interrupt Enable.
+ * 0b0..Disabled. The MonOv interrupt is disabled.
+ * 0b1..Enabled. The MonOv interrupt is enabled.
+ */
+#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
+#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
+#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
+/*! MONIDLEEN - Monitor Idle interrupt Enable.
+ * 0b0..Disabled. The MonIdle interrupt is disabled.
+ * 0b1..Enabled. The MonIdle interrupt is enabled.
+ */
+#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
+/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
+ * 0b0..Disabled. The Event time-out interrupt is disabled.
+ * 0b1..Enabled. The Event time-out interrupt is enabled.
+ */
+#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
+/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
+ * 0b0..Disabled. The SCL time-out interrupt is disabled.
+ * 0b1..Enabled. The SCL time-out interrupt is enabled.
+ */
+#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear register. */
+/*! @{ */
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
+/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
+ * bit in the INTENSET register if implemented.
+ */
+#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
+/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
+ */
+#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
+/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
+ */
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
+/*! SLVPENDINGCLR - Slave Pending interrupt clear.
+ */
+#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
+/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
+ */
+#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
+#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
+/*! SLVDESELCLR - Slave Deselect interrupt clear.
+ */
+#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
+#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
+#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
+/*! MONRDYCLR - Monitor data Ready interrupt clear.
+ */
+#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
+#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
+#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
+/*! MONOVCLR - Monitor Overrun interrupt clear.
+ */
+#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
+#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
+#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
+/*! MONIDLECLR - Monitor Idle interrupt clear.
+ */
+#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
+/*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
+ */
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
+/*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
+ */
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
+/*! @} */
+
+/*! @name TIMEOUT - Time-out value register. */
+/*! @{ */
+#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
+#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
+/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
+ * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
+ */
+#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
+#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
+#define I2C_TIMEOUT_TO_SHIFT (4U)
+/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
+ * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
+ * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
+ * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after
+ * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
+ * I2C function clock.
+ */
+#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
+/*! @} */
+
+/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
+/*! @{ */
+#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
+#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
+/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
+ * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
+ * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
+ * divided by 65,536 before use.
+ */
+#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
+/*! @{ */
+#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
+#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
+/*! MSTPENDING - Master Pending.
+ */
+#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
+#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
+/*! MSTARBLOSS - Master Arbitration Loss flag.
+ */
+#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
+#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
+/*! MSTSTSTPERR - Master Start/Stop Error flag.
+ */
+#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
+#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
+#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
+/*! SLVPENDING - Slave Pending.
+ */
+#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
+#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
+/*! SLVNOTSTR - Slave Not Stretching status.
+ */
+#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
+#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
+#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
+/*! SLVDESEL - Slave Deselected flag.
+ */
+#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
+#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
+#define I2C_INTSTAT_MONRDY_SHIFT (16U)
+/*! MONRDY - Monitor Ready.
+ */
+#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
+#define I2C_INTSTAT_MONOV_MASK (0x20000U)
+#define I2C_INTSTAT_MONOV_SHIFT (17U)
+/*! MONOV - Monitor Overflow flag.
+ */
+#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
+#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
+#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
+/*! MONIDLE - Monitor Idle flag.
+ */
+#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
+/*! EVENTTIMEOUT - Event time-out Interrupt flag.
+ */
+#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
+#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
+/*! SCLTIMEOUT - SCL time-out Interrupt flag.
+ */
+#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
+/*! @} */
+
+/*! @name MSTCTL - Master control register. */
+/*! @{ */
+#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
+/*! MSTCONTINUE - Master Continue. This bit is write-only.
+ * 0b0..No effect.
+ * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing
+ * transmit data, reading received data, or any other housekeeping related to the next bus operation.
+ */
+#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
+#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
+#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
+/*! MSTSTART - Master Start control. This bit is write-only.
+ * 0b0..No effect.
+ * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
+ */
+#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
+#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
+#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
+/*! MSTSTOP - Master Stop control. This bit is write-only.
+ * 0b0..No effect.
+ * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
+ * if the master is receiving data from the slave (Master Receiver mode).
+ */
+#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
+#define I2C_MSTCTL_MSTDMA_MASK (0x8U)
+#define I2C_MSTCTL_MSTDMA_SHIFT (3U)
+/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type
+ * operations such as Start, address, Stop, and address match must always be done with software,
+ * typically via an interrupt. Address acknowledgement must also be done by software except when
+ * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by
+ * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA
+ * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is
+ * read/write.
+ * 0b0..Disable. No DMA requests are generated for master operation.
+ * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
+ * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
+ */
+#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
+/*! @} */
+
+/*! @name MSTTIME - Master timing configuration. */
+/*! @{ */
+#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
+/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
+ * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
+ * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
+ * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
+ * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
+ * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
+ * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
+ * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
+ * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
+ * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
+ * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
+ * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
+ */
+#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
+#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
+/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
+ * master on SCL. Other masters in a multi-master system could shorten this time. This
+ * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
+ * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
+ * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
+ * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
+ * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
+ * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
+ * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
+ * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
+ * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
+ * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
+ */
+#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
+/*! @} */
+
+/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
+/*! @{ */
+#define I2C_MSTDAT_DATA_MASK (0xFFU)
+#define I2C_MSTDAT_DATA_SHIFT (0U)
+/*! DATA - Master function data register. Read: read the most recently received data for the Master
+ * function. Write: transmit data using the Master function.
+ */
+#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
+/*! @} */
+
+/*! @name SLVCTL - Slave control register. */
+/*! @{ */
+#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
+/*! SLVCONTINUE - Slave Continue.
+ * 0b0..No effect.
+ * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag
+ * in the STAT register. This must be done after writing transmit data, reading received data, or any other
+ * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE
+ * should not be set unless SLVPENDING = 1.
+ */
+#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
+#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
+#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
+/*! SLVNACK - Slave NACK.
+ * 0b0..No effect.
+ * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
+ */
+#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
+#define I2C_SLVCTL_SLVDMA_MASK (0x8U)
+#define I2C_SLVCTL_SLVDMA_SHIFT (3U)
+/*! SLVDMA - Slave DMA enable.
+ * 0b0..Disabled. No DMA requests are issued for Slave mode operation.
+ * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
+ */
+#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
+#define I2C_SLVCTL_AUTOACK_MASK (0x100U)
+#define I2C_SLVCTL_AUTOACK_SHIFT (8U)
+/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches
+ * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA
+ * to allow processing of the data without intervention. If this bit is clear and a header
+ * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or
+ * interrupt.
+ * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching
+ * address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
+ * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately,
+ * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does
+ * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK
+ * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
+ */
+#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)
+/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write
+ * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to
+ * match the transfer direction, the direction needs to be specified. This bit allows a direction to
+ * be chosen for the next operation.
+ * 0b0..The expected next operation in Automatic Mode is an I2C write.
+ * 0b1..The expected next operation in Automatic Mode is an I2C read.
+ */
+#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
+/*! @} */
+
+/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
+/*! @{ */
+#define I2C_SLVDAT_DATA_MASK (0xFFU)
+#define I2C_SLVDAT_DATA_SHIFT (0U)
+/*! DATA - Slave function data register. Read: read the most recently received data for the Slave
+ * function. Write: transmit data using the Slave function.
+ */
+#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
+/*! @} */
+
+/*! @name SLVADR - Slave address register. */
+/*! @{ */
+#define I2C_SLVADR_SADISABLE_MASK (0x1U)
+#define I2C_SLVADR_SADISABLE_SHIFT (0U)
+/*! SADISABLE - Slave Address n Disable.
+ * 0b0..Enabled. Slave Address n is enabled.
+ * 0b1..Ignored Slave Address n is ignored.
+ */
+#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
+#define I2C_SLVADR_SLVADR_MASK (0xFEU)
+#define I2C_SLVADR_SLVADR_SHIFT (1U)
+/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.
+ */
+#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
+#define I2C_SLVADR_AUTONACK_MASK (0x8000U)
+#define I2C_SLVADR_AUTONACK_SHIFT (15U)
+/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows
+ * software to ignore I2C traffic while handling previous I2C data or other operations.
+ * 0b0..Normal operation, matching I2C addresses are not ignored.
+ * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches
+ * SLVADRn, and AUTOMATCHREAD matches the direction.
+ */
+#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
+/*! @} */
+
+/* The count of I2C_SLVADR */
+#define I2C_SLVADR_COUNT (4U)
+
+/*! @name SLVQUAL0 - Slave Qualification for address 0. */
+/*! @{ */
+#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
+/*! QUALMODE0 - Qualify mode for slave address 0.
+ * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
+ * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
+ */
+#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
+#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
+/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to
+ * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is
+ * set to 1 will cause an automatic match of the corresponding bit of the received address when it
+ * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for
+ * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0
+ * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
+ */
+#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
+/*! @} */
+
+/*! @name MONRXDAT - Monitor receiver data register. */
+/*! @{ */
+#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
+#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
+/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
+ */
+#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
+#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
+#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
+/*! MONSTART - Monitor Received Start.
+ * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
+ * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
+ */
+#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
+#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
+#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
+/*! MONRESTART - Monitor Received Repeated Start.
+ * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
+ * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
+ */
+#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
+#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
+#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
+/*! MONNACK - Monitor Received NACK.
+ * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
+ * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
+ */
+#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral identification register. */
+/*! @{ */
+#define I2C_ID_APERTURE_MASK (0xFFU)
+#define I2C_ID_APERTURE_SHIFT (0U)
+/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
+ */
+#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
+#define I2C_ID_MINOR_REV_MASK (0xF00U)
+#define I2C_ID_MINOR_REV_SHIFT (8U)
+/*! MINOR_REV - Minor revision of module implementation.
+ */
+#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
+#define I2C_ID_MAJOR_REV_MASK (0xF000U)
+#define I2C_ID_MAJOR_REV_SHIFT (12U)
+/*! MAJOR_REV - Major revision of module implementation.
+ */
+#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
+#define I2C_ID_ID_MASK (0xFFFF0000U)
+#define I2C_ID_ID_SHIFT (16U)
+/*! ID - Module identifier for the selected function.
+ */
+#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40086000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40087000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE (0x40088000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2 ((I2C_Type *)I2C2_BASE)
+/** Peripheral I2C3 base address */
+#define I2C3_BASE (0x40089000u)
+/** Peripheral I2C3 base pointer */
+#define I2C3 ((I2C_Type *)I2C3_BASE)
+/** Peripheral I2C4 base address */
+#define I2C4_BASE (0x4008A000u)
+/** Peripheral I2C4 base pointer */
+#define I2C4 ((I2C_Type *)I2C4_BASE)
+/** Peripheral I2C5 base address */
+#define I2C5_BASE (0x40096000u)
+/** Peripheral I2C5 base pointer */
+#define I2C5 ((I2C_Type *)I2C5_BASE)
+/** Peripheral I2C6 base address */
+#define I2C6_BASE (0x40097000u)
+/** Peripheral I2C6 base pointer */
+#define I2C6 ((I2C_Type *)I2C6_BASE)
+/** Peripheral I2C7 base address */
+#define I2C7_BASE (0x40098000u)
+/** Peripheral I2C7 base pointer */
+#define I2C7 ((I2C_Type *)I2C7_BASE)
+/** Peripheral I2C8 base address */
+#define I2C8_BASE (0x40099000u)
+/** Peripheral I2C8 base pointer */
+#define I2C8 ((I2C_Type *)I2C8_BASE)
+/** Peripheral I2C9 base address */
+#define I2C9_BASE (0x4009A000u)
+/** Peripheral I2C9 base pointer */
+#define I2C9 ((I2C_Type *)I2C9_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[3072];
+ __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
+ __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
+ __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */
+ struct { /* offset: 0xC20, array step: 0x20 */
+ __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */
+ __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */
+ __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */
+ uint8_t RESERVED_0[20];
+ } SECCHANNEL[3];
+ uint8_t RESERVED_2[384];
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
+ uint8_t RESERVED_4[4];
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
+ __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
+ uint8_t RESERVED_5[8];
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
+ __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
+ uint8_t RESERVED_6[8];
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+ __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
+ uint8_t RESERVED_7[4020];
+ __I uint32_t ID; /**< I2S Module identification, offset: 0x1DFC */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name CFG1 - Configuration register 1 for the primary channel pair. */
+/*! @{ */
+#define I2S_CFG1_MAINENABLE_MASK (0x1U)
+#define I2S_CFG1_MAINENABLE_SHIFT (0U)
+/*! MAINENABLE - Main enable for I 2S function in this Flexcomm
+ * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags
+ * are reset. No other channel pairs can be enabled.
+ * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits.
+ */
+#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
+#define I2S_CFG1_DATAPAUSE_MASK (0x2U)
+#define I2S_CFG1_DATAPAUSE_SHIFT (1U)
+/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer
+ * and the FIFO. This could be done in order to change streams, or while restarting after a data
+ * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is
+ * in the process of being sent or received. Once a data pause has been requested, the interface
+ * may need to complete sending data that was in progress before interrupting the flow of data.
+ * Software must check that the pause is actually in effect before taking action. This is done by
+ * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer
+ * will resume at the beginning of the next frame.
+ * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused.
+ * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1.
+ */
+#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
+#define I2S_CFG1_PAIRCOUNT_MASK (0xCU)
+#define I2S_CFG1_PAIRCOUNT_SHIFT (2U)
+/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field
+ * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this
+ * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs
+ * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.
+ * 0b00..1 I2S channel pairs in this flexcomm
+ * 0b01..2 I2S channel pairs in this flexcomm
+ * 0b10..3 I2S channel pairs in this flexcomm
+ * 0b11..4 I2S channel pairs in this flexcomm
+ */
+#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
+#define I2S_CFG1_MSTSLVCFG_MASK (0x30U)
+#define I2S_CFG1_MSTSLVCFG_SHIFT (4U)
+/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.
+ * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data.
+ * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of
+ * SCK, when divided from the Flexcomm function clock.
+ * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data.
+ * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices.
+ */
+#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
+#define I2S_CFG1_MODE_MASK (0xC0U)
+#define I2S_CFG1_MODE_SHIFT (6U)
+/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all
+ * supported cases. See Formats and modes for examples.
+ * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece
+ * of left channel data occurring during the first phase, and one pieces of right channel data occurring
+ * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the
+ * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If
+ * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right.
+ * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0.
+ * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame.
+ * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame.
+ */
+#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
+#define I2S_CFG1_RIGHTLOW_MASK (0x100U)
+#define I2S_CFG1_RIGHTLOW_SHIFT (8U)
+/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left
+ * and right channel data as it is transferred to or from the FIFO. This bit is not used if the
+ * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10
+ * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION
+ * can still place that data in the frame where right channel data is normally located. if all
+ * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.
+ * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO
+ * bits 31:16 are used for the right channel.
+ * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO
+ * bits 15:0 are used for the right channel.
+ */
+#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
+#define I2S_CFG1_LEFTJUST_MASK (0x200U)
+#define I2S_CFG1_LEFTJUST_SHIFT (9U)
+/*! LEFTJUST - Left Justify data.
+ * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting
+ * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data
+ * in the stream on the data bus.
+ * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting
+ * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would
+ * correspond to left justified data in the stream on the data bus.
+ */
+#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
+#define I2S_CFG1_ONECHANNEL_MASK (0x400U)
+#define I2S_CFG1_ONECHANNEL_SHIFT (10U)
+/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit
+ * applies only to the first I2S channel pair. Other channel pairs may select this mode
+ * independently in their separate CFG1 registers.
+ * 0b0..I2S data for this channel pair is treated as left and right channels.
+ * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this
+ * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a
+ * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel
+ * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side
+ * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data
+ * for the single channel of data is placed at the clock defined by POSITION.
+ */
+#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
+#define I2S_CFG1_PDMDATA_MASK (0x800U)
+#define I2S_CFG1_PDMDATA_SHIFT (11U)
+/*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be
+ * set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a
+ * D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7.
+ * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO.
+ * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in
+ * this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample
+ * rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun.
+ */
+#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
+#define I2S_CFG1_SCK_POL_MASK (0x1000U)
+#define I2S_CFG1_SCK_POL_SHIFT (12U)
+/*! SCK_POL - SCK polarity.
+ * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S).
+ * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges.
+ */
+#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
+#define I2S_CFG1_WS_POL_MASK (0x2000U)
+#define I2S_CFG1_WS_POL_SHIFT (13U)
+/*! WS_POL - WS polarity.
+ * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S).
+ * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S).
+ */
+#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
+#define I2S_CFG1_DATALEN_MASK (0x1F0000U)
+#define I2S_CFG1_DATALEN_SHIFT (16U)
+/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or
+ * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received
+ * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the
+ * I2S: Determines the size of data transfers between the FIFO and the I2S
+ * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of
+ * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse
+ * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to
+ * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F =
+ * data is 32 bits in length
+ */
+#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
+/*! @} */
+
+/*! @name CFG2 - Configuration register 2 for the primary channel pair. */
+/*! @{ */
+#define I2S_CFG2_FRAMELEN_MASK (0x1FFU)
+#define I2S_CFG2_FRAMELEN_SHIFT (0U)
+/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the
+ * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported
+ * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is
+ * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in
+ * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger
+ * than DATALEN in order for the WS pulse to be generated correctly.
+ */
+#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
+#define I2S_CFG2_POSITION_MASK (0x1FF0000U)
+#define I2S_CFG2_POSITION_SHIFT (16U)
+/*! POSITION - Data Position. Defines the location within the frame of the data for this channel
+ * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION
+ * defines the location of data in both the left phase and right phase, starting one clock after
+ * the WS edge. In other modes, POSITION defines the location of data within the entire frame.
+ * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The
+ * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels
+ * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit
+ * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS
+ * phase. 0x002 = data begins at bit position 2 within the frame or WS phase.
+ */
+#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
+/*! @} */
+
+/*! @name STAT - Status register for the primary channel pair. */
+/*! @{ */
+#define I2S_STAT_BUSY_MASK (0x1U)
+#define I2S_STAT_BUSY_SHIFT (0U)
+/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair.
+ * 0b0..The transmitter/receiver for channel pair is currently idle.
+ * 0b1..The transmitter/receiver for channel pair is currently processing data.
+ */
+#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
+#define I2S_STAT_SLVFRMERR_MASK (0x2U)
+#define I2S_STAT_SLVFRMERR_SHIFT (1U)
+/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as
+ * a slave. An error indicates that the incoming WS signal did not transition as expected due to
+ * a mismatch between FRAMELEN and the actual incoming I2S stream.
+ * 0b0..No error has been recorded.
+ * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position.
+ */
+#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
+#define I2S_STAT_LR_MASK (0x4U)
+#define I2S_STAT_LR_SHIFT (2U)
+/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to
+ * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data
+ * being processed for the currently busy channel pair.
+ * 0b0..Left channel.
+ * 0b1..Right channel.
+ */
+#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
+#define I2S_STAT_DATAPAUSED_MASK (0x8U)
+#define I2S_STAT_DATAPAUSED_SHIFT (3U)
+/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels
+ * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for
+ * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register.
+ * 0b1..A data pause has been requested and is now in force.
+ */
+#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
+/*! @} */
+
+/*! @name DIV - Clock divider, used by all channel pairs. */
+/*! @{ */
+#define I2S_DIV_DIV_MASK (0xFFFU)
+#define I2S_DIV_DIV_SHIFT (0U)
+/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The
+ * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2.
+ * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is
+ * divided by 4,096.
+ */
+#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
+/*! @} */
+
+/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */
+/*! @{ */
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U)
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U)
+/*! PAIRENABLE - Enable for this channel pair..
+ */
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U)
+/*! ONECHANNEL - Single channel mode.
+ */
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PCFG1 */
+#define I2S_SECCHANNEL_PCFG1_COUNT (3U)
+
+/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */
+/*! @{ */
+#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U)
+#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U)
+/*! POSITION - Data Position.
+ */
+#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PCFG2 */
+#define I2S_SECCHANNEL_PCFG2_COUNT (3U)
+
+/*! @name SECCHANNEL_PSTAT - Status register for channel pair */
+/*! @{ */
+#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U)
+#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U)
+/*! BUSY - Busy status for this channel pair.
+ */
+#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U)
+/*! SLVFRMERR - Save Frame Error flag.
+ */
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
+#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U)
+#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U)
+/*! LR - Left/Right indication.
+ */
+#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U)
+/*! DATAPAUSED - Data Paused status flag.
+ */
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PSTAT */
+#define I2S_SECCHANNEL_PSTAT_COUNT (3U)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+/*! @{ */
+#define I2S_FIFOCFG_ENABLETX_MASK (0x1U)
+#define I2S_FIFOCFG_ENABLETX_SHIFT (0U)
+/*! ENABLETX - Enable the transmit FIFO.
+ * 0b0..The transmit FIFO is not enabled.
+ * 0b1..The transmit FIFO is enabled.
+ */
+#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
+#define I2S_FIFOCFG_ENABLERX_MASK (0x2U)
+#define I2S_FIFOCFG_ENABLERX_SHIFT (1U)
+/*! ENABLERX - Enable the receive FIFO.
+ * 0b0..The receive FIFO is not enabled.
+ * 0b1..The receive FIFO is enabled.
+ */
+#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
+#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
+/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX
+ * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is
+ * cleared, new data is provided, and the I2S is un-paused.
+ * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24
+ * bits or less, or when MONO = 1 for this channel pair.
+ * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred.
+ */
+#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+#define I2S_FIFOCFG_PACK48_MASK (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT (3U)
+/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.
+ * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values.
+ * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values.
+ */
+#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+#define I2S_FIFOCFG_SIZE_MASK (0x30U)
+#define I2S_FIFOCFG_SIZE_SHIFT (4U)
+/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
+ * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
+ */
+#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
+#define I2S_FIFOCFG_DMATX_MASK (0x1000U)
+#define I2S_FIFOCFG_DMATX_SHIFT (12U)
+/*! DMATX - DMA configuration for transmit.
+ * 0b0..DMA is not used for the transmit function.
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
+#define I2S_FIFOCFG_DMARX_MASK (0x2000U)
+#define I2S_FIFOCFG_DMARX_SHIFT (13U)
+/*! DMARX - DMA configuration for receive.
+ * 0b0..DMA is not used for the receive function.
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
+#define I2S_FIFOCFG_WAKETX_MASK (0x4000U)
+#define I2S_FIFOCFG_WAKETX_SHIFT (14U)
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ * Wake-up control register.
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
+ * FIFOTRIG, even when the TXLVL interrupt is not enabled.
+ */
+#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
+#define I2S_FIFOCFG_WAKERX_MASK (0x8000U)
+#define I2S_FIFOCFG_WAKERX_SHIFT (15U)
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ * Wake-up control register.
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
+ * FIFOTRIG, even when the RXLVL interrupt is not enabled.
+ */
+#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
+#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U)
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
+ */
+#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
+#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U)
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
+ */
+#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO status register. */
+/*! @{ */
+#define I2S_FIFOSTAT_TXERR_MASK (0x1U)
+#define I2S_FIFOSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
+ * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
+ * needed. Cleared by writing a 1 to this bit.
+ */
+#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
+#define I2S_FIFOSTAT_RXERR_MASK (0x2U)
+#define I2S_FIFOSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
+ * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
+ */
+#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
+#define I2S_FIFOSTAT_PERINT_MASK (0x8U)
+#define I2S_FIFOSTAT_PERINT_SHIFT (3U)
+/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
+ * an interrupt. The details can be found by reading the peripheral's STAT register.
+ */
+#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
+#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
+ */
+#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
+#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
+ * written. When 0, the transmit FIFO is full and another write would cause it to overflow.
+ */
+#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
+ */
+#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
+#define I2S_FIFOSTAT_RXFULL_MASK (0x80U)
+#define I2S_FIFOSTAT_RXFULL_SHIFT (7U)
+/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
+ * prevent the peripheral from causing an overflow.
+ */
+#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
+#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define I2S_FIFOSTAT_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
+ * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
+ * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
+ * 0.
+ */
+#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
+#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define I2S_FIFOSTAT_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
+ * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
+ * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
+ * 1.
+ */
+#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+/*! @{ */
+#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U)
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
+ * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
+ */
+#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
+#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U)
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
+ * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
+ */
+#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
+#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define I2S_FIFOTRIG_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
+ * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
+ * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
+ * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
+ * FIFO level decreases to 15 entries (is no longer full).
+ */
+#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
+#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define I2S_FIFOTRIG_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
+ * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
+ * can wake up the device just enough to perform DMA, then return to the reduced power mode. See
+ * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
+ * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
+ * FIFO has received 16 entries (has become full).
+ */
+#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+/*! @{ */
+#define I2S_FIFOINTENSET_TXERR_MASK (0x1U)
+#define I2S_FIFOINTENSET_TXERR_SHIFT (0U)
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a transmit error.
+ * 0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
+#define I2S_FIFOINTENSET_RXERR_MASK (0x2U)
+#define I2S_FIFOINTENSET_RXERR_SHIFT (1U)
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a receive error.
+ * 0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
+#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U)
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
+ * specified by the TXLVL field in the FIFOTRIG register.
+ * 0b0..No interrupt will be generated based on the TX FIFO level.
+ * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
+ * to the level specified by TXLVL in the FIFOTRIG register.
+ */
+#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
+#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U)
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
+ * specified by the TXLVL field in the FIFOTRIG register.
+ * 0b0..No interrupt will be generated based on the RX FIFO level.
+ * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
+ * increases to the level specified by RXLVL in the FIFOTRIG register.
+ */
+#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+/*! @{ */
+#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U)
+/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
+#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U)
+/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
+#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U)
+/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
+#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U)
+/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+/*! @{ */
+#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO error.
+ */
+#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
+#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO error.
+ */
+#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
+#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit FIFO level interrupt.
+ */
+#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
+#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive FIFO level interrupt.
+ */
+#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
+#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U)
+/*! PERINT - Peripheral interrupt.
+ */
+#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO write data. */
+/*! @{ */
+#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFOWR_TXDATA_SHIFT (0U)
+/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details.
+ */
+#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+/*! @{ */
+#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFOWR48H_TXDATA_SHIFT (0U)
+/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details.
+ */
+#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO read data. */
+/*! @{ */
+#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFORD_RXDATA_SHIFT (0U)
+/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details.
+ */
+#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+/*! @{ */
+#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFORD48H_RXDATA_SHIFT (0U)
+/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
+ */
+#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+/*! @{ */
+#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U)
+/*! RXDATA - Received data from the FIFO.
+ */
+#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+/*! @{ */
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U)
+/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
+ */
+#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
+/*! @} */
+
+/*! @name ID - I2S Module identification */
+/*! @{ */
+#define I2S_ID_Aperture_MASK (0xFFU)
+#define I2S_ID_Aperture_SHIFT (0U)
+/*! Aperture - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
+ */
+#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK)
+#define I2S_ID_Minor_Rev_MASK (0xF00U)
+#define I2S_ID_Minor_Rev_SHIFT (8U)
+/*! Minor_Rev - Minor revision of module implementation, starting at 0.
+ */
+#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK)
+#define I2S_ID_Major_Rev_MASK (0xF000U)
+#define I2S_ID_Major_Rev_SHIFT (12U)
+/*! Major_Rev - Major revision of module implementation, starting at 0.
+ */
+#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK)
+#define I2S_ID_ID_MASK (0xFFFF0000U)
+#define I2S_ID_ID_SHIFT (16U)
+/*! ID - Unique module identifier for this IP block.
+ */
+#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x40097000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+/** Peripheral I2S1 base address */
+#define I2S1_BASE (0x40098000u)
+/** Peripheral I2S1 base pointer */
+#define I2S1 ((I2S_Type *)I2S1_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0, I2S1 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- INPUTMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INPUTMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SCT0_INMUX[7]; /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */
+ uint8_t RESERVED_0[164];
+ __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
+ __IO uint32_t DMA_ITRIG_INMUX[32]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */
+ __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */
+ __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */
+} INPUTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- INPUTMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
+ * @{
+ */
+
+/*! @name SCT0_INMUX - Trigger select register for DMA channel */
+/*! @{ */
+#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU)
+#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)
+/*! INP_N - Input number to SCT0 inputs 0 to 6..
+ */
+#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_SCT0_INMUX */
+#define INPUTMUX_SCT0_INMUX_COUNT (7U)
+
+/*! @name PINTSEL - Pin interrupt select register */
+/*! @{ */
+#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU)
+#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)
+/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
+ */
+#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_PINTSEL */
+#define INPUTMUX_PINTSEL_COUNT (8U)
+
+/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
+/*! @{ */
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU)
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)
+/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 31). 0 = ADC0 Sequence A
+ * interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 =
+ * Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match
+ * 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer
+ * CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin
+ * interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2
+ * 19 = DMA output trigger mux 3
+ */
+#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMA_ITRIG_INMUX */
+#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (32U)
+
+/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
+/*! @{ */
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU)
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U)
+/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19).
+ */
+#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMA_OTRIG_INMUX */
+#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U)
+
+/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
+/*! @{ */
+#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU)
+#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U)
+/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =
+ * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock
+ * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
+ */
+#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
+/*! @} */
+
+/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
+/*! @{ */
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U)
+/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =
+ * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock
+ * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
+ */
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Register_Masks */
+
+
+/* INPUTMUX - Peripheral instance base addresses */
+/** Peripheral INPUTMUX base address */
+#define INPUTMUX_BASE (0x40005000u)
+/** Peripheral INPUTMUX base pointer */
+#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
+/** Array initializer of INPUTMUX peripheral base addresses */
+#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
+/** Array initializer of INPUTMUX peripheral base pointers */
+#define INPUTMUX_BASE_PTRS { INPUTMUX }
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- IOCON Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
+ * @{
+ */
+
+/** IOCON - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PIO[6][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
+} IOCON_Type;
+
+/* ----------------------------------------------------------------------------
+ -- IOCON Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Register_Masks IOCON Register Masks
+ * @{
+ */
+
+/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */
+/*! @{ */
+#define IOCON_PIO_FUNC_MASK (0xFU)
+#define IOCON_PIO_FUNC_SHIFT (0U)
+/*! FUNC - Selects pin function.
+ * 0b0000..Alternative connection 0.
+ * 0b0001..Alternative connection 1.
+ * 0b0010..Alternative connection 2.
+ * 0b0011..Alternative connection 3.
+ * 0b0100..Alternative connection 4.
+ * 0b0101..Alternative connection 5.
+ * 0b0110..Alternative connection 6.
+ * 0b0111..Alternative connection 7.
+ * 0b1000..Alternative connection 8.
+ * 0b1001..Alternative connection 9.
+ * 0b1010..Alternative connection 10.
+ */
+#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
+#define IOCON_PIO_MODE_MASK (0x30U)
+#define IOCON_PIO_MODE_SHIFT (4U)
+/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).
+ * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
+ * 0b01..Pull-down. Pull-down resistor enabled.
+ * 0b10..Pull-up. Pull-up resistor enabled.
+ * 0b11..Repeater. Repeater mode.
+ */
+#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
+#define IOCON_PIO_ANAMODE_MASK (0x40U)
+#define IOCON_PIO_ANAMODE_SHIFT (6U)
+/*! ANAMODE - Enables or disables analog mode.
+ * 0b0..Enable analog Mode.
+ * 0b1..Disable analog Mode.
+ */
+#define IOCON_PIO_ANAMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ANAMODE_SHIFT)) & IOCON_PIO_ANAMODE_MASK)
+#define IOCON_PIO_I2CSLEW_MASK (0x40U)
+#define IOCON_PIO_I2CSLEW_SHIFT (6U)
+/*! I2CSLEW - Controls slew rate of I2C pad.
+ * 0b0..I2C mode.
+ * 0b1..GPIO mode.
+ */
+#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)
+#define IOCON_PIO_INVERT_MASK (0x80U)
+#define IOCON_PIO_INVERT_SHIFT (7U)
+/*! INVERT - Input polarity.
+ * 0b0..Disabled. Input function is not inverted.
+ * 0b1..Enabled. Input is function inverted.
+ */
+#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
+#define IOCON_PIO_DIGIMODE_MASK (0x100U)
+#define IOCON_PIO_DIGIMODE_SHIFT (8U)
+/*! DIGIMODE - Select Analog/Digital mode.
+ * 0b0..Analog mode.
+ * 0b1..Digital mode.
+ */
+#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
+#define IOCON_PIO_FILTEROFF_MASK (0x200U)
+#define IOCON_PIO_FILTEROFF_SHIFT (9U)
+/*! FILTEROFF - Controls input glitch filter.
+ * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out.
+ * 0b1..Filter disabled. No input filtering is done.
+ */
+#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
+#define IOCON_PIO_I2CDRIVE_MASK (0x400U)
+#define IOCON_PIO_I2CDRIVE_SHIFT (10U)
+/*! I2CDRIVE - Controls the current sink capability of the pin.
+ * 0b0..Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
+ * 0b1..High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate
+ * specific device data sheet for details.
+ */
+#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)
+#define IOCON_PIO_SLEW_MASK (0x400U)
+#define IOCON_PIO_SLEW_SHIFT (10U)
+/*! SLEW - Driver slew rate.
+ * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
+ * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
+ */
+#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
+#define IOCON_PIO_I2CFILTEROFF_MASK (0x800U)
+#define IOCON_PIO_I2CFILTEROFF_SHIFT (11U)
+/*! I2CFILTEROFF - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
+ * 0b0..Enabled. I2C 50 ns glitch filter enabled.
+ * 0b1..Disabled. I2C 50 ns glitch filter disabled.
+ */
+#define IOCON_PIO_I2CFILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTEROFF_SHIFT)) & IOCON_PIO_I2CFILTEROFF_MASK)
+#define IOCON_PIO_OD_MASK (0x800U)
+#define IOCON_PIO_OD_SHIFT (11U)
+/*! OD - Controls open-drain mode.
+ * 0b0..Normal. Normal push-pull output
+ * 0b1..Open-drain. Simulated open-drain output (high drive disabled).
+ */
+#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
+/*! @} */
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT (6U)
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT2 (32U)
+
+
+/*!
+ * @}
+ */ /* end of group IOCON_Register_Masks */
+
+
+/* IOCON - Peripheral instance base addresses */
+/** Peripheral IOCON base address */
+#define IOCON_BASE (0x40001000u)
+/** Peripheral IOCON base pointer */
+#define IOCON ((IOCON_Type *)IOCON_BASE)
+/** Array initializer of IOCON peripheral base addresses */
+#define IOCON_BASE_ADDRS { IOCON_BASE }
+/** Array initializer of IOCON peripheral base pointers */
+#define IOCON_BASE_PTRS { IOCON }
+
+/*!
+ * @}
+ */ /* end of group IOCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
+ * @{
+ */
+
+/** LCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TIMH; /**< Horizontal Timing Control register, offset: 0x0 */
+ __IO uint32_t TIMV; /**< Vertical Timing Control register, offset: 0x4 */
+ __IO uint32_t POL; /**< Clock and Signal Polarity Control register, offset: 0x8 */
+ __IO uint32_t LE; /**< Line End Control register, offset: 0xC */
+ __IO uint32_t UPBASE; /**< Upper Panel Frame Base Address register, offset: 0x10 */
+ __IO uint32_t LPBASE; /**< Lower Panel Frame Base Address register, offset: 0x14 */
+ __IO uint32_t CTRL; /**< LCD Control register, offset: 0x18 */
+ __IO uint32_t INTMSK; /**< Interrupt Mask register, offset: 0x1C */
+ __I uint32_t INTRAW; /**< Raw Interrupt Status register, offset: 0x20 */
+ __I uint32_t INTSTAT; /**< Masked Interrupt Status register, offset: 0x24 */
+ __O uint32_t INTCLR; /**< Interrupt Clear register, offset: 0x28 */
+ __I uint32_t UPCURR; /**< Upper Panel Current Address Value register, offset: 0x2C */
+ __I uint32_t LPCURR; /**< Lower Panel Current Address Value register, offset: 0x30 */
+ uint8_t RESERVED_0[460];
+ __IO uint32_t PAL[128]; /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_1[1024];
+ __IO uint32_t CRSR_IMG[256]; /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */
+ __IO uint32_t CRSR_CTRL; /**< Cursor Control register, offset: 0xC00 */
+ __IO uint32_t CRSR_CFG; /**< Cursor Configuration register, offset: 0xC04 */
+ __IO uint32_t CRSR_PAL0; /**< Cursor Palette register 0, offset: 0xC08 */
+ __IO uint32_t CRSR_PAL1; /**< Cursor Palette register 1, offset: 0xC0C */
+ __IO uint32_t CRSR_XY; /**< Cursor XY Position register, offset: 0xC10 */
+ __IO uint32_t CRSR_CLIP; /**< Cursor Clip Position register, offset: 0xC14 */
+ uint8_t RESERVED_2[8];
+ __IO uint32_t CRSR_INTMSK; /**< Cursor Interrupt Mask register, offset: 0xC20 */
+ __O uint32_t CRSR_INTCLR; /**< Cursor Interrupt Clear register, offset: 0xC24 */
+ __I uint32_t CRSR_INTRAW; /**< Cursor Raw Interrupt Status register, offset: 0xC28 */
+ __I uint32_t CRSR_INTSTAT; /**< Cursor Masked Interrupt Status register, offset: 0xC2C */
+} LCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Masks LCD Register Masks
+ * @{
+ */
+
+/*! @name TIMH - Horizontal Timing Control register */
+/*! @{ */
+#define LCD_TIMH_PPL_MASK (0xFCU)
+#define LCD_TIMH_PPL_SHIFT (2U)
+/*! PPL - Pixels-per-line.
+ */
+#define LCD_TIMH_PPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK)
+#define LCD_TIMH_HSW_MASK (0xFF00U)
+#define LCD_TIMH_HSW_SHIFT (8U)
+/*! HSW - Horizontal synchronization pulse width.
+ */
+#define LCD_TIMH_HSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK)
+#define LCD_TIMH_HFP_MASK (0xFF0000U)
+#define LCD_TIMH_HFP_SHIFT (16U)
+/*! HFP - Horizontal front porch.
+ */
+#define LCD_TIMH_HFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK)
+#define LCD_TIMH_HBP_MASK (0xFF000000U)
+#define LCD_TIMH_HBP_SHIFT (24U)
+/*! HBP - Horizontal back porch.
+ */
+#define LCD_TIMH_HBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK)
+/*! @} */
+
+/*! @name TIMV - Vertical Timing Control register */
+/*! @{ */
+#define LCD_TIMV_LPP_MASK (0x3FFU)
+#define LCD_TIMV_LPP_SHIFT (0U)
+/*! LPP - Lines per panel.
+ */
+#define LCD_TIMV_LPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK)
+#define LCD_TIMV_VSW_MASK (0xFC00U)
+#define LCD_TIMV_VSW_SHIFT (10U)
+/*! VSW - Vertical synchronization pulse width.
+ */
+#define LCD_TIMV_VSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK)
+#define LCD_TIMV_VFP_MASK (0xFF0000U)
+#define LCD_TIMV_VFP_SHIFT (16U)
+/*! VFP - Vertical front porch.
+ */
+#define LCD_TIMV_VFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK)
+#define LCD_TIMV_VBP_MASK (0xFF000000U)
+#define LCD_TIMV_VBP_SHIFT (24U)
+/*! VBP - Vertical back porch.
+ */
+#define LCD_TIMV_VBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK)
+/*! @} */
+
+/*! @name POL - Clock and Signal Polarity Control register */
+/*! @{ */
+#define LCD_POL_PCD_LO_MASK (0x1FU)
+#define LCD_POL_PCD_LO_SHIFT (0U)
+/*! PCD_LO - Lower five bits of panel clock divisor.
+ */
+#define LCD_POL_PCD_LO(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK)
+#define LCD_POL_ACB_MASK (0x7C0U)
+#define LCD_POL_ACB_SHIFT (6U)
+/*! ACB - AC bias pin frequency.
+ */
+#define LCD_POL_ACB(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK)
+#define LCD_POL_IVS_MASK (0x800U)
+#define LCD_POL_IVS_SHIFT (11U)
+/*! IVS - Invert vertical synchronization.
+ */
+#define LCD_POL_IVS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK)
+#define LCD_POL_IHS_MASK (0x1000U)
+#define LCD_POL_IHS_SHIFT (12U)
+/*! IHS - Invert horizontal synchronization.
+ */
+#define LCD_POL_IHS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK)
+#define LCD_POL_IPC_MASK (0x2000U)
+#define LCD_POL_IPC_SHIFT (13U)
+/*! IPC - Invert panel clock.
+ */
+#define LCD_POL_IPC(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK)
+#define LCD_POL_IOE_MASK (0x4000U)
+#define LCD_POL_IOE_SHIFT (14U)
+/*! IOE - Invert output enable.
+ */
+#define LCD_POL_IOE(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK)
+#define LCD_POL_CPL_MASK (0x3FF0000U)
+#define LCD_POL_CPL_SHIFT (16U)
+/*! CPL - Clocks per line.
+ */
+#define LCD_POL_CPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK)
+#define LCD_POL_BCD_MASK (0x4000000U)
+#define LCD_POL_BCD_SHIFT (26U)
+/*! BCD - Bypass panel clock divider.
+ */
+#define LCD_POL_BCD(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK)
+#define LCD_POL_PCD_HI_MASK (0xF8000000U)
+#define LCD_POL_PCD_HI_SHIFT (27U)
+/*! PCD_HI - Upper five bits of panel clock divisor.
+ */
+#define LCD_POL_PCD_HI(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK)
+/*! @} */
+
+/*! @name LE - Line End Control register */
+/*! @{ */
+#define LCD_LE_LED_MASK (0x7FU)
+#define LCD_LE_LED_SHIFT (0U)
+/*! LED - Line-end delay.
+ */
+#define LCD_LE_LED(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK)
+#define LCD_LE_LEE_MASK (0x10000U)
+#define LCD_LE_LEE_SHIFT (16U)
+/*! LEE - LCD Line end enable.
+ */
+#define LCD_LE_LEE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK)
+/*! @} */
+
+/*! @name UPBASE - Upper Panel Frame Base Address register */
+/*! @{ */
+#define LCD_UPBASE_LCDUPBASE_MASK (0xFFFFFFF8U)
+#define LCD_UPBASE_LCDUPBASE_SHIFT (3U)
+/*! LCDUPBASE - LCD upper panel base address.
+ */
+#define LCD_UPBASE_LCDUPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK)
+/*! @} */
+
+/*! @name LPBASE - Lower Panel Frame Base Address register */
+/*! @{ */
+#define LCD_LPBASE_LCDLPBASE_MASK (0xFFFFFFF8U)
+#define LCD_LPBASE_LCDLPBASE_SHIFT (3U)
+/*! LCDLPBASE - LCD lower panel base address.
+ */
+#define LCD_LPBASE_LCDLPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK)
+/*! @} */
+
+/*! @name CTRL - LCD Control register */
+/*! @{ */
+#define LCD_CTRL_LCDEN_MASK (0x1U)
+#define LCD_CTRL_LCDEN_SHIFT (0U)
+/*! LCDEN - LCD enable control bit.
+ */
+#define LCD_CTRL_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK)
+#define LCD_CTRL_LCDBPP_MASK (0xEU)
+#define LCD_CTRL_LCDBPP_SHIFT (1U)
+/*! LCDBPP - LCD bits per pixel.
+ */
+#define LCD_CTRL_LCDBPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK)
+#define LCD_CTRL_LCDBW_MASK (0x10U)
+#define LCD_CTRL_LCDBW_SHIFT (4U)
+/*! LCDBW - STN LCD monochrome/color selection.
+ */
+#define LCD_CTRL_LCDBW(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK)
+#define LCD_CTRL_LCDTFT_MASK (0x20U)
+#define LCD_CTRL_LCDTFT_SHIFT (5U)
+/*! LCDTFT - LCD panel TFT type selection.
+ */
+#define LCD_CTRL_LCDTFT(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK)
+#define LCD_CTRL_LCDMONO8_MASK (0x40U)
+#define LCD_CTRL_LCDMONO8_SHIFT (6U)
+/*! LCDMONO8 - Monochrome LCD interface width.
+ */
+#define LCD_CTRL_LCDMONO8(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK)
+#define LCD_CTRL_LCDDUAL_MASK (0x80U)
+#define LCD_CTRL_LCDDUAL_SHIFT (7U)
+/*! LCDDUAL - Single or Dual LCD panel selection.
+ */
+#define LCD_CTRL_LCDDUAL(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK)
+#define LCD_CTRL_BGR_MASK (0x100U)
+#define LCD_CTRL_BGR_SHIFT (8U)
+/*! BGR - Color format selection.
+ */
+#define LCD_CTRL_BGR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK)
+#define LCD_CTRL_BEBO_MASK (0x200U)
+#define LCD_CTRL_BEBO_SHIFT (9U)
+/*! BEBO - Big-endian Byte Order.
+ */
+#define LCD_CTRL_BEBO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK)
+#define LCD_CTRL_BEPO_MASK (0x400U)
+#define LCD_CTRL_BEPO_SHIFT (10U)
+/*! BEPO - Big-Endian Pixel Ordering.
+ */
+#define LCD_CTRL_BEPO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK)
+#define LCD_CTRL_LCDPWR_MASK (0x800U)
+#define LCD_CTRL_LCDPWR_SHIFT (11U)
+/*! LCDPWR - LCD power enable.
+ */
+#define LCD_CTRL_LCDPWR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK)
+#define LCD_CTRL_LCDVCOMP_MASK (0x3000U)
+#define LCD_CTRL_LCDVCOMP_SHIFT (12U)
+/*! LCDVCOMP - LCD Vertical Compare Interrupt.
+ */
+#define LCD_CTRL_LCDVCOMP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK)
+#define LCD_CTRL_WATERMARK_MASK (0x10000U)
+#define LCD_CTRL_WATERMARK_SHIFT (16U)
+/*! WATERMARK - LCD DMA FIFO watermark level.
+ */
+#define LCD_CTRL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK)
+/*! @} */
+
+/*! @name INTMSK - Interrupt Mask register */
+/*! @{ */
+#define LCD_INTMSK_FUFIM_MASK (0x2U)
+#define LCD_INTMSK_FUFIM_SHIFT (1U)
+/*! FUFIM - FIFO underflow interrupt enable.
+ */
+#define LCD_INTMSK_FUFIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK)
+#define LCD_INTMSK_LNBUIM_MASK (0x4U)
+#define LCD_INTMSK_LNBUIM_SHIFT (2U)
+/*! LNBUIM - LCD next base address update interrupt enable.
+ */
+#define LCD_INTMSK_LNBUIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK)
+#define LCD_INTMSK_VCOMPIM_MASK (0x8U)
+#define LCD_INTMSK_VCOMPIM_SHIFT (3U)
+/*! VCOMPIM - Vertical compare interrupt enable.
+ */
+#define LCD_INTMSK_VCOMPIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK)
+#define LCD_INTMSK_BERIM_MASK (0x10U)
+#define LCD_INTMSK_BERIM_SHIFT (4U)
+/*! BERIM - AHB master error interrupt enable.
+ */
+#define LCD_INTMSK_BERIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK)
+/*! @} */
+
+/*! @name INTRAW - Raw Interrupt Status register */
+/*! @{ */
+#define LCD_INTRAW_FUFRIS_MASK (0x2U)
+#define LCD_INTRAW_FUFRIS_SHIFT (1U)
+/*! FUFRIS - FIFO underflow raw interrupt status.
+ */
+#define LCD_INTRAW_FUFRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK)
+#define LCD_INTRAW_LNBURIS_MASK (0x4U)
+#define LCD_INTRAW_LNBURIS_SHIFT (2U)
+/*! LNBURIS - LCD next address base update raw interrupt status.
+ */
+#define LCD_INTRAW_LNBURIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK)
+#define LCD_INTRAW_VCOMPRIS_MASK (0x8U)
+#define LCD_INTRAW_VCOMPRIS_SHIFT (3U)
+/*! VCOMPRIS - Vertical compare raw interrupt status.
+ */
+#define LCD_INTRAW_VCOMPRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK)
+#define LCD_INTRAW_BERRAW_MASK (0x10U)
+#define LCD_INTRAW_BERRAW_SHIFT (4U)
+/*! BERRAW - AHB master bus error raw interrupt status.
+ */
+#define LCD_INTRAW_BERRAW(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Masked Interrupt Status register */
+/*! @{ */
+#define LCD_INTSTAT_FUFMIS_MASK (0x2U)
+#define LCD_INTSTAT_FUFMIS_SHIFT (1U)
+/*! FUFMIS - FIFO underflow masked interrupt status.
+ */
+#define LCD_INTSTAT_FUFMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK)
+#define LCD_INTSTAT_LNBUMIS_MASK (0x4U)
+#define LCD_INTSTAT_LNBUMIS_SHIFT (2U)
+/*! LNBUMIS - LCD next address base update masked interrupt status.
+ */
+#define LCD_INTSTAT_LNBUMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK)
+#define LCD_INTSTAT_VCOMPMIS_MASK (0x8U)
+#define LCD_INTSTAT_VCOMPMIS_SHIFT (3U)
+/*! VCOMPMIS - Vertical compare masked interrupt status.
+ */
+#define LCD_INTSTAT_VCOMPMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK)
+#define LCD_INTSTAT_BERMIS_MASK (0x10U)
+#define LCD_INTSTAT_BERMIS_SHIFT (4U)
+/*! BERMIS - AHB master bus error masked interrupt status.
+ */
+#define LCD_INTSTAT_BERMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK)
+/*! @} */
+
+/*! @name INTCLR - Interrupt Clear register */
+/*! @{ */
+#define LCD_INTCLR_FUFIC_MASK (0x2U)
+#define LCD_INTCLR_FUFIC_SHIFT (1U)
+/*! FUFIC - FIFO underflow interrupt clear.
+ */
+#define LCD_INTCLR_FUFIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK)
+#define LCD_INTCLR_LNBUIC_MASK (0x4U)
+#define LCD_INTCLR_LNBUIC_SHIFT (2U)
+/*! LNBUIC - LCD next address base update interrupt clear.
+ */
+#define LCD_INTCLR_LNBUIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK)
+#define LCD_INTCLR_VCOMPIC_MASK (0x8U)
+#define LCD_INTCLR_VCOMPIC_SHIFT (3U)
+/*! VCOMPIC - Vertical compare interrupt clear.
+ */
+#define LCD_INTCLR_VCOMPIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK)
+#define LCD_INTCLR_BERIC_MASK (0x10U)
+#define LCD_INTCLR_BERIC_SHIFT (4U)
+/*! BERIC - AHB master error interrupt clear.
+ */
+#define LCD_INTCLR_BERIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK)
+/*! @} */
+
+/*! @name UPCURR - Upper Panel Current Address Value register */
+/*! @{ */
+#define LCD_UPCURR_LCDUPCURR_MASK (0xFFFFFFFFU)
+#define LCD_UPCURR_LCDUPCURR_SHIFT (0U)
+/*! LCDUPCURR - LCD Upper Panel Current Address.
+ */
+#define LCD_UPCURR_LCDUPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK)
+/*! @} */
+
+/*! @name LPCURR - Lower Panel Current Address Value register */
+/*! @{ */
+#define LCD_LPCURR_LCDLPCURR_MASK (0xFFFFFFFFU)
+#define LCD_LPCURR_LCDLPCURR_SHIFT (0U)
+/*! LCDLPCURR - LCD Lower Panel Current Address.
+ */
+#define LCD_LPCURR_LCDLPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK)
+/*! @} */
+
+/*! @name PAL - 256x16-bit Color Palette registers */
+/*! @{ */
+#define LCD_PAL_R04_0_MASK (0x1FU)
+#define LCD_PAL_R04_0_SHIFT (0U)
+/*! R04_0 - Red palette data.
+ */
+#define LCD_PAL_R04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK)
+#define LCD_PAL_G04_0_MASK (0x3E0U)
+#define LCD_PAL_G04_0_SHIFT (5U)
+/*! G04_0 - Green palette data.
+ */
+#define LCD_PAL_G04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK)
+#define LCD_PAL_B04_0_MASK (0x7C00U)
+#define LCD_PAL_B04_0_SHIFT (10U)
+/*! B04_0 - Blue palette data.
+ */
+#define LCD_PAL_B04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK)
+#define LCD_PAL_I0_MASK (0x8000U)
+#define LCD_PAL_I0_SHIFT (15U)
+/*! I0 - Intensity / unused bit.
+ */
+#define LCD_PAL_I0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK)
+#define LCD_PAL_R14_0_MASK (0x1F0000U)
+#define LCD_PAL_R14_0_SHIFT (16U)
+/*! R14_0 - Red palette data.
+ */
+#define LCD_PAL_R14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK)
+#define LCD_PAL_G14_0_MASK (0x3E00000U)
+#define LCD_PAL_G14_0_SHIFT (21U)
+/*! G14_0 - Green palette data.
+ */
+#define LCD_PAL_G14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK)
+#define LCD_PAL_B14_0_MASK (0x7C000000U)
+#define LCD_PAL_B14_0_SHIFT (26U)
+/*! B14_0 - Blue palette data.
+ */
+#define LCD_PAL_B14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK)
+#define LCD_PAL_I1_MASK (0x80000000U)
+#define LCD_PAL_I1_SHIFT (31U)
+/*! I1 - Intensity / unused bit.
+ */
+#define LCD_PAL_I1(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK)
+/*! @} */
+
+/* The count of LCD_PAL */
+#define LCD_PAL_COUNT (128U)
+
+/*! @name CRSR_IMG - Cursor Image registers */
+/*! @{ */
+#define LCD_CRSR_IMG_CRSR_IMG_MASK (0xFFFFFFFFU)
+#define LCD_CRSR_IMG_CRSR_IMG_SHIFT (0U)
+/*! CRSR_IMG - Cursor Image data.
+ */
+#define LCD_CRSR_IMG_CRSR_IMG(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK)
+/*! @} */
+
+/* The count of LCD_CRSR_IMG */
+#define LCD_CRSR_IMG_COUNT (256U)
+
+/*! @name CRSR_CTRL - Cursor Control register */
+/*! @{ */
+#define LCD_CRSR_CTRL_CRSRON_MASK (0x1U)
+#define LCD_CRSR_CTRL_CRSRON_SHIFT (0U)
+/*! CRSRON - Cursor enable.
+ */
+#define LCD_CRSR_CTRL_CRSRON(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK)
+#define LCD_CRSR_CTRL_CRSRNUM1_0_MASK (0x30U)
+#define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT (4U)
+/*! CRSRNUM1_0 - Cursor image number.
+ */
+#define LCD_CRSR_CTRL_CRSRNUM1_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK)
+/*! @} */
+
+/*! @name CRSR_CFG - Cursor Configuration register */
+/*! @{ */
+#define LCD_CRSR_CFG_CRSRSIZE_MASK (0x1U)
+#define LCD_CRSR_CFG_CRSRSIZE_SHIFT (0U)
+/*! CRSRSIZE - Cursor size selection.
+ */
+#define LCD_CRSR_CFG_CRSRSIZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK)
+#define LCD_CRSR_CFG_FRAMESYNC_MASK (0x2U)
+#define LCD_CRSR_CFG_FRAMESYNC_SHIFT (1U)
+/*! FRAMESYNC - Cursor frame synchronization type.
+ */
+#define LCD_CRSR_CFG_FRAMESYNC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK)
+/*! @} */
+
+/*! @name CRSR_PAL0 - Cursor Palette register 0 */
+/*! @{ */
+#define LCD_CRSR_PAL0_RED_MASK (0xFFU)
+#define LCD_CRSR_PAL0_RED_SHIFT (0U)
+/*! RED - Red color component.
+ */
+#define LCD_CRSR_PAL0_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK)
+#define LCD_CRSR_PAL0_GREEN_MASK (0xFF00U)
+#define LCD_CRSR_PAL0_GREEN_SHIFT (8U)
+/*! GREEN - Green color component.
+ */
+#define LCD_CRSR_PAL0_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK)
+#define LCD_CRSR_PAL0_BLUE_MASK (0xFF0000U)
+#define LCD_CRSR_PAL0_BLUE_SHIFT (16U)
+/*! BLUE - Blue color component.
+ */
+#define LCD_CRSR_PAL0_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK)
+/*! @} */
+
+/*! @name CRSR_PAL1 - Cursor Palette register 1 */
+/*! @{ */
+#define LCD_CRSR_PAL1_RED_MASK (0xFFU)
+#define LCD_CRSR_PAL1_RED_SHIFT (0U)
+/*! RED - Red color component.
+ */
+#define LCD_CRSR_PAL1_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK)
+#define LCD_CRSR_PAL1_GREEN_MASK (0xFF00U)
+#define LCD_CRSR_PAL1_GREEN_SHIFT (8U)
+/*! GREEN - Green color component.
+ */
+#define LCD_CRSR_PAL1_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK)
+#define LCD_CRSR_PAL1_BLUE_MASK (0xFF0000U)
+#define LCD_CRSR_PAL1_BLUE_SHIFT (16U)
+/*! BLUE - Blue color component.
+ */
+#define LCD_CRSR_PAL1_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK)
+/*! @} */
+
+/*! @name CRSR_XY - Cursor XY Position register */
+/*! @{ */
+#define LCD_CRSR_XY_CRSRX_MASK (0x3FFU)
+#define LCD_CRSR_XY_CRSRX_SHIFT (0U)
+/*! CRSRX - X ordinate of the cursor origin measured in pixels.
+ */
+#define LCD_CRSR_XY_CRSRX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK)
+#define LCD_CRSR_XY_CRSRY_MASK (0x3FF0000U)
+#define LCD_CRSR_XY_CRSRY_SHIFT (16U)
+/*! CRSRY - Y ordinate of the cursor origin measured in pixels.
+ */
+#define LCD_CRSR_XY_CRSRY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK)
+/*! @} */
+
+/*! @name CRSR_CLIP - Cursor Clip Position register */
+/*! @{ */
+#define LCD_CRSR_CLIP_CRSRCLIPX_MASK (0x3FU)
+#define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT (0U)
+/*! CRSRCLIPX - Cursor clip position for X direction.
+ */
+#define LCD_CRSR_CLIP_CRSRCLIPX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK)
+#define LCD_CRSR_CLIP_CRSRCLIPY_MASK (0x3F00U)
+#define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT (8U)
+/*! CRSRCLIPY - Cursor clip position for Y direction.
+ */
+#define LCD_CRSR_CLIP_CRSRCLIPY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK)
+/*! @} */
+
+/*! @name CRSR_INTMSK - Cursor Interrupt Mask register */
+/*! @{ */
+#define LCD_CRSR_INTMSK_CRSRIM_MASK (0x1U)
+#define LCD_CRSR_INTMSK_CRSRIM_SHIFT (0U)
+/*! CRSRIM - Cursor interrupt mask.
+ */
+#define LCD_CRSR_INTMSK_CRSRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK)
+/*! @} */
+
+/*! @name CRSR_INTCLR - Cursor Interrupt Clear register */
+/*! @{ */
+#define LCD_CRSR_INTCLR_CRSRIC_MASK (0x1U)
+#define LCD_CRSR_INTCLR_CRSRIC_SHIFT (0U)
+/*! CRSRIC - Cursor interrupt clear.
+ */
+#define LCD_CRSR_INTCLR_CRSRIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK)
+/*! @} */
+
+/*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */
+/*! @{ */
+#define LCD_CRSR_INTRAW_CRSRRIS_MASK (0x1U)
+#define LCD_CRSR_INTRAW_CRSRRIS_SHIFT (0U)
+/*! CRSRRIS - Cursor raw interrupt status.
+ */
+#define LCD_CRSR_INTRAW_CRSRRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK)
+/*! @} */
+
+/*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */
+/*! @{ */
+#define LCD_CRSR_INTSTAT_CRSRMIS_MASK (0x1U)
+#define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT (0U)
+/*! CRSRMIS - Cursor masked interrupt status.
+ */
+#define LCD_CRSR_INTSTAT_CRSRMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/** Peripheral LCD base address */
+#define LCD_BASE (0x40083000u)
+/** Peripheral LCD base pointer */
+#define LCD ((LCD_Type *)LCD_BASE)
+/** Array initializer of LCD peripheral base addresses */
+#define LCD_BASE_ADDRS { LCD_BASE }
+/** Array initializer of LCD peripheral base pointers */
+#define LCD_BASE_PTRS { LCD }
+/** Interrupt vectors for the LCD peripheral type */
+#define LCD_IRQS { LCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MRT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
+ * @{
+ */
+
+/** MRT - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x10 */
+ __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
+ __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
+ __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
+ __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
+ } CHANNEL[4];
+ uint8_t RESERVED_0[176];
+ __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
+ __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
+ __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
+} MRT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MRT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Register_Masks MRT Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
+/*! @{ */
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
+/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT
+ * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to
+ * this bit field starts the timer immediately. If the timer is running, writing a zero to this
+ * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
+ * stops at the end of the time interval.
+ */
+#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
+#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
+/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.
+ * This bit is write-only. Reading this bit always returns 0.
+ * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the
+ * time interval if the repeat mode is selected.
+ * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
+ */
+#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_INTVAL */
+#define MRT_CHANNEL_INTVAL_COUNT (4U)
+
+/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
+/*! @{ */
+#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
+/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn
+ * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval
+ * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn
+ * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields
+ * returns -1 (0x00FF FFFF).
+ */
+#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_TIMER */
+#define MRT_CHANNEL_TIMER_COUNT (4U)
+
+/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
+/*! @{ */
+#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
+/*! INTEN - Enable the TIMERn interrupt.
+ * 0b0..Disabled. TIMERn interrupt is disabled.
+ * 0b1..Enabled. TIMERn interrupt is enabled.
+ */
+#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
+#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
+#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
+/*! MODE - Selects timer mode.
+ * 0b00..Repeat interrupt mode.
+ * 0b01..One-shot interrupt mode.
+ * 0b10..One-shot stall mode.
+ * 0b11..Reserved.
+ */
+#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_CTRL */
+#define MRT_CHANNEL_CTRL_COUNT (4U)
+
+/*! @name CHANNEL_STAT - MRT Status register. */
+/*! @{ */
+#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
+/*! INTFLAG - Monitors the interrupt flag.
+ * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
+ * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If
+ * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt
+ * are raised. Writing a 1 to this bit clears the interrupt request.
+ */
+#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
+#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
+#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
+/*! RUN - Indicates the state of TIMERn. This bit is read-only.
+ * 0b0..Idle state. TIMERn is stopped.
+ * 0b1..Running. TIMERn is running.
+ */
+#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
+#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)
+#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)
+/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG
+ * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating
+ * modes.
+ * 0b0..This channel is not in use.
+ * 0b1..This channel is in use.
+ */
+#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_STAT */
+#define MRT_CHANNEL_STAT_COUNT (4U)
+
+/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
+/*! @{ */
+#define MRT_MODCFG_NOC_MASK (0xFU)
+#define MRT_MODCFG_NOC_SHIFT (0U)
+/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)
+ */
+#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
+#define MRT_MODCFG_NOB_MASK (0x1F0U)
+#define MRT_MODCFG_NOB_SHIFT (4U)
+/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.)
+ */
+#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
+#define MRT_MODCFG_MULTITASK_MASK (0x80000000U)
+#define MRT_MODCFG_MULTITASK_SHIFT (31U)
+/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
+ * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
+ * 0b1..Multi-task mode.
+ */
+#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
+/*! @} */
+
+/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
+/*! @{ */
+#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
+#define MRT_IDLE_CH_CHAN_SHIFT (4U)
+/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
+ * positioned such that it can be used as an offset from the MRT base address in order to access
+ * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See
+ * text above for more details.
+ */
+#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
+/*! @} */
+
+/*! @name IRQ_FLAG - Global interrupt flag register */
+/*! @{ */
+#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
+/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
+ * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
+ * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
+ * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global
+ * interrupt are raised. Writing a 1 to this bit clears the interrupt request.
+ */
+#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
+#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
+/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.
+ */
+#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
+#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
+/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0.
+ */
+#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
+#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
+/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0.
+ */
+#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MRT_Register_Masks */
+
+
+/* MRT - Peripheral instance base addresses */
+/** Peripheral MRT0 base address */
+#define MRT0_BASE (0x4000D000u)
+/** Peripheral MRT0 base pointer */
+#define MRT0 ((MRT_Type *)MRT0_BASE)
+/** Array initializer of MRT peripheral base addresses */
+#define MRT_BASE_ADDRS { MRT0_BASE }
+/** Array initializer of MRT peripheral base pointers */
+#define MRT_BASE_PTRS { MRT0 }
+/** Interrupt vectors for the MRT peripheral type */
+#define MRT_IRQS { MRT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MRT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OTPC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer
+ * @{
+ */
+
+/** OTPC - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[16];
+ __I uint32_t AESKEY[8]; /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */
+ __I uint32_t ECRP; /**< ECRP options., offset: 0x30 */
+ uint8_t RESERVED_1[4];
+ __I uint32_t USER0; /**< User application specific options., offset: 0x38 */
+ __I uint32_t USER1; /**< User application specific options., offset: 0x3C */
+} OTPC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OTPC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTPC_Register_Masks OTPC Register Masks
+ * @{
+ */
+
+/*! @name AESKEY - Register for reading the AES key. */
+/*! @{ */
+#define OTPC_AESKEY_KEY_MASK (0xFFFFFFFFU)
+#define OTPC_AESKEY_KEY_SHIFT (0U)
+/*! KEY - AES key.
+ */
+#define OTPC_AESKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK)
+/*! @} */
+
+/* The count of OTPC_AESKEY */
+#define OTPC_AESKEY_COUNT (8U)
+
+/*! @name ECRP - ECRP options. */
+/*! @{ */
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK (0x10U)
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT (4U)
+/*! CRP_MASS_ERASE_DISABLE - Disable or enable CRP mass erase.
+ */
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK (0x20U)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT (5U)
+/*! IAP_PROTECTION_ENABLE - This bit controls the ability to enable checking for ECRP in IAP functions.
+ */
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK (0x40U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT (6U)
+/*! CRP_ISP_DISABLE_PIN - This bit controls the ability to enter ISP mode using the ISP pin.
+ */
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK (0x80U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT (7U)
+/*! CRP_ISP_DISABLE_IAP - This bit controls the ability to re-invoke ISP using IAP routines.
+ */
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK)
+#define OTPC_ECRP_CRP_ALLOW_ZERO_MASK (0x200U)
+#define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT (9U)
+/*! CRP_ALLOW_ZERO - This bit controls how 0 is treated when read as a ECRP value..
+ */
+#define OTPC_ECRP_CRP_ALLOW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK)
+#define OTPC_ECRP_JTAG_DISABLE_MASK (0x80000000U)
+#define OTPC_ECRP_JTAG_DISABLE_SHIFT (31U)
+/*! JTAG_DISABLE - 0 => Enable SWD/JTAG; 1 => Disable SWD/JTAG..
+ */
+#define OTPC_ECRP_JTAG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK)
+/*! @} */
+
+/*! @name USER0 - User application specific options. */
+/*! @{ */
+#define OTPC_USER0_USER0_MASK (0xFFFFFFFFU)
+#define OTPC_USER0_USER0_SHIFT (0U)
+/*! USER0 - User application specific option.
+ */
+#define OTPC_USER0_USER0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK)
+/*! @} */
+
+/*! @name USER1 - User application specific options. */
+/*! @{ */
+#define OTPC_USER1_USER1_MASK (0xFFFFFFFFU)
+#define OTPC_USER1_USER1_SHIFT (0U)
+/*! USER1 - User application specific option.
+ */
+#define OTPC_USER1_USER1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group OTPC_Register_Masks */
+
+
+/* OTPC - Peripheral instance base addresses */
+/** Peripheral OTPC base address */
+#define OTPC_BASE (0x40015000u)
+/** Peripheral OTPC base pointer */
+#define OTPC ((OTPC_Type *)OTPC_BASE)
+/** Array initializer of OTPC peripheral base addresses */
+#define OTPC_BASE_ADDRS { OTPC_BASE }
+/** Array initializer of OTPC peripheral base pointers */
+#define OTPC_BASE_PTRS { OTPC }
+
+/*!
+ * @}
+ */ /* end of group OTPC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PINT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
+ * @{
+ */
+
+/** PINT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
+ __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
+ __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
+ __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
+ __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
+ __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
+ __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
+ __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
+ __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
+ __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
+ __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
+ __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
+ __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
+} PINT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PINT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Register_Masks PINT Register Masks
+ * @{
+ */
+
+/*! @name ISEL - Pin Interrupt Mode register */
+/*! @{ */
+#define PINT_ISEL_PMODE_MASK (0xFFU)
+#define PINT_ISEL_PMODE_SHIFT (0U)
+/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt
+ * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
+ */
+#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
+/*! @} */
+
+/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
+/*! @{ */
+#define PINT_IENR_ENRL_MASK (0xFFU)
+#define PINT_IENR_ENRL_SHIFT (0U)
+/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the
+ * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable
+ * rising edge or level interrupt.
+ */
+#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
+/*! @} */
+
+/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
+/*! @{ */
+#define PINT_SIENR_SETENRL_MASK (0xFFU)
+#define PINT_SIENR_SETENRL_SHIFT (0U)
+/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n
+ * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
+ */
+#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
+/*! @} */
+
+/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
+/*! @{ */
+#define PINT_CIENR_CENRL_MASK (0xFFU)
+#define PINT_CIENR_CENRL_SHIFT (0U)
+/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit
+ * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level
+ * interrupt.
+ */
+#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
+/*! @} */
+
+/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
+/*! @{ */
+#define PINT_IENF_ENAF_MASK (0xFFU)
+#define PINT_IENF_ENAF_SHIFT (0U)
+/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt.
+ * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt
+ * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active
+ * interrupt level HIGH.
+ */
+#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
+/*! @} */
+
+/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
+/*! @{ */
+#define PINT_SIENF_SETENAF_MASK (0xFFU)
+#define PINT_SIENF_SETENAF_SHIFT (0U)
+/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n
+ * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable
+ * falling edge interrupt.
+ */
+#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
+/*! @} */
+
+/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
+/*! @{ */
+#define PINT_CIENF_CENAF_MASK (0xFFU)
+#define PINT_CIENF_CENAF_SHIFT (0U)
+/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n
+ * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or
+ * falling edge interrupt disabled.
+ */
+#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
+/*! @} */
+
+/*! @name RISE - Pin interrupt rising edge register */
+/*! @{ */
+#define PINT_RISE_RDET_MASK (0xFFU)
+#define PINT_RISE_RDET_SHIFT (0U)
+/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read
+ * 0: No rising edge has been detected on this pin since Reset or the last time a one was written
+ * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the
+ * last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
+ */
+#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
+/*! @} */
+
+/*! @name FALL - Pin interrupt falling edge register */
+/*! @{ */
+#define PINT_FALL_FDET_MASK (0xFFU)
+#define PINT_FALL_FDET_SHIFT (0U)
+/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read
+ * 0: No falling edge has been detected on this pin since Reset or the last time a one was
+ * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or
+ * the last time a one was written to this bit. Write 1: clear falling edge detection for this
+ * pin.
+ */
+#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
+/*! @} */
+
+/*! @name IST - Pin interrupt status register */
+/*! @{ */
+#define PINT_IST_PSTAT_MASK (0xFFU)
+#define PINT_IST_PSTAT_SHIFT (0U)
+/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts
+ * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for
+ * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this
+ * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin.
+ * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
+ */
+#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
+/*! @} */
+
+/*! @name PMCTRL - Pattern match interrupt control register */
+/*! @{ */
+#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
+/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
+ * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
+ * 0b1..Pattern match. Interrupts are driven in response to pattern matches.
+ */
+#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
+#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
+#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
+/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
+ * 0b0..Disabled. RXEV output to the CPU is disabled.
+ * 0b1..Enabled. RXEV output to the CPU is enabled.
+ */
+#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
+#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
+#define PINT_PMCTRL_PMAT_SHIFT (24U)
+/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field
+ * indicates that the corresponding product term is matched by the current state of the appropriate
+ * inputs.
+ */
+#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
+/*! @} */
+
+/*! @name PMSRC - Pattern match interrupt bit-slice source register */
+/*! @{ */
+#define PINT_PMSRC_SRC0_MASK (0x700U)
+#define PINT_PMSRC_SRC0_SHIFT (8U)
+/*! SRC0 - Selects the input source for bit slice 0
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
+ */
+#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
+#define PINT_PMSRC_SRC1_MASK (0x3800U)
+#define PINT_PMSRC_SRC1_SHIFT (11U)
+/*! SRC1 - Selects the input source for bit slice 1
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
+ */
+#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
+#define PINT_PMSRC_SRC2_MASK (0x1C000U)
+#define PINT_PMSRC_SRC2_SHIFT (14U)
+/*! SRC2 - Selects the input source for bit slice 2
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
+ */
+#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
+#define PINT_PMSRC_SRC3_MASK (0xE0000U)
+#define PINT_PMSRC_SRC3_SHIFT (17U)
+/*! SRC3 - Selects the input source for bit slice 3
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
+ */
+#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
+#define PINT_PMSRC_SRC4_MASK (0x700000U)
+#define PINT_PMSRC_SRC4_SHIFT (20U)
+/*! SRC4 - Selects the input source for bit slice 4
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
+ */
+#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
+#define PINT_PMSRC_SRC5_MASK (0x3800000U)
+#define PINT_PMSRC_SRC5_SHIFT (23U)
+/*! SRC5 - Selects the input source for bit slice 5
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
+ */
+#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
+#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
+#define PINT_PMSRC_SRC6_SHIFT (26U)
+/*! SRC6 - Selects the input source for bit slice 6
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
+ */
+#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
+#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
+#define PINT_PMSRC_SRC7_SHIFT (29U)
+/*! SRC7 - Selects the input source for bit slice 7
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
+ */
+#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
+/*! @} */
+
+/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
+/*! @{ */
+#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
+/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
+ * 0b0..No effect. Slice 0 is not an endpoint.
+ * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
+#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
+/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
+ * 0b0..No effect. Slice 1 is not an endpoint.
+ * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
+#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
+/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
+ * 0b0..No effect. Slice 2 is not an endpoint.
+ * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
+#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
+/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
+ * 0b0..No effect. Slice 3 is not an endpoint.
+ * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
+#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
+/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
+ * 0b0..No effect. Slice 4 is not an endpoint.
+ * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
+#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
+/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
+ * 0b0..No effect. Slice 5 is not an endpoint.
+ * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
+#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
+/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
+ * 0b0..No effect. Slice 6 is not an endpoint.
+ * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
+#define PINT_PMCFG_CFG0_MASK (0x700U)
+#define PINT_PMCFG_CFG0_SHIFT (8U)
+/*! CFG0 - Specifies the match contribution condition for bit slice 0.
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ * cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ * is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
+#define PINT_PMCFG_CFG1_MASK (0x3800U)
+#define PINT_PMCFG_CFG1_SHIFT (11U)
+/*! CFG1 - Specifies the match contribution condition for bit slice 1.
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ * cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ * is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
+#define PINT_PMCFG_CFG2_MASK (0x1C000U)
+#define PINT_PMCFG_CFG2_SHIFT (14U)
+/*! CFG2 - Specifies the match contribution condition for bit slice 2.
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ * cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ * is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
+#define PINT_PMCFG_CFG3_MASK (0xE0000U)
+#define PINT_PMCFG_CFG3_SHIFT (17U)
+/*! CFG3 - Specifies the match contribution condition for bit slice 3.
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ * cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ * is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
+#define PINT_PMCFG_CFG4_MASK (0x700000U)
+#define PINT_PMCFG_CFG4_SHIFT (20U)
+/*! CFG4 - Specifies the match contribution condition for bit slice 4.
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ * cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ * is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
+#define PINT_PMCFG_CFG5_MASK (0x3800000U)
+#define PINT_PMCFG_CFG5_SHIFT (23U)
+/*! CFG5 - Specifies the match contribution condition for bit slice 5.
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ * cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ * is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
+#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
+#define PINT_PMCFG_CFG6_SHIFT (26U)
+/*! CFG6 - Specifies the match contribution condition for bit slice 6.
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ * cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ * is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
+#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
+#define PINT_PMCFG_CFG7_SHIFT (29U)
+/*! CFG7 - Specifies the match contribution condition for bit slice 7.
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
+ * PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
+ * cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
+ * is cleared after one clock cycle.
+ */
+#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PINT_Register_Masks */
+
+
+/* PINT - Peripheral instance base addresses */
+/** Peripheral PINT base address */
+#define PINT_BASE (0x40004000u)
+/** Peripheral PINT base pointer */
+#define PINT ((PINT_Type *)PINT_BASE)
+/** Array initializer of PINT peripheral base addresses */
+#define PINT_BASE_ADDRS { PINT_BASE }
+/** Array initializer of PINT peripheral base pointers */
+#define PINT_BASE_PTRS { PINT }
+/** Interrupt vectors for the PINT peripheral type */
+#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer
+ * @{
+ */
+
+/** RIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t COMPVAL; /**< Compare value LSB register, offset: 0x0 */
+ __IO uint32_t MASK; /**< Mask LSB register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< Control register, offset: 0x8 */
+ __IO uint32_t COUNTER; /**< Counter LSB register, offset: 0xC */
+ __IO uint32_t COMPVAL_H; /**< Compare value MSB register, offset: 0x10 */
+ __IO uint32_t MASK_H; /**< Mask MSB register, offset: 0x14 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t COUNTER_H; /**< Counter MSB register, offset: 0x1C */
+} RIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RIT_Register_Masks RIT Register Masks
+ * @{
+ */
+
+/*! @name COMPVAL - Compare value LSB register */
+/*! @{ */
+#define RIT_COMPVAL_RICOMP_MASK (0xFFFFFFFFU)
+#define RIT_COMPVAL_RICOMP_SHIFT (0U)
+/*! RICOMP - .
+ */
+#define RIT_COMPVAL_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK)
+/*! @} */
+
+/*! @name MASK - Mask LSB register */
+/*! @{ */
+#define RIT_MASK_RIMASK_MASK (0xFFFFFFFFU)
+#define RIT_MASK_RIMASK_SHIFT (0U)
+/*! RIMASK - Mask register.
+ */
+#define RIT_MASK_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK)
+/*! @} */
+
+/*! @name CTRL - Control register */
+/*! @{ */
+#define RIT_CTRL_RITINT_MASK (0x1U)
+#define RIT_CTRL_RITINT_SHIFT (0U)
+/*! RITINT - Interrupt flag.
+ */
+#define RIT_CTRL_RITINT(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK)
+#define RIT_CTRL_RITENCLR_MASK (0x2U)
+#define RIT_CTRL_RITENCLR_SHIFT (1U)
+/*! RITENCLR - Timer enable clear.
+ */
+#define RIT_CTRL_RITENCLR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK)
+#define RIT_CTRL_RITENBR_MASK (0x4U)
+#define RIT_CTRL_RITENBR_SHIFT (2U)
+/*! RITENBR - Timer enable for debug.
+ */
+#define RIT_CTRL_RITENBR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK)
+#define RIT_CTRL_RITEN_MASK (0x8U)
+#define RIT_CTRL_RITEN_SHIFT (3U)
+/*! RITEN - Timer enable.
+ */
+#define RIT_CTRL_RITEN(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK)
+/*! @} */
+
+/*! @name COUNTER - Counter LSB register */
+/*! @{ */
+#define RIT_COUNTER_RICOUNTER_MASK (0xFFFFFFFFU)
+#define RIT_COUNTER_RICOUNTER_SHIFT (0U)
+/*! RICOUNTER - 32 LSBs of the up counter.
+ */
+#define RIT_COUNTER_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK)
+/*! @} */
+
+/*! @name COMPVAL_H - Compare value MSB register */
+/*! @{ */
+#define RIT_COMPVAL_H_RICOMP_MASK (0xFFFFU)
+#define RIT_COMPVAL_H_RICOMP_SHIFT (0U)
+/*! RICOMP - Compare value MSB register.
+ */
+#define RIT_COMPVAL_H_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK)
+/*! @} */
+
+/*! @name MASK_H - Mask MSB register */
+/*! @{ */
+#define RIT_MASK_H_RIMASK_MASK (0xFFFFU)
+#define RIT_MASK_H_RIMASK_SHIFT (0U)
+/*! RIMASK - Mask register.
+ */
+#define RIT_MASK_H_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK)
+/*! @} */
+
+/*! @name COUNTER_H - Counter MSB register */
+/*! @{ */
+#define RIT_COUNTER_H_RICOUNTER_MASK (0xFFFFU)
+#define RIT_COUNTER_H_RICOUNTER_SHIFT (0U)
+/*! RICOUNTER - 16 LSBs of the up counter.
+ */
+#define RIT_COUNTER_H_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RIT_Register_Masks */
+
+
+/* RIT - Peripheral instance base addresses */
+/** Peripheral RIT base address */
+#define RIT_BASE (0x4002D000u)
+/** Peripheral RIT base pointer */
+#define RIT ((RIT_Type *)RIT_BASE)
+/** Array initializer of RIT peripheral base addresses */
+#define RIT_BASE_ADDRS { RIT_BASE }
+/** Array initializer of RIT peripheral base pointers */
+#define RIT_BASE_PTRS { RIT }
+/** Interrupt vectors for the RIT peripheral type */
+#define RIT_IRQS { RIT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */
+ __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */
+ __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */
+ __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */
+ uint8_t RESERVED_0[48];
+ __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - RTC control register */
+/*! @{ */
+#define RTC_CTRL_SWRESET_MASK (0x1U)
+#define RTC_CTRL_SWRESET_SHIFT (0U)
+/*! SWRESET - Software reset control
+ * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.
+ * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value
+ * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes
+ * to set any of the other bits within this register. Do not attempt to write to any bits of this register at
+ * the same time that the reset bit is being cleared.
+ */
+#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
+#define RTC_CTRL_ALARM1HZ_MASK (0x4U)
+#define RTC_CTRL_ALARM1HZ_SHIFT (2U)
+/*! ALARM1HZ - RTC 1 Hz timer alarm flag status.
+ * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.
+ * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt
+ * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.
+ */
+#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
+#define RTC_CTRL_WAKE1KHZ_MASK (0x8U)
+#define RTC_CTRL_WAKE1KHZ_SHIFT (3U)
+/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status.
+ * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
+ * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up
+ * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.
+ */
+#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
+#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U)
+#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U)
+/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down.
+ * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.
+ * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.
+ */
+#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
+#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U)
+#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U)
+/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down.
+ * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
+ * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.
+ */
+#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
+#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)
+/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz
+ * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).
+ * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
+ * 0b1..Enable. The 1 kHz RTC timer is enabled.
+ */
+#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
+#define RTC_CTRL_RTC_EN_MASK (0x80U)
+#define RTC_CTRL_RTC_EN_SHIFT (7U)
+/*! RTC_EN - RTC enable.
+ * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should
+ * be 0 when writing to load a value in the RTC counter register.
+ * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate
+ * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the
+ * high-resolution, 1 kHz clock, set bit 6 in this register.
+ */
+#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
+#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U)
+#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U)
+/*! RTC_OSC_PD - RTC oscillator power-down control.
+ * 0b0..See RTC_OSC_BYPASS
+ * 0b1..RTC oscillator is powered-down.
+ */
+#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
+/*! @} */
+
+/*! @name MATCH - RTC match register */
+/*! @{ */
+#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)
+#define RTC_MATCH_MATVAL_SHIFT (0U)
+/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the
+ * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.
+ */
+#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
+/*! @} */
+
+/*! @name COUNT - RTC counter register */
+/*! @{ */
+#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU)
+#define RTC_COUNT_VAL_SHIFT (0U)
+/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial
+ * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC
+ * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this
+ * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after
+ * the RTC_EN bit is set.
+ */
+#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
+/*! @} */
+
+/*! @name WAKE - High-resolution/wake-up timer control register */
+/*! @{ */
+#define RTC_WAKE_VAL_MASK (0xFFFFU)
+#define RTC_WAKE_VAL_SHIFT (0U)
+/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads
+ * a start count value into the wake-up timer and initializes a count-down sequence. Do not write
+ * to this register while counting is in progress.
+ */
+#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
+/*! @} */
+
+/*! @name GPREG - General Purpose register */
+/*! @{ */
+#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU)
+#define RTC_GPREG_GPDATA_SHIFT (0U)
+/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
+ */
+#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
+/*! @} */
+
+/* The count of RTC_GPREG */
+#define RTC_GPREG_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4002C000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SCT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
+ * @{
+ */
+
+/** SCT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
+ __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
+ __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
+ __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
+ __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
+ __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
+ uint8_t RESERVED_0[40];
+ __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
+ __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
+ __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
+ __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
+ __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
+ __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
+ __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
+ __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */
+ __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */
+ uint8_t RESERVED_1[140];
+ __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
+ __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
+ __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
+ __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
+ union { /* offset: 0x100 */
+ __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
+ __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
+ };
+ uint8_t RESERVED_2[192];
+ union { /* offset: 0x200 */
+ __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
+ __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
+ };
+ uint8_t RESERVED_3[192];
+ struct { /* offset: 0x300, array step: 0x8 */
+ __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
+ __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
+ } EV[16];
+ uint8_t RESERVED_4[384];
+ struct { /* offset: 0x500, array step: 0x8 */
+ __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
+ __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
+ } OUT[10];
+} SCT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SCT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Register_Masks SCT Register Masks
+ * @{
+ */
+
+/*! @name CONFIG - SCT configuration register */
+/*! @{ */
+#define SCT_CONFIG_UNIFY_MASK (0x1U)
+#define SCT_CONFIG_UNIFY_SHIFT (0U)
+/*! UNIFY - SCT operation
+ * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
+ * 0b1..The SCT operates as a unified 32-bit counter.
+ */
+#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
+#define SCT_CONFIG_CLKMODE_MASK (0x6U)
+#define SCT_CONFIG_CLKMODE_SHIFT (1U)
+/*! CLKMODE - SCT clock mode
+ * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
+ * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
+ * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
+ * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
+ * high-performance, sampled-clock mode.
+ * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the
+ * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
+ * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
+ * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
+ * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
+ * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
+ * the system clock.
+ */
+#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
+#define SCT_CONFIG_CKSEL_MASK (0x78U)
+#define SCT_CONFIG_CKSEL_SHIFT (3U)
+/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent
+ * on the CLKMODE bit selection in this register.
+ * 0b0000..Rising edges on input 0.
+ * 0b0001..Falling edges on input 0.
+ * 0b0010..Rising edges on input 1.
+ * 0b0011..Falling edges on input 1.
+ * 0b0100..Rising edges on input 2.
+ * 0b0101..Falling edges on input 2.
+ * 0b0110..Rising edges on input 3.
+ * 0b0111..Falling edges on input 3.
+ * 0b1000..Rising edges on input 4.
+ * 0b1001..Falling edges on input 4.
+ * 0b1010..Rising edges on input 5.
+ * 0b1011..Falling edges on input 5.
+ * 0b1100..Rising edges on input 6.
+ * 0b1101..Falling edges on input 6.
+ * 0b1110..Rising edges on input 7.
+ * 0b1111..Falling edges on input 7.
+ */
+#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
+#define SCT_CONFIG_NORELOAD_L_MASK (0x80U)
+#define SCT_CONFIG_NORELOAD_L_SHIFT (7U)
+/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their
+ * respective reload registers. Setting this bit eliminates the need to write to the reload
+ * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any
+ * time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
+ */
+#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
+#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
+#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
+/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their
+ * respective reload registers. Setting this bit eliminates the need to write to the reload
+ * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at
+ * any time. This bit is not used when the UNIFY bit is set.
+ */
+#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
+#define SCT_CONFIG_INSYNC_MASK (0x1FE00U)
+#define SCT_CONFIG_INSYNC_SHIFT (9U)
+/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all
+ * other bits are reserved. A 1 in one of these bits subjects the corresponding input to
+ * synchronization to the SCT clock, before it is used to create an event. If an input is known to
+ * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note:
+ * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input
+ * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation.
+ * It does not apply to the clock input specified in the CKSEL field.
+ */
+#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
+#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
+/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto
+ * LIMIT condition without the need to define an associated event. As with any LIMIT event, this
+ * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change
+ * the direction of count in bi-directional mode. Software can write to set or clear this bit at
+ * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
+ */
+#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
+#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
+/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a
+ * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event,
+ * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to
+ * change the direction of count in bi-directional mode. Software can write to set or clear this bit
+ * at any time. This bit is not used when the UNIFY bit is set.
+ */
+#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
+/*! @} */
+
+/*! @name CTRL - SCT control register */
+/*! @{ */
+#define SCT_CTRL_DOWN_L_MASK (0x1U)
+#define SCT_CTRL_DOWN_L_SHIFT (0U)
+/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
+ * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
+ * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
+ */
+#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
+#define SCT_CTRL_STOP_L_MASK (0x2U)
+#define SCT_CTRL_STOP_L_SHIFT (1U)
+/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
+ * related to the counter can occur. If a designated start event occurs, this bit is cleared and
+ * counting resumes.
+ */
+#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
+#define SCT_CTRL_HALT_L_MASK (0x4U)
+#define SCT_CTRL_HALT_L_SHIFT (2U)
+/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
+ * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
+ * remove the halt condition while keeping the SCT in the stop condition (not running) with a
+ * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
+ * only software can clear this bit to restore counter operation. This bit is set on reset.
+ */
+#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
+#define SCT_CTRL_CLRCTR_L_MASK (0x8U)
+#define SCT_CTRL_CLRCTR_L_SHIFT (3U)
+/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
+ */
+#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
+#define SCT_CTRL_BIDIR_L_MASK (0x10U)
+#define SCT_CTRL_BIDIR_L_SHIFT (4U)
+/*! BIDIR_L - L or unified counter direction select
+ * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
+ * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
+#define SCT_CTRL_PRE_L_MASK (0x1FE0U)
+#define SCT_CTRL_PRE_L_SHIFT (5U)
+/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
+ * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
+ * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
+ */
+#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
+#define SCT_CTRL_DOWN_H_MASK (0x10000U)
+#define SCT_CTRL_DOWN_H_SHIFT (16U)
+/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
+ * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
+ * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
+ */
+#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
+#define SCT_CTRL_STOP_H_MASK (0x20000U)
+#define SCT_CTRL_STOP_H_SHIFT (17U)
+/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
+ * the counter can occur. If such an event matches the mask in the Start register, this bit is
+ * cleared and counting resumes.
+ */
+#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
+#define SCT_CTRL_HALT_H_MASK (0x40000U)
+#define SCT_CTRL_HALT_H_SHIFT (18U)
+/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
+ * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
+ * halt condition while keeping the SCT in the stop condition (not running) with a single write to
+ * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
+ * can only be cleared by software to restore counter operation. This bit is set on reset.
+ */
+#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
+#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
+#define SCT_CTRL_CLRCTR_H_SHIFT (19U)
+/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
+ */
+#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
+#define SCT_CTRL_BIDIR_H_MASK (0x100000U)
+#define SCT_CTRL_BIDIR_H_SHIFT (20U)
+/*! BIDIR_H - Direction select
+ * 0b0..The H counter counts up to its limit condition, then is cleared to zero.
+ * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
+#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
+#define SCT_CTRL_PRE_H_SHIFT (21U)
+/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
+ * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
+ * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
+ */
+#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
+/*! @} */
+
+/*! @name LIMIT - SCT limit event select register */
+/*! @{ */
+#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)
+#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
+/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter
+ * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
+#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)
+#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
+/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit
+ * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
+/*! @} */
+
+/*! @name HALT - SCT halt event select register */
+/*! @{ */
+#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)
+#define SCT_HALT_HALTMSK_L_SHIFT (0U)
+/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0,
+ * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
+#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)
+#define SCT_HALT_HALTMSK_H_SHIFT (16U)
+/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16,
+ * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
+/*! @} */
+
+/*! @name STOP - SCT stop event select register */
+/*! @{ */
+#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)
+#define SCT_STOP_STOPMSK_L_SHIFT (0U)
+/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0,
+ * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
+#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)
+#define SCT_STOP_STOPMSK_H_SHIFT (16U)
+/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16,
+ * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
+/*! @} */
+
+/*! @name START - SCT start event select register */
+/*! @{ */
+#define SCT_START_STARTMSK_L_MASK (0xFFFFU)
+#define SCT_START_STARTMSK_L_SHIFT (0U)
+/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit
+ * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
+#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)
+#define SCT_START_STARTMSK_H_SHIFT (16U)
+/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit
+ * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
+/*! @} */
+
+/*! @name COUNT - SCT counter register */
+/*! @{ */
+#define SCT_COUNT_CTR_L_MASK (0xFFFFU)
+#define SCT_COUNT_CTR_L_SHIFT (0U)
+/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write
+ * the lower 16 bits of the 32-bit unified counter.
+ */
+#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
+#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
+#define SCT_COUNT_CTR_H_SHIFT (16U)
+/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write
+ * the upper 16 bits of the 32-bit unified counter.
+ */
+#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
+/*! @} */
+
+/*! @name STATE - SCT state register */
+/*! @{ */
+#define SCT_STATE_STATE_L_MASK (0x1FU)
+#define SCT_STATE_STATE_L_SHIFT (0U)
+/*! STATE_L - State variable.
+ */
+#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
+#define SCT_STATE_STATE_H_MASK (0x1F0000U)
+#define SCT_STATE_STATE_H_SHIFT (16U)
+/*! STATE_H - State variable.
+ */
+#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
+/*! @} */
+
+/*! @name INPUT - SCT input register */
+/*! @{ */
+#define SCT_INPUT_AIN0_MASK (0x1U)
+#define SCT_INPUT_AIN0_SHIFT (0U)
+/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
+#define SCT_INPUT_AIN1_MASK (0x2U)
+#define SCT_INPUT_AIN1_SHIFT (1U)
+/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
+#define SCT_INPUT_AIN2_MASK (0x4U)
+#define SCT_INPUT_AIN2_SHIFT (2U)
+/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
+#define SCT_INPUT_AIN3_MASK (0x8U)
+#define SCT_INPUT_AIN3_SHIFT (3U)
+/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
+#define SCT_INPUT_AIN4_MASK (0x10U)
+#define SCT_INPUT_AIN4_SHIFT (4U)
+/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
+#define SCT_INPUT_AIN5_MASK (0x20U)
+#define SCT_INPUT_AIN5_SHIFT (5U)
+/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
+#define SCT_INPUT_AIN6_MASK (0x40U)
+#define SCT_INPUT_AIN6_SHIFT (6U)
+/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
+#define SCT_INPUT_AIN7_MASK (0x80U)
+#define SCT_INPUT_AIN7_SHIFT (7U)
+/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
+#define SCT_INPUT_AIN8_MASK (0x100U)
+#define SCT_INPUT_AIN8_SHIFT (8U)
+/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
+#define SCT_INPUT_AIN9_MASK (0x200U)
+#define SCT_INPUT_AIN9_SHIFT (9U)
+/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
+#define SCT_INPUT_AIN10_MASK (0x400U)
+#define SCT_INPUT_AIN10_SHIFT (10U)
+/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
+#define SCT_INPUT_AIN11_MASK (0x800U)
+#define SCT_INPUT_AIN11_SHIFT (11U)
+/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
+#define SCT_INPUT_AIN12_MASK (0x1000U)
+#define SCT_INPUT_AIN12_SHIFT (12U)
+/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
+#define SCT_INPUT_AIN13_MASK (0x2000U)
+#define SCT_INPUT_AIN13_SHIFT (13U)
+/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
+#define SCT_INPUT_AIN14_MASK (0x4000U)
+#define SCT_INPUT_AIN14_SHIFT (14U)
+/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
+#define SCT_INPUT_AIN15_MASK (0x8000U)
+#define SCT_INPUT_AIN15_SHIFT (15U)
+/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
+#define SCT_INPUT_SIN0_MASK (0x10000U)
+#define SCT_INPUT_SIN0_SHIFT (16U)
+/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
+#define SCT_INPUT_SIN1_MASK (0x20000U)
+#define SCT_INPUT_SIN1_SHIFT (17U)
+/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
+#define SCT_INPUT_SIN2_MASK (0x40000U)
+#define SCT_INPUT_SIN2_SHIFT (18U)
+/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
+#define SCT_INPUT_SIN3_MASK (0x80000U)
+#define SCT_INPUT_SIN3_SHIFT (19U)
+/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
+#define SCT_INPUT_SIN4_MASK (0x100000U)
+#define SCT_INPUT_SIN4_SHIFT (20U)
+/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
+#define SCT_INPUT_SIN5_MASK (0x200000U)
+#define SCT_INPUT_SIN5_SHIFT (21U)
+/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
+#define SCT_INPUT_SIN6_MASK (0x400000U)
+#define SCT_INPUT_SIN6_SHIFT (22U)
+/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
+#define SCT_INPUT_SIN7_MASK (0x800000U)
+#define SCT_INPUT_SIN7_SHIFT (23U)
+/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
+#define SCT_INPUT_SIN8_MASK (0x1000000U)
+#define SCT_INPUT_SIN8_SHIFT (24U)
+/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
+#define SCT_INPUT_SIN9_MASK (0x2000000U)
+#define SCT_INPUT_SIN9_SHIFT (25U)
+/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
+#define SCT_INPUT_SIN10_MASK (0x4000000U)
+#define SCT_INPUT_SIN10_SHIFT (26U)
+/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
+#define SCT_INPUT_SIN11_MASK (0x8000000U)
+#define SCT_INPUT_SIN11_SHIFT (27U)
+/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
+#define SCT_INPUT_SIN12_MASK (0x10000000U)
+#define SCT_INPUT_SIN12_SHIFT (28U)
+/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
+#define SCT_INPUT_SIN13_MASK (0x20000000U)
+#define SCT_INPUT_SIN13_SHIFT (29U)
+/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
+#define SCT_INPUT_SIN14_MASK (0x40000000U)
+#define SCT_INPUT_SIN14_SHIFT (30U)
+/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
+#define SCT_INPUT_SIN15_MASK (0x80000000U)
+#define SCT_INPUT_SIN15_SHIFT (31U)
+/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
+/*! @} */
+
+/*! @name REGMODE - SCT match/capture mode register */
+/*! @{ */
+#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)
+#define SCT_REGMODE_REGMOD_L_SHIFT (0U)
+/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1,
+ * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
+ * match register. 1 = register operates as capture register.
+ */
+#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
+#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)
+#define SCT_REGMODE_REGMOD_H_SHIFT (16U)
+/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit
+ * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
+ * match registers. 1 = register operates as capture registers.
+ */
+#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
+/*! @} */
+
+/*! @name OUTPUT - SCT output register */
+/*! @{ */
+#define SCT_OUTPUT_OUT_MASK (0xFFFFU)
+#define SCT_OUTPUT_OUT_SHIFT (0U)
+/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the
+ * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
+ * outputs in this SCT.
+ */
+#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
+/*! @} */
+
+/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
+/*! @{ */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
+/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
+/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
+/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
+/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)
+/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)
+/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)
+/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)
+/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)
+/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)
+/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)
+/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)
+/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)
+/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)
+/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)
+/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)
+/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
+/*! @} */
+
+/*! @name RES - SCT conflict resolution register */
+/*! @{ */
+#define SCT_RES_O0RES_MASK (0x3U)
+#define SCT_RES_O0RES_SHIFT (0U)
+/*! O0RES - Effect of simultaneous set and clear on output 0.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR0 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
+#define SCT_RES_O1RES_MASK (0xCU)
+#define SCT_RES_O1RES_SHIFT (2U)
+/*! O1RES - Effect of simultaneous set and clear on output 1.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR1 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
+#define SCT_RES_O2RES_MASK (0x30U)
+#define SCT_RES_O2RES_SHIFT (4U)
+/*! O2RES - Effect of simultaneous set and clear on output 2.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output n (or set based on the SETCLR2 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
+#define SCT_RES_O3RES_MASK (0xC0U)
+#define SCT_RES_O3RES_SHIFT (6U)
+/*! O3RES - Effect of simultaneous set and clear on output 3.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR3 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
+#define SCT_RES_O4RES_MASK (0x300U)
+#define SCT_RES_O4RES_SHIFT (8U)
+/*! O4RES - Effect of simultaneous set and clear on output 4.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR4 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
+#define SCT_RES_O5RES_MASK (0xC00U)
+#define SCT_RES_O5RES_SHIFT (10U)
+/*! O5RES - Effect of simultaneous set and clear on output 5.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR5 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
+#define SCT_RES_O6RES_MASK (0x3000U)
+#define SCT_RES_O6RES_SHIFT (12U)
+/*! O6RES - Effect of simultaneous set and clear on output 6.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR6 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
+#define SCT_RES_O7RES_MASK (0xC000U)
+#define SCT_RES_O7RES_SHIFT (14U)
+/*! O7RES - Effect of simultaneous set and clear on output 7.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output n (or set based on the SETCLR7 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
+#define SCT_RES_O8RES_MASK (0x30000U)
+#define SCT_RES_O8RES_SHIFT (16U)
+/*! O8RES - Effect of simultaneous set and clear on output 8.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR8 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
+#define SCT_RES_O9RES_MASK (0xC0000U)
+#define SCT_RES_O9RES_SHIFT (18U)
+/*! O9RES - Effect of simultaneous set and clear on output 9.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR9 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
+#define SCT_RES_O10RES_MASK (0x300000U)
+#define SCT_RES_O10RES_SHIFT (20U)
+/*! O10RES - Effect of simultaneous set and clear on output 10.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR10 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
+#define SCT_RES_O11RES_MASK (0xC00000U)
+#define SCT_RES_O11RES_SHIFT (22U)
+/*! O11RES - Effect of simultaneous set and clear on output 11.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR11 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
+#define SCT_RES_O12RES_MASK (0x3000000U)
+#define SCT_RES_O12RES_SHIFT (24U)
+/*! O12RES - Effect of simultaneous set and clear on output 12.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR12 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
+#define SCT_RES_O13RES_MASK (0xC000000U)
+#define SCT_RES_O13RES_SHIFT (26U)
+/*! O13RES - Effect of simultaneous set and clear on output 13.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR13 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
+#define SCT_RES_O14RES_MASK (0x30000000U)
+#define SCT_RES_O14RES_SHIFT (28U)
+/*! O14RES - Effect of simultaneous set and clear on output 14.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR14 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
+#define SCT_RES_O15RES_MASK (0xC0000000U)
+#define SCT_RES_O15RES_SHIFT (30U)
+/*! O15RES - Effect of simultaneous set and clear on output 15.
+ * 0b00..No change.
+ * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register).
+ * 0b10..Clear output (or set based on the SETCLR15 field).
+ * 0b11..Toggle output.
+ */
+#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
+/*! @} */
+
+/*! @name DMAREQ0 - SCT DMA request 0 register */
+/*! @{ */
+#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU)
+#define SCT_DMAREQ0_DEV_0_SHIFT (0U)
+/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1,
+ * etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
+#define SCT_DMAREQ0_DRL0_MASK (0x40000000U)
+#define SCT_DMAREQ0_DRL0_SHIFT (30U)
+/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
+ */
+#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
+#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U)
+#define SCT_DMAREQ0_DRQ0_SHIFT (31U)
+/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA
+ * channel is enabled and properly set up, it is unlikely that software will see this flag, it will
+ * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
+ * setup.
+ */
+#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
+/*! @} */
+
+/*! @name DMAREQ1 - SCT DMA request 1 register */
+/*! @{ */
+#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU)
+#define SCT_DMAREQ1_DEV_1_SHIFT (0U)
+/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1,
+ * etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
+#define SCT_DMAREQ1_DRL1_MASK (0x40000000U)
+#define SCT_DMAREQ1_DRL1_SHIFT (30U)
+/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
+ */
+#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
+#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U)
+#define SCT_DMAREQ1_DRQ1_SHIFT (31U)
+/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA
+ * channel is enabled and properly set up, it is unlikely that software will see this flag, it will
+ * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
+ * setup.
+ */
+#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
+/*! @} */
+
+/*! @name EVEN - SCT event interrupt enable register */
+/*! @{ */
+#define SCT_EVEN_IEN_MASK (0xFFFFU)
+#define SCT_EVEN_IEN_SHIFT (0U)
+/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are
+ * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in
+ * this SCT.
+ */
+#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
+/*! @} */
+
+/*! @name EVFLAG - SCT event flag register */
+/*! @{ */
+#define SCT_EVFLAG_FLAG_MASK (0xFFFFU)
+#define SCT_EVFLAG_FLAG_SHIFT (0U)
+/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit
+ * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
+/*! @} */
+
+/*! @name CONEN - SCT conflict interrupt enable register */
+/*! @{ */
+#define SCT_CONEN_NCEN_MASK (0xFFFFU)
+#define SCT_CONEN_NCEN_SHIFT (0U)
+/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag
+ * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
+ * outputs in this SCT.
+ */
+#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
+/*! @} */
+
+/*! @name CONFLAG - SCT conflict flag register */
+/*! @{ */
+#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)
+#define SCT_CONFLAG_NCFLAG_SHIFT (0U)
+/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was
+ * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits =
+ * number of outputs in this SCT.
+ */
+#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
+#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
+#define SCT_CONFLAG_BUSERRL_SHIFT (30U)
+/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE
+ * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write
+ * to certain L and H registers can be half successful and half unsuccessful.
+ */
+#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
+#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
+#define SCT_CONFLAG_BUSERRH_SHIFT (31U)
+/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or
+ * the Output register when the H counter was not halted.
+ */
+#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
+/*! @} */
+
+/*! @name CAP - SCT capture register of capture channel */
+/*! @{ */
+#define SCT_CAP_CAPn_L_MASK (0xFFFFU)
+#define SCT_CAP_CAPn_L_SHIFT (0U)
+/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
+ * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last
+ * captured.
+ */
+#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
+#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U)
+#define SCT_CAP_CAPn_H_SHIFT (16U)
+/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
+ * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last
+ * captured.
+ */
+#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
+/*! @} */
+
+/* The count of SCT_CAP */
+#define SCT_CAP_COUNT (16U)
+
+/*! @name MATCH - SCT match value register of match channels */
+/*! @{ */
+#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU)
+#define SCT_MATCH_MATCHn_L_SHIFT (0U)
+/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When
+ * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified
+ * counter.
+ */
+#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
+#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U)
+#define SCT_MATCH_MATCHn_H_SHIFT (16U)
+/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When
+ * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified
+ * counter.
+ */
+#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
+/*! @} */
+
+/* The count of SCT_MATCH */
+#define SCT_MATCH_COUNT (16U)
+
+/*! @name CAPCTRL - SCT capture control register */
+/*! @{ */
+#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU)
+#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U)
+/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1)
+ * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of
+ * match/captures in this SCT.
+ */
+#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
+#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
+#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U)
+/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event
+ * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
+ */
+#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
+/*! @} */
+
+/* The count of SCT_CAPCTRL */
+#define SCT_CAPCTRL_COUNT (16U)
+
+/*! @name MATCHREL - SCT match reload value register */
+/*! @{ */
+#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU)
+#define SCT_MATCHREL_RELOADn_L_SHIFT (0U)
+/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register.
+ * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn
+ * register.
+ */
+#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
+#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U)
+#define SCT_MATCHREL_RELOADn_H_SHIFT (16U)
+/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When
+ * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn
+ * register.
+ */
+#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHREL */
+#define SCT_MATCHREL_COUNT (16U)
+
+/*! @name EV_STATE - SCT event state register 0 */
+/*! @{ */
+#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU)
+#define SCT_EV_STATE_STATEMSKn_SHIFT (0U)
+/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT
+ * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of
+ * bits = number of states in this SCT.
+ */
+#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
+/*! @} */
+
+/* The count of SCT_EV_STATE */
+#define SCT_EV_STATE_COUNT (16U)
+
+/*! @name EV_CTRL - SCT event control register 0 */
+/*! @{ */
+#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU)
+#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U)
+/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur
+ * only when the counter selected by the HEVENT bit is running.
+ */
+#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
+#define SCT_EV_CTRL_HEVENT_MASK (0x10U)
+#define SCT_EV_CTRL_HEVENT_SHIFT (4U)
+/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1.
+ * 0b0..Selects the L state and the L match register selected by MATCHSEL.
+ * 0b1..Selects the H state and the H match register selected by MATCHSEL.
+ */
+#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
+#define SCT_EV_CTRL_OUTSEL_MASK (0x20U)
+#define SCT_EV_CTRL_OUTSEL_SHIFT (5U)
+/*! OUTSEL - Input/output select
+ * 0b0..Selects the inputs selected by IOSEL.
+ * 0b1..Selects the outputs selected by IOSEL.
+ */
+#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
+#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U)
+#define SCT_EV_CTRL_IOSEL_SHIFT (6U)
+/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not
+ * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit
+ * ingredient of every event.
+ */
+#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
+#define SCT_EV_CTRL_IOCOND_MASK (0xC00U)
+#define SCT_EV_CTRL_IOCOND_SHIFT (10U)
+/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the
+ * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state
+ * detection, an input must have a minimum pulse width of at least one SCT clock period .
+ * 0b00..LOW
+ * 0b01..Rise
+ * 0b10..Fall
+ * 0b11..HIGH
+ */
+#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
+#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U)
+#define SCT_EV_CTRL_COMBMODE_SHIFT (12U)
+/*! COMBMODE - Selects how the specified match and I/O condition are used and combined.
+ * 0b00..OR. The event occurs when either the specified match or I/O condition occurs.
+ * 0b01..MATCH. Uses the specified match only.
+ * 0b10..IO. Uses the specified I/O condition only.
+ * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
+ */
+#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
+#define SCT_EV_CTRL_STATELD_MASK (0x4000U)
+#define SCT_EV_CTRL_STATELD_SHIFT (14U)
+/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this
+ * event is the highest-numbered event occurring for that state.
+ * 0b0..STATEV value is added into STATE (the carry-out is ignored).
+ * 0b1..STATEV value is loaded into STATE.
+ */
+#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
+#define SCT_EV_CTRL_STATEV_MASK (0xF8000U)
+#define SCT_EV_CTRL_STATEV_SHIFT (15U)
+/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on
+ * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and
+ * STATEV are both zero, there is no change to the STATE value.
+ */
+#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
+#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U)
+#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U)
+/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the
+ * triggering of this event, then a match is considered to be active whenever the counter value is
+ * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR
+ * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active
+ * during the cycle when the counter is equal to the match value.
+ */
+#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
+#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U)
+#define SCT_EV_CTRL_DIRECTION_SHIFT (21U)
+/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters
+ * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
+ * 0b00..Direction independent. This event is triggered regardless of the count direction.
+ * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
+ * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
+ */
+#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
+/*! @} */
+
+/* The count of SCT_EV_CTRL */
+#define SCT_EV_CTRL_COUNT (16U)
+
+/*! @name OUT_SET - SCT output 0 set register */
+/*! @{ */
+#define SCT_OUT_SET_SET_MASK (0xFFFFU)
+#define SCT_OUT_SET_SET_SHIFT (0U)
+/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output
+ * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
+ * counter is used in bi-directional mode, it is possible to reverse the action specified by the
+ * output set and clear registers when counting down, See the OUTPUTCTRL register.
+ */
+#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
+/*! @} */
+
+/* The count of SCT_OUT_SET */
+#define SCT_OUT_SET_COUNT (10U)
+
+/*! @name OUT_CLR - SCT output 0 clear register */
+/*! @{ */
+#define SCT_OUT_CLR_CLR_MASK (0xFFFFU)
+#define SCT_OUT_CLR_CLR_SHIFT (0U)
+/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0
+ * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
+ * counter is used in bi-directional mode, it is possible to reverse the action specified by the
+ * output set and clear registers when counting down, See the OUTPUTCTRL register.
+ */
+#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
+/*! @} */
+
+/* The count of SCT_OUT_CLR */
+#define SCT_OUT_CLR_COUNT (10U)
+
+
+/*!
+ * @}
+ */ /* end of group SCT_Register_Masks */
+
+
+/* SCT - Peripheral instance base addresses */
+/** Peripheral SCT0 base address */
+#define SCT0_BASE (0x40085000u)
+/** Peripheral SCT0 base pointer */
+#define SCT0 ((SCT_Type *)SCT0_BASE)
+/** Array initializer of SCT peripheral base addresses */
+#define SCT_BASE_ADDRS { SCT0_BASE }
+/** Array initializer of SCT peripheral base pointers */
+#define SCT_BASE_PTRS { SCT0 }
+/** Interrupt vectors for the SCT peripheral type */
+#define SCT_IRQS { SCT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SCT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDIF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer
+ * @{
+ */
+
+/** SDIF - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control register, offset: 0x0 */
+ __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */
+ __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */
+ __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */
+ __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */
+ __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */
+ __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */
+ __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */
+ __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */
+ __IO uint32_t CMD; /**< Command register, offset: 0x2C */
+ __I uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */
+ __I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */
+ __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */
+ __I uint32_t STATUS; /**< Status register, offset: 0x48 */
+ __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */
+ __I uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */
+ __I uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */
+ uint8_t RESERVED_1[4];
+ __I uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */
+ __I uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
+ __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */
+ __O uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */
+ __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */
+ __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */
+ __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
+ __I uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */
+ __I uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */
+ uint8_t RESERVED_4[100];
+ __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */
+ __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */
+ uint8_t RESERVED_5[248];
+ __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
+} SDIF_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SDIF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Register_Masks SDIF Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register */
+/*! @{ */
+#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U)
+#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U)
+/*! CONTROLLER_RESET - Controller reset.
+ */
+#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
+#define SDIF_CTRL_FIFO_RESET_MASK (0x2U)
+#define SDIF_CTRL_FIFO_RESET_SHIFT (1U)
+/*! FIFO_RESET - Fifo reset.
+ */
+#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
+#define SDIF_CTRL_DMA_RESET_MASK (0x4U)
+#define SDIF_CTRL_DMA_RESET_SHIFT (2U)
+/*! DMA_RESET - DMA reset.
+ */
+#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
+#define SDIF_CTRL_INT_ENABLE_MASK (0x10U)
+#define SDIF_CTRL_INT_ENABLE_SHIFT (4U)
+/*! INT_ENABLE - Global interrupt enable/disable bit.
+ */
+#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
+#define SDIF_CTRL_READ_WAIT_MASK (0x40U)
+#define SDIF_CTRL_READ_WAIT_SHIFT (6U)
+/*! READ_WAIT - Read/wait.
+ */
+#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U)
+/*! SEND_IRQ_RESPONSE - Send irq response.
+ */
+#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
+#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U)
+#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U)
+/*! ABORT_READ_DATA - Abort read data.
+ */
+#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
+#define SDIF_CTRL_SEND_CCSD_MASK (0x200U)
+#define SDIF_CTRL_SEND_CCSD_SHIFT (9U)
+/*! SEND_CCSD - Send ccsd.
+ */
+#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U)
+/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd.
+ */
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
+/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status.
+ */
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U)
+/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin.
+ */
+#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U)
+/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin.
+ */
+#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U)
+/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin.
+ */
+#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U)
+/*! USE_INTERNAL_DMAC - SD/MMC DMA use.
+ */
+#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
+/*! @} */
+
+/*! @name PWREN - Power Enable register */
+/*! @{ */
+#define SDIF_PWREN_POWER_ENABLE_MASK (0x1U)
+#define SDIF_PWREN_POWER_ENABLE_SHIFT (0U)
+/*! POWER_ENABLE - Power on/off switch for card; once power is turned on, software should wait for
+ * regulator/switch ramp-up time before trying to initialize card.
+ */
+#define SDIF_PWREN_POWER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)
+/*! @} */
+
+/*! @name CLKDIV - Clock Divider register */
+/*! @{ */
+#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU)
+#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U)
+/*! CLK_DIVIDER0 - Clock divider-0 value.
+ */
+#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
+/*! @} */
+
+/*! @name CLKENA - Clock Enable register */
+/*! @{ */
+#define SDIF_CLKENA_CCLK_ENABLE_MASK (0x1U)
+#define SDIF_CLKENA_CCLK_ENABLE_SHIFT (0U)
+/*! CCLK_ENABLE - Clock-enable control for SD card clock.
+ */
+#define SDIF_CLKENA_CCLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)
+#define SDIF_CLKENA_CCLK_LOW_POWER_MASK (0x10000U)
+#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT (16U)
+/*! CCLK_LOW_POWER - Low-power control for SD card clock.
+ */
+#define SDIF_CLKENA_CCLK_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)
+/*! @} */
+
+/*! @name TMOUT - Time-out register */
+/*! @{ */
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U)
+/*! RESPONSE_TIMEOUT - Response time-out value.
+ */
+#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
+#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U)
+#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U)
+/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out.
+ */
+#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
+/*! @} */
+
+/*! @name CTYPE - Card Type register */
+/*! @{ */
+#define SDIF_CTYPE_CARD_WIDTH0_MASK (0x1U)
+#define SDIF_CTYPE_CARD_WIDTH0_SHIFT (0U)
+/*! CARD_WIDTH0 - Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit
+ * modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to
+ * 0).
+ */
+#define SDIF_CTYPE_CARD_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)
+#define SDIF_CTYPE_CARD_WIDTH1_MASK (0x10000U)
+#define SDIF_CTYPE_CARD_WIDTH1_SHIFT (16U)
+/*! CARD_WIDTH1 - Indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
+ */
+#define SDIF_CTYPE_CARD_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)
+/*! @} */
+
+/*! @name BLKSIZ - Block Size register */
+/*! @{ */
+#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU)
+#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U)
+/*! BLOCK_SIZE - Block size.
+ */
+#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
+/*! @} */
+
+/*! @name BYTCNT - Byte Count register */
+/*! @{ */
+#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU)
+#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U)
+/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers.
+ */
+#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
+/*! @} */
+
+/*! @name INTMASK - Interrupt Mask register */
+/*! @{ */
+#define SDIF_INTMASK_CDET_MASK (0x1U)
+#define SDIF_INTMASK_CDET_SHIFT (0U)
+/*! CDET - Card detect.
+ */
+#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
+#define SDIF_INTMASK_RE_MASK (0x2U)
+#define SDIF_INTMASK_RE_SHIFT (1U)
+/*! RE - Response error.
+ */
+#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
+#define SDIF_INTMASK_CDONE_MASK (0x4U)
+#define SDIF_INTMASK_CDONE_SHIFT (2U)
+/*! CDONE - Command done.
+ */
+#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
+#define SDIF_INTMASK_DTO_MASK (0x8U)
+#define SDIF_INTMASK_DTO_SHIFT (3U)
+/*! DTO - Data transfer over.
+ */
+#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
+#define SDIF_INTMASK_TXDR_MASK (0x10U)
+#define SDIF_INTMASK_TXDR_SHIFT (4U)
+/*! TXDR - Transmit FIFO data request.
+ */
+#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
+#define SDIF_INTMASK_RXDR_MASK (0x20U)
+#define SDIF_INTMASK_RXDR_SHIFT (5U)
+/*! RXDR - Receive FIFO data request.
+ */
+#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
+#define SDIF_INTMASK_RCRC_MASK (0x40U)
+#define SDIF_INTMASK_RCRC_SHIFT (6U)
+/*! RCRC - Response CRC error.
+ */
+#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
+#define SDIF_INTMASK_DCRC_MASK (0x80U)
+#define SDIF_INTMASK_DCRC_SHIFT (7U)
+/*! DCRC - Data CRC error.
+ */
+#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
+#define SDIF_INTMASK_RTO_MASK (0x100U)
+#define SDIF_INTMASK_RTO_SHIFT (8U)
+/*! RTO - Response time-out.
+ */
+#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
+#define SDIF_INTMASK_DRTO_MASK (0x200U)
+#define SDIF_INTMASK_DRTO_SHIFT (9U)
+/*! DRTO - Data read time-out.
+ */
+#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
+#define SDIF_INTMASK_HTO_MASK (0x400U)
+#define SDIF_INTMASK_HTO_SHIFT (10U)
+/*! HTO - Data starvation-by-host time-out (HTO).
+ */
+#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
+#define SDIF_INTMASK_FRUN_MASK (0x800U)
+#define SDIF_INTMASK_FRUN_SHIFT (11U)
+/*! FRUN - FIFO underrun/overrun error.
+ */
+#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
+#define SDIF_INTMASK_HLE_MASK (0x1000U)
+#define SDIF_INTMASK_HLE_SHIFT (12U)
+/*! HLE - Hardware locked write error.
+ */
+#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
+#define SDIF_INTMASK_SBE_MASK (0x2000U)
+#define SDIF_INTMASK_SBE_SHIFT (13U)
+/*! SBE - Start-bit error.
+ */
+#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
+#define SDIF_INTMASK_ACD_MASK (0x4000U)
+#define SDIF_INTMASK_ACD_SHIFT (14U)
+/*! ACD - Auto command done.
+ */
+#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
+#define SDIF_INTMASK_EBE_MASK (0x8000U)
+#define SDIF_INTMASK_EBE_SHIFT (15U)
+/*! EBE - End-bit error (read)/Write no CRC.
+ */
+#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
+#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U)
+#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U)
+/*! SDIO_INT_MASK - Mask SDIO interrupt.
+ */
+#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
+/*! @} */
+
+/*! @name CMDARG - Command Argument register */
+/*! @{ */
+#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU)
+#define SDIF_CMDARG_CMD_ARG_SHIFT (0U)
+/*! CMD_ARG - Value indicates command argument to be passed to card.
+ */
+#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
+/*! @} */
+
+/*! @name CMD - Command register */
+/*! @{ */
+#define SDIF_CMD_CMD_INDEX_MASK (0x3FU)
+#define SDIF_CMD_CMD_INDEX_SHIFT (0U)
+/*! CMD_INDEX - Command index.
+ */
+#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
+#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U)
+#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U)
+/*! RESPONSE_EXPECT - Response expect.
+ */
+#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
+#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U)
+#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U)
+/*! RESPONSE_LENGTH - Response length.
+ */
+#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U)
+/*! CHECK_RESPONSE_CRC - Check response CRC.
+ */
+#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
+#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U)
+#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U)
+/*! DATA_EXPECTED - Data expected.
+ */
+#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
+#define SDIF_CMD_READ_WRITE_MASK (0x400U)
+#define SDIF_CMD_READ_WRITE_SHIFT (10U)
+/*! READ_WRITE - read/write.
+ */
+#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
+#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U)
+#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U)
+/*! TRANSFER_MODE - Transfer mode.
+ */
+#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
+#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U)
+#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U)
+/*! SEND_AUTO_STOP - Send auto stop.
+ */
+#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U)
+/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete.
+ */
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
+#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U)
+#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U)
+/*! STOP_ABORT_CMD - Stop abort command.
+ */
+#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
+#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U)
+#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U)
+/*! SEND_INITIALIZATION - Send initialization.
+ */
+#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
+/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only.
+ */
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
+#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U)
+#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U)
+/*! READ_CEATA_DEVICE - Read ceata device.
+ */
+#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
+#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U)
+#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U)
+/*! CCS_EXPECTED - CCS expected.
+ */
+#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
+#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U)
+#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U)
+/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode.
+ */
+#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
+#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U)
+#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U)
+/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge.
+ */
+#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
+#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U)
+#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U)
+/*! DISABLE_BOOT - Disable Boot.
+ */
+#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
+#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U)
+#define SDIF_CMD_BOOT_MODE_SHIFT (27U)
+/*! BOOT_MODE - Boot Mode.
+ */
+#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
+#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U)
+#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U)
+/*! VOLT_SWITCH - Voltage switch bit.
+ */
+#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
+#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U)
+#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U)
+/*! USE_HOLD_REG - Use Hold Register.
+ */
+#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
+#define SDIF_CMD_START_CMD_MASK (0x80000000U)
+#define SDIF_CMD_START_CMD_SHIFT (31U)
+/*! START_CMD - Start command.
+ */
+#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
+/*! @} */
+
+/*! @name RESP - Response register */
+/*! @{ */
+#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU)
+#define SDIF_RESP_RESPONSE_SHIFT (0U)
+/*! RESPONSE - Bits of response.
+ */
+#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
+/*! @} */
+
+/* The count of SDIF_RESP */
+#define SDIF_RESP_COUNT (4U)
+
+/*! @name MINTSTS - Masked Interrupt Status register */
+/*! @{ */
+#define SDIF_MINTSTS_CDET_MASK (0x1U)
+#define SDIF_MINTSTS_CDET_SHIFT (0U)
+/*! CDET - Card detect.
+ */
+#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
+#define SDIF_MINTSTS_RE_MASK (0x2U)
+#define SDIF_MINTSTS_RE_SHIFT (1U)
+/*! RE - Response error.
+ */
+#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
+#define SDIF_MINTSTS_CDONE_MASK (0x4U)
+#define SDIF_MINTSTS_CDONE_SHIFT (2U)
+/*! CDONE - Command done.
+ */
+#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
+#define SDIF_MINTSTS_DTO_MASK (0x8U)
+#define SDIF_MINTSTS_DTO_SHIFT (3U)
+/*! DTO - Data transfer over.
+ */
+#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
+#define SDIF_MINTSTS_TXDR_MASK (0x10U)
+#define SDIF_MINTSTS_TXDR_SHIFT (4U)
+/*! TXDR - Transmit FIFO data request.
+ */
+#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
+#define SDIF_MINTSTS_RXDR_MASK (0x20U)
+#define SDIF_MINTSTS_RXDR_SHIFT (5U)
+/*! RXDR - Receive FIFO data request.
+ */
+#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
+#define SDIF_MINTSTS_RCRC_MASK (0x40U)
+#define SDIF_MINTSTS_RCRC_SHIFT (6U)
+/*! RCRC - Response CRC error.
+ */
+#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
+#define SDIF_MINTSTS_DCRC_MASK (0x80U)
+#define SDIF_MINTSTS_DCRC_SHIFT (7U)
+/*! DCRC - Data CRC error.
+ */
+#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
+#define SDIF_MINTSTS_RTO_MASK (0x100U)
+#define SDIF_MINTSTS_RTO_SHIFT (8U)
+/*! RTO - Response time-out.
+ */
+#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
+#define SDIF_MINTSTS_DRTO_MASK (0x200U)
+#define SDIF_MINTSTS_DRTO_SHIFT (9U)
+/*! DRTO - Data read time-out.
+ */
+#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
+#define SDIF_MINTSTS_HTO_MASK (0x400U)
+#define SDIF_MINTSTS_HTO_SHIFT (10U)
+/*! HTO - Data starvation-by-host time-out (HTO).
+ */
+#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
+#define SDIF_MINTSTS_FRUN_MASK (0x800U)
+#define SDIF_MINTSTS_FRUN_SHIFT (11U)
+/*! FRUN - FIFO underrun/overrun error.
+ */
+#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
+#define SDIF_MINTSTS_HLE_MASK (0x1000U)
+#define SDIF_MINTSTS_HLE_SHIFT (12U)
+/*! HLE - Hardware locked write error.
+ */
+#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
+#define SDIF_MINTSTS_SBE_MASK (0x2000U)
+#define SDIF_MINTSTS_SBE_SHIFT (13U)
+/*! SBE - Start-bit error.
+ */
+#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
+#define SDIF_MINTSTS_ACD_MASK (0x4000U)
+#define SDIF_MINTSTS_ACD_SHIFT (14U)
+/*! ACD - Auto command done.
+ */
+#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
+#define SDIF_MINTSTS_EBE_MASK (0x8000U)
+#define SDIF_MINTSTS_EBE_SHIFT (15U)
+/*! EBE - End-bit error (read)/write no CRC.
+ */
+#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U)
+/*! SDIO_INTERRUPT - Interrupt from SDIO card.
+ */
+#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
+/*! @} */
+
+/*! @name RINTSTS - Raw Interrupt Status register */
+/*! @{ */
+#define SDIF_RINTSTS_CDET_MASK (0x1U)
+#define SDIF_RINTSTS_CDET_SHIFT (0U)
+/*! CDET - Card detect.
+ */
+#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
+#define SDIF_RINTSTS_RE_MASK (0x2U)
+#define SDIF_RINTSTS_RE_SHIFT (1U)
+/*! RE - Response error.
+ */
+#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
+#define SDIF_RINTSTS_CDONE_MASK (0x4U)
+#define SDIF_RINTSTS_CDONE_SHIFT (2U)
+/*! CDONE - Command done.
+ */
+#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
+#define SDIF_RINTSTS_DTO_MASK (0x8U)
+#define SDIF_RINTSTS_DTO_SHIFT (3U)
+/*! DTO - Data transfer over.
+ */
+#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
+#define SDIF_RINTSTS_TXDR_MASK (0x10U)
+#define SDIF_RINTSTS_TXDR_SHIFT (4U)
+/*! TXDR - Transmit FIFO data request.
+ */
+#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
+#define SDIF_RINTSTS_RXDR_MASK (0x20U)
+#define SDIF_RINTSTS_RXDR_SHIFT (5U)
+/*! RXDR - Receive FIFO data request.
+ */
+#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
+#define SDIF_RINTSTS_RCRC_MASK (0x40U)
+#define SDIF_RINTSTS_RCRC_SHIFT (6U)
+/*! RCRC - Response CRC error.
+ */
+#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
+#define SDIF_RINTSTS_DCRC_MASK (0x80U)
+#define SDIF_RINTSTS_DCRC_SHIFT (7U)
+/*! DCRC - Data CRC error.
+ */
+#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
+#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U)
+#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U)
+/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR).
+ */
+#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
+#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U)
+#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U)
+/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS).
+ */
+#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
+#define SDIF_RINTSTS_HTO_MASK (0x400U)
+#define SDIF_RINTSTS_HTO_SHIFT (10U)
+/*! HTO - Data starvation-by-host time-out (HTO).
+ */
+#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
+#define SDIF_RINTSTS_FRUN_MASK (0x800U)
+#define SDIF_RINTSTS_FRUN_SHIFT (11U)
+/*! FRUN - FIFO underrun/overrun error.
+ */
+#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
+#define SDIF_RINTSTS_HLE_MASK (0x1000U)
+#define SDIF_RINTSTS_HLE_SHIFT (12U)
+/*! HLE - Hardware locked write error.
+ */
+#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
+#define SDIF_RINTSTS_SBE_MASK (0x2000U)
+#define SDIF_RINTSTS_SBE_SHIFT (13U)
+/*! SBE - Start-bit error.
+ */
+#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
+#define SDIF_RINTSTS_ACD_MASK (0x4000U)
+#define SDIF_RINTSTS_ACD_SHIFT (14U)
+/*! ACD - Auto command done.
+ */
+#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
+#define SDIF_RINTSTS_EBE_MASK (0x8000U)
+#define SDIF_RINTSTS_EBE_SHIFT (15U)
+/*! EBE - End-bit error (read)/write no CRC.
+ */
+#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U)
+/*! SDIO_INTERRUPT - Interrupt from SDIO card.
+ */
+#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
+/*! @} */
+
+/*! @name STATUS - Status register */
+/*! @{ */
+#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U)
+/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer.
+ */
+#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U)
+/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer.
+ */
+#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U)
+#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U)
+/*! FIFO_EMPTY - FIFO is empty status.
+ */
+#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
+#define SDIF_STATUS_FIFO_FULL_MASK (0x8U)
+#define SDIF_STATUS_FIFO_FULL_SHIFT (3U)
+/*! FIFO_FULL - FIFO is full status.
+ */
+#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
+#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U)
+#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U)
+/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx
+ * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 -
+ * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp
+ * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The
+ * command FSM state is represented using 19 bits.
+ */
+#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
+#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U)
+#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U)
+/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present.
+ */
+#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
+#define SDIF_STATUS_DATA_BUSY_MASK (0x200U)
+#define SDIF_STATUS_DATA_BUSY_SHIFT (9U)
+/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy.
+ */
+#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U)
+/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy.
+ */
+#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
+#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U)
+#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U)
+/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core.
+ */
+#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
+#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U)
+#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U)
+/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO.
+ */
+#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
+#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U)
+#define SDIF_STATUS_DMA_ACK_SHIFT (30U)
+/*! DMA_ACK - DMA acknowledge signal state.
+ */
+#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
+#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U)
+#define SDIF_STATUS_DMA_REQ_SHIFT (31U)
+/*! DMA_REQ - DMA request signal state.
+ */
+#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
+/*! @} */
+
+/*! @name FIFOTH - FIFO Threshold Watermark register */
+/*! @{ */
+#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU)
+#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U)
+/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card.
+ */
+#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
+#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U)
+#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U)
+/*! RX_WMARK - FIFO threshold watermark level when receiving data to card.
+ */
+#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
+#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U)
+#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U)
+/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller
+ * multiple-transaction-size SRC/DEST_MSIZE.
+ */
+#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
+/*! @} */
+
+/*! @name CDETECT - Card Detect register */
+/*! @{ */
+#define SDIF_CDETECT_CARD_DETECT_MASK (0x1U)
+#define SDIF_CDETECT_CARD_DETECT_SHIFT (0U)
+/*! CARD_DETECT - Card detect.
+ */
+#define SDIF_CDETECT_CARD_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK)
+/*! @} */
+
+/*! @name WRTPRT - Write Protect register */
+/*! @{ */
+#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U)
+#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U)
+/*! WRITE_PROTECT - Write protect.
+ */
+#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
+/*! @} */
+
+/*! @name TCBCNT - Transferred CIU Card Byte Count register */
+/*! @{ */
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U)
+/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card.
+ */
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
+/*! @} */
+
+/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
+/*! @{ */
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U)
+/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO.
+ */
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
+/*! @} */
+
+/*! @name DEBNCE - Debounce Count register */
+/*! @{ */
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U)
+/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms.
+ */
+#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
+/*! @} */
+
+/*! @name RST_N - Hardware Reset */
+/*! @{ */
+#define SDIF_RST_N_CARD_RESET_MASK (0x1U)
+#define SDIF_RST_N_CARD_RESET_SHIFT (0U)
+/*! CARD_RESET - Hardware reset.
+ */
+#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
+/*! @} */
+
+/*! @name BMOD - Bus Mode register */
+/*! @{ */
+#define SDIF_BMOD_SWR_MASK (0x1U)
+#define SDIF_BMOD_SWR_SHIFT (0U)
+/*! SWR - Software Reset.
+ */
+#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
+#define SDIF_BMOD_FB_MASK (0x2U)
+#define SDIF_BMOD_FB_SHIFT (1U)
+/*! FB - Fixed Burst.
+ */
+#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
+#define SDIF_BMOD_DSL_MASK (0x7CU)
+#define SDIF_BMOD_DSL_SHIFT (2U)
+/*! DSL - Descriptor Skip Length.
+ */
+#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
+#define SDIF_BMOD_DE_MASK (0x80U)
+#define SDIF_BMOD_DE_SHIFT (7U)
+/*! DE - SD/MMC DMA Enable.
+ */
+#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
+#define SDIF_BMOD_PBL_MASK (0x700U)
+#define SDIF_BMOD_PBL_SHIFT (8U)
+/*! PBL - Programmable Burst Length.
+ */
+#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
+/*! @} */
+
+/*! @name PLDMND - Poll Demand register */
+/*! @{ */
+#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU)
+#define SDIF_PLDMND_PD_SHIFT (0U)
+/*! PD - Poll Demand.
+ */
+#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
+/*! @} */
+
+/*! @name DBADDR - Descriptor List Base Address register */
+/*! @{ */
+#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU)
+#define SDIF_DBADDR_SDL_SHIFT (0U)
+/*! SDL - Start of Descriptor List.
+ */
+#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
+/*! @} */
+
+/*! @name IDSTS - Internal DMAC Status register */
+/*! @{ */
+#define SDIF_IDSTS_TI_MASK (0x1U)
+#define SDIF_IDSTS_TI_SHIFT (0U)
+/*! TI - Transmit Interrupt.
+ */
+#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
+#define SDIF_IDSTS_RI_MASK (0x2U)
+#define SDIF_IDSTS_RI_SHIFT (1U)
+/*! RI - Receive Interrupt.
+ */
+#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
+#define SDIF_IDSTS_FBE_MASK (0x4U)
+#define SDIF_IDSTS_FBE_SHIFT (2U)
+/*! FBE - Fatal Bus Error Interrupt.
+ */
+#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
+#define SDIF_IDSTS_DU_MASK (0x10U)
+#define SDIF_IDSTS_DU_SHIFT (4U)
+/*! DU - Descriptor Unavailable Interrupt.
+ */
+#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
+#define SDIF_IDSTS_CES_MASK (0x20U)
+#define SDIF_IDSTS_CES_SHIFT (5U)
+/*! CES - Card Error Summary.
+ */
+#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
+#define SDIF_IDSTS_NIS_MASK (0x100U)
+#define SDIF_IDSTS_NIS_SHIFT (8U)
+/*! NIS - Normal Interrupt Summary.
+ */
+#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
+#define SDIF_IDSTS_AIS_MASK (0x200U)
+#define SDIF_IDSTS_AIS_SHIFT (9U)
+/*! AIS - Abnormal Interrupt Summary.
+ */
+#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
+#define SDIF_IDSTS_EB_MASK (0x1C00U)
+#define SDIF_IDSTS_EB_SHIFT (10U)
+/*! EB - Error Bits.
+ */
+#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
+#define SDIF_IDSTS_FSM_MASK (0x1E000U)
+#define SDIF_IDSTS_FSM_SHIFT (13U)
+/*! FSM - DMAC state machine present state.
+ */
+#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
+/*! @} */
+
+/*! @name IDINTEN - Internal DMAC Interrupt Enable register */
+/*! @{ */
+#define SDIF_IDINTEN_TI_MASK (0x1U)
+#define SDIF_IDINTEN_TI_SHIFT (0U)
+/*! TI - Transmit Interrupt Enable.
+ */
+#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
+#define SDIF_IDINTEN_RI_MASK (0x2U)
+#define SDIF_IDINTEN_RI_SHIFT (1U)
+/*! RI - Receive Interrupt Enable.
+ */
+#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
+#define SDIF_IDINTEN_FBE_MASK (0x4U)
+#define SDIF_IDINTEN_FBE_SHIFT (2U)
+/*! FBE - Fatal Bus Error Enable.
+ */
+#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
+#define SDIF_IDINTEN_DU_MASK (0x10U)
+#define SDIF_IDINTEN_DU_SHIFT (4U)
+/*! DU - Descriptor Unavailable Interrupt.
+ */
+#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
+#define SDIF_IDINTEN_CES_MASK (0x20U)
+#define SDIF_IDINTEN_CES_SHIFT (5U)
+/*! CES - Card Error summary Interrupt Enable.
+ */
+#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
+#define SDIF_IDINTEN_NIS_MASK (0x100U)
+#define SDIF_IDINTEN_NIS_SHIFT (8U)
+/*! NIS - Normal Interrupt Summary Enable.
+ */
+#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
+#define SDIF_IDINTEN_AIS_MASK (0x200U)
+#define SDIF_IDINTEN_AIS_SHIFT (9U)
+/*! AIS - Abnormal Interrupt Summary Enable.
+ */
+#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
+/*! @} */
+
+/*! @name DSCADDR - Current Host Descriptor Address register */
+/*! @{ */
+#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU)
+#define SDIF_DSCADDR_HDA_SHIFT (0U)
+/*! HDA - Host Descriptor Address Pointer.
+ */
+#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
+/*! @} */
+
+/*! @name BUFADDR - Current Buffer Descriptor Address register */
+/*! @{ */
+#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU)
+#define SDIF_BUFADDR_HBA_SHIFT (0U)
+/*! HBA - Host Buffer Address Pointer.
+ */
+#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
+/*! @} */
+
+/*! @name CARDTHRCTL - Card Threshold Control */
+/*! @{ */
+#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U)
+/*! CARDRDTHREN - Card Read Threshold Enable.
+ */
+#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U)
+/*! BSYCLRINTEN - Busy Clear Interrupt Enable.
+ */
+#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U)
+/*! CARDTHRESHOLD - Card Threshold size.
+ */
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
+/*! @} */
+
+/*! @name BACKENDPWR - Power control */
+/*! @{ */
+#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U)
+#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U)
+/*! BACKENDPWR - Back-end Power control for card application.
+ */
+#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
+/*! @} */
+
+/*! @name FIFO - SDIF FIFO */
+/*! @{ */
+#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU)
+#define SDIF_FIFO_DATA_SHIFT (0U)
+/*! DATA - SDIF FIFO.
+ */
+#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
+/*! @} */
+
+/* The count of SDIF_FIFO */
+#define SDIF_FIFO_COUNT (64U)
+
+
+/*!
+ * @}
+ */ /* end of group SDIF_Register_Masks */
+
+
+/* SDIF - Peripheral instance base addresses */
+/** Peripheral SDIF base address */
+#define SDIF_BASE (0x4009B000u)
+/** Peripheral SDIF base pointer */
+#define SDIF ((SDIF_Type *)SDIF_BASE)
+/** Array initializer of SDIF peripheral base addresses */
+#define SDIF_BASE_ADDRS { SDIF_BASE }
+/** Array initializer of SDIF peripheral base pointers */
+#define SDIF_BASE_PTRS { SDIF }
+/** Interrupt vectors for the SDIF peripheral type */
+#define SDIF_IRQS { SDIO_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SDIF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SHA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SHA_Peripheral_Access_Layer SHA Peripheral Access Layer
+ * @{
+ */
+
+/** SHA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control register, offset: 0x0 */
+ __IO uint32_t STATUS; /**< Status register, offset: 0x4 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable register, offset: 0x8 */
+ __O uint32_t INTENCLR; /**< Interrupt Clear register, offset: 0xC */
+ __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */
+ __IO uint32_t MEMADDR; /**< Memory Address register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t INDATA; /**< Input Data register, offset: 0x20 */
+ __O uint32_t ALIAS[7]; /**< Alias register, array offset: 0x24, array step: 0x4 */
+ __I uint32_t DIGEST[8]; /**< Digest register, array offset: 0x40, array step: 0x4 */
+} SHA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SHA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SHA_Register_Masks SHA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register */
+/*! @{ */
+#define SHA_CTRL_MODE_MASK (0x3U)
+#define SHA_CTRL_MODE_SHIFT (0U)
+/*! MODE - This field is used to select the operational mode of SHA block.
+ */
+#define SHA_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_MODE_SHIFT)) & SHA_CTRL_MODE_MASK)
+#define SHA_CTRL_NEW_MASK (0x10U)
+#define SHA_CTRL_NEW_SHIFT (4U)
+/*! NEW - When this bit is set, a new hash operation is started.
+ */
+#define SHA_CTRL_NEW(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_NEW_SHIFT)) & SHA_CTRL_NEW_MASK)
+#define SHA_CTRL_DMA_MASK (0x100U)
+#define SHA_CTRL_DMA_SHIFT (8U)
+/*! DMA - When this bit is set, the DMA is used to fill INDATA.
+ */
+#define SHA_CTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_DMA_SHIFT)) & SHA_CTRL_DMA_MASK)
+/*! @} */
+
+/*! @name STATUS - Status register */
+/*! @{ */
+#define SHA_STATUS_WAITING_MASK (0x1U)
+#define SHA_STATUS_WAITING_SHIFT (0U)
+/*! WAITING - This field indicates if the block is waiting for more data to process.
+ */
+#define SHA_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_WAITING_SHIFT)) & SHA_STATUS_WAITING_MASK)
+#define SHA_STATUS_DIGEST_MASK (0x2U)
+#define SHA_STATUS_DIGEST_SHIFT (1U)
+/*! DIGEST - This field indicates if a DIGEST is ready and waiting and there is no active next block that has already started.
+ */
+#define SHA_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_DIGEST_SHIFT)) & SHA_STATUS_DIGEST_MASK)
+#define SHA_STATUS_ERROR_MASK (0x4U)
+#define SHA_STATUS_ERROR_SHIFT (2U)
+/*! ERROR - This field indicates if an error has occurred.
+ */
+#define SHA_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_ERROR_SHIFT)) & SHA_STATUS_ERROR_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable register */
+/*! @{ */
+#define SHA_INTENSET_WAITING_MASK (0x1U)
+#define SHA_INTENSET_WAITING_SHIFT (0U)
+/*! WAITING - This field indicates if interrupt should be enabled when waiting for input data.
+ */
+#define SHA_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_WAITING_SHIFT)) & SHA_INTENSET_WAITING_MASK)
+#define SHA_INTENSET_DIGEST_MASK (0x2U)
+#define SHA_INTENSET_DIGEST_SHIFT (1U)
+/*! DIGEST - This field indicates if interrupt is generated when Digest is ready (completed a Hash or completed a full sequence).
+ */
+#define SHA_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_DIGEST_SHIFT)) & SHA_INTENSET_DIGEST_MASK)
+#define SHA_INTENSET_ERROR_MASK (0x4U)
+#define SHA_INTENSET_ERROR_SHIFT (2U)
+/*! ERROR - This field indicates if interrupt is generated on an ERROR (as defined in STAT register).
+ */
+#define SHA_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_ERROR_SHIFT)) & SHA_INTENSET_ERROR_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Clear register */
+/*! @{ */
+#define SHA_INTENCLR_WAITING_MASK (0x1U)
+#define SHA_INTENCLR_WAITING_SHIFT (0U)
+/*! WAITING - Writing a 1 clears the interrupt enabled by the INTENSET register.
+ */
+#define SHA_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_WAITING_SHIFT)) & SHA_INTENCLR_WAITING_MASK)
+#define SHA_INTENCLR_DIGEST_MASK (0x2U)
+#define SHA_INTENCLR_DIGEST_SHIFT (1U)
+/*! DIGEST - Writing a 1 clears the interrupt enabled by the INTENSET register.
+ */
+#define SHA_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_DIGEST_SHIFT)) & SHA_INTENCLR_DIGEST_MASK)
+#define SHA_INTENCLR_ERROR_MASK (0x4U)
+#define SHA_INTENCLR_ERROR_SHIFT (2U)
+/*! ERROR - Writing a 1 clears the interrupt enabled by the INTENSET register.
+ */
+#define SHA_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_ERROR_SHIFT)) & SHA_INTENCLR_ERROR_MASK)
+/*! @} */
+
+/*! @name MEMCTRL - Memory Control register */
+/*! @{ */
+#define SHA_MEMCTRL_MASTER_MASK (0x1U)
+#define SHA_MEMCTRL_MASTER_SHIFT (0U)
+/*! MASTER - This field is used to enable SHA block as AHB bus master.
+ */
+#define SHA_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_MASTER_SHIFT)) & SHA_MEMCTRL_MASTER_MASK)
+#define SHA_MEMCTRL_COUNT_MASK (0x7FF0000U)
+#define SHA_MEMCTRL_COUNT_SHIFT (16U)
+/*! COUNT - This field indicates the number of 512-bit blocks to copy starting at MEMADDR.
+ */
+#define SHA_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_COUNT_SHIFT)) & SHA_MEMCTRL_COUNT_MASK)
+/*! @} */
+
+/*! @name MEMADDR - Memory Address register */
+/*! @{ */
+#define SHA_MEMADDR_BASEADDR_MASK (0xFFFFFFFFU)
+#define SHA_MEMADDR_BASEADDR_SHIFT (0U)
+/*! BASEADDR - This field indicates the base address in Internal Flash, SRAM0, SRAMX, or SPIFI to start copying from.
+ */
+#define SHA_MEMADDR_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMADDR_BASEADDR_SHIFT)) & SHA_MEMADDR_BASEADDR_MASK)
+/*! @} */
+
+/*! @name INDATA - Input Data register */
+/*! @{ */
+#define SHA_INDATA_DATA_MASK (0xFFFFFFFFU)
+#define SHA_INDATA_DATA_SHIFT (0U)
+/*! DATA - In this field the next word is written in little-endian format.
+ */
+#define SHA_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_INDATA_DATA_SHIFT)) & SHA_INDATA_DATA_MASK)
+/*! @} */
+
+/*! @name ALIAS - Alias register */
+/*! @{ */
+#define SHA_ALIAS_DATA_MASK (0xFFFFFFFFU)
+#define SHA_ALIAS_DATA_SHIFT (0U)
+/*! DATA - In this field the next word is written in little-endian format.
+ */
+#define SHA_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_ALIAS_DATA_SHIFT)) & SHA_ALIAS_DATA_MASK)
+/*! @} */
+
+/* The count of SHA_ALIAS */
+#define SHA_ALIAS_COUNT (7U)
+
+/*! @name DIGEST - Digest register */
+/*! @{ */
+#define SHA_DIGEST_DIGEST_MASK (0xFFFFFFFFU)
+#define SHA_DIGEST_DIGEST_SHIFT (0U)
+/*! DIGEST - This field contains one word of the Digest.
+ */
+#define SHA_DIGEST_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_DIGEST_DIGEST_SHIFT)) & SHA_DIGEST_DIGEST_MASK)
+/*! @} */
+
+/* The count of SHA_DIGEST */
+#define SHA_DIGEST_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group SHA_Register_Masks */
+
+
+/* SHA - Peripheral instance base addresses */
+/** Peripheral SHA0 base address */
+#define SHA0_BASE (0x400A4000u)
+/** Peripheral SHA0 base pointer */
+#define SHA0 ((SHA_Type *)SHA0_BASE)
+/** Array initializer of SHA peripheral base addresses */
+#define SHA_BASE_ADDRS { SHA0_BASE }
+/** Array initializer of SHA peripheral base pointers */
+#define SHA_BASE_PTRS { SHA0 }
+
+/*!
+ * @}
+ */ /* end of group SHA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMARTCARD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer
+ * @{
+ */
+
+/** SMARTCARD - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ __IO uint32_t DLL; /**< Divisor Latch LSB, offset: 0x0 */
+ __I uint32_t RBR; /**< Receiver Buffer Register, offset: 0x0 */
+ __O uint32_t THR; /**< Transmit Holding Register, offset: 0x0 */
+ };
+ union { /* offset: 0x4 */
+ __IO uint32_t DLM; /**< Divisor Latch MSB, offset: 0x4 */
+ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x4 */
+ };
+ union { /* offset: 0x8 */
+ __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */
+ __I uint32_t IIR; /**< Interrupt ID Register, offset: 0x8 */
+ };
+ __IO uint32_t LCR; /**< Line Control Register, offset: 0xC */
+ uint8_t RESERVED_0[4];
+ __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SCR; /**< Scratch Pad Register, offset: 0x1C */
+ uint8_t RESERVED_2[12];
+ __IO uint32_t OSR; /**< Oversampling register, offset: 0x2C */
+ uint8_t RESERVED_3[24];
+ __IO uint32_t SCICTRL; /**< Smart Card Interface control register, offset: 0x48 */
+} SMARTCARD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMARTCARD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks
+ * @{
+ */
+
+/*! @name DLL - Divisor Latch LSB */
+/*! @{ */
+#define SMARTCARD_DLL_DLLSB_MASK (0xFFU)
+#define SMARTCARD_DLL_DLLSB_SHIFT (0U)
+/*! DLLSB - The SCIn Divisor Latch LSB Register, along with the SCInDLM register, determines the baud rate of the SCIn.
+ */
+#define SMARTCARD_DLL_DLLSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK)
+/*! @} */
+
+/*! @name RBR - Receiver Buffer Register */
+/*! @{ */
+#define SMARTCARD_RBR_RBR_MASK (0xFFU)
+#define SMARTCARD_RBR_RBR_SHIFT (0U)
+/*! RBR - The SCIn Receiver Buffer Register contains the oldest received byte in the SCIn Rx FIFO.
+ */
+#define SMARTCARD_RBR_RBR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK)
+/*! @} */
+
+/*! @name THR - Transmit Holding Register */
+/*! @{ */
+#define SMARTCARD_THR_THR_MASK (0xFFU)
+#define SMARTCARD_THR_THR_SHIFT (0U)
+/*! THR - Writing to the SCIn Transmit Holding Register causes the data to be stored in the SCIn transmit FIFO.
+ */
+#define SMARTCARD_THR_THR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK)
+/*! @} */
+
+/*! @name DLM - Divisor Latch MSB */
+/*! @{ */
+#define SMARTCARD_DLM_DLMSB_MASK (0xFFU)
+#define SMARTCARD_DLM_DLMSB_SHIFT (0U)
+/*! DLMSB - The SCIn Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the SCIn.
+ */
+#define SMARTCARD_DLM_DLMSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK)
+/*! @} */
+
+/*! @name IER - Interrupt Enable Register */
+/*! @{ */
+#define SMARTCARD_IER_RBRIE_MASK (0x1U)
+#define SMARTCARD_IER_RBRIE_SHIFT (0U)
+/*! RBRIE - RBR Interrupt Enable.
+ */
+#define SMARTCARD_IER_RBRIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK)
+#define SMARTCARD_IER_THREIE_MASK (0x2U)
+#define SMARTCARD_IER_THREIE_SHIFT (1U)
+/*! THREIE - THRE Interrupt Enable.
+ */
+#define SMARTCARD_IER_THREIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK)
+#define SMARTCARD_IER_RXIE_MASK (0x4U)
+#define SMARTCARD_IER_RXIE_SHIFT (2U)
+/*! RXIE - RX Line Status Interrupt Enable.
+ */
+#define SMARTCARD_IER_RXIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK)
+/*! @} */
+
+/*! @name FCR - FIFO Control Register */
+/*! @{ */
+#define SMARTCARD_FCR_FIFOEN_MASK (0x1U)
+#define SMARTCARD_FCR_FIFOEN_SHIFT (0U)
+/*! FIFOEN - FIFO Enable.
+ */
+#define SMARTCARD_FCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK)
+#define SMARTCARD_FCR_RXFIFORES_MASK (0x2U)
+#define SMARTCARD_FCR_RXFIFORES_SHIFT (1U)
+/*! RXFIFORES - RX FIFO Reset.
+ */
+#define SMARTCARD_FCR_RXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK)
+#define SMARTCARD_FCR_TXFIFORES_MASK (0x4U)
+#define SMARTCARD_FCR_TXFIFORES_SHIFT (2U)
+/*! TXFIFORES - TX FIFO Reset.
+ */
+#define SMARTCARD_FCR_TXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK)
+#define SMARTCARD_FCR_DMAMODE_MASK (0x8U)
+#define SMARTCARD_FCR_DMAMODE_SHIFT (3U)
+/*! DMAMODE - DMA Mode Select.
+ */
+#define SMARTCARD_FCR_DMAMODE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK)
+#define SMARTCARD_FCR_RXTRIGLVL_MASK (0xC0U)
+#define SMARTCARD_FCR_RXTRIGLVL_SHIFT (6U)
+/*! RXTRIGLVL - RX Trigger Level.
+ */
+#define SMARTCARD_FCR_RXTRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK)
+/*! @} */
+
+/*! @name IIR - Interrupt ID Register */
+/*! @{ */
+#define SMARTCARD_IIR_INTSTATUS_MASK (0x1U)
+#define SMARTCARD_IIR_INTSTATUS_SHIFT (0U)
+/*! INTSTATUS - Interrupt status.
+ */
+#define SMARTCARD_IIR_INTSTATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK)
+#define SMARTCARD_IIR_INTID_MASK (0xEU)
+#define SMARTCARD_IIR_INTID_SHIFT (1U)
+/*! INTID - Interrupt identification.
+ */
+#define SMARTCARD_IIR_INTID(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK)
+#define SMARTCARD_IIR_FIFOENABLE_MASK (0xC0U)
+#define SMARTCARD_IIR_FIFOENABLE_SHIFT (6U)
+/*! FIFOENABLE - Copies of SCInFCR[0].
+ */
+#define SMARTCARD_IIR_FIFOENABLE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK)
+/*! @} */
+
+/*! @name LCR - Line Control Register */
+/*! @{ */
+#define SMARTCARD_LCR_WLS_MASK (0x3U)
+#define SMARTCARD_LCR_WLS_SHIFT (0U)
+/*! WLS - Word Length Select.
+ */
+#define SMARTCARD_LCR_WLS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK)
+#define SMARTCARD_LCR_SBS_MASK (0x4U)
+#define SMARTCARD_LCR_SBS_SHIFT (2U)
+/*! SBS - Stop Bit Select.
+ */
+#define SMARTCARD_LCR_SBS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK)
+#define SMARTCARD_LCR_PE_MASK (0x8U)
+#define SMARTCARD_LCR_PE_SHIFT (3U)
+/*! PE - Parity Enable.
+ */
+#define SMARTCARD_LCR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK)
+#define SMARTCARD_LCR_PS_MASK (0x30U)
+#define SMARTCARD_LCR_PS_SHIFT (4U)
+/*! PS - Parity Select.
+ */
+#define SMARTCARD_LCR_PS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK)
+#define SMARTCARD_LCR_DLAB_MASK (0x80U)
+#define SMARTCARD_LCR_DLAB_SHIFT (7U)
+/*! DLAB - Divisor Latch Access Bit.
+ */
+#define SMARTCARD_LCR_DLAB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK)
+/*! @} */
+
+/*! @name LSR - Line Status Register */
+/*! @{ */
+#define SMARTCARD_LSR_RDR_MASK (0x1U)
+#define SMARTCARD_LSR_RDR_SHIFT (0U)
+/*! RDR - Receiver Data Ready.
+ */
+#define SMARTCARD_LSR_RDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK)
+#define SMARTCARD_LSR_OE_MASK (0x2U)
+#define SMARTCARD_LSR_OE_SHIFT (1U)
+/*! OE - Overrun Error.
+ */
+#define SMARTCARD_LSR_OE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK)
+#define SMARTCARD_LSR_PE_MASK (0x4U)
+#define SMARTCARD_LSR_PE_SHIFT (2U)
+/*! PE - Parity Error.
+ */
+#define SMARTCARD_LSR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK)
+#define SMARTCARD_LSR_FE_MASK (0x8U)
+#define SMARTCARD_LSR_FE_SHIFT (3U)
+/*! FE - Framing Error.
+ */
+#define SMARTCARD_LSR_FE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK)
+#define SMARTCARD_LSR_THRE_MASK (0x20U)
+#define SMARTCARD_LSR_THRE_SHIFT (5U)
+/*! THRE - Transmitter Holding Register Empty.
+ */
+#define SMARTCARD_LSR_THRE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK)
+#define SMARTCARD_LSR_TEMT_MASK (0x40U)
+#define SMARTCARD_LSR_TEMT_SHIFT (6U)
+/*! TEMT - Transmitter Empty.
+ */
+#define SMARTCARD_LSR_TEMT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK)
+#define SMARTCARD_LSR_RXFE_MASK (0x80U)
+#define SMARTCARD_LSR_RXFE_SHIFT (7U)
+/*! RXFE - Error in RX FIFO.
+ */
+#define SMARTCARD_LSR_RXFE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK)
+/*! @} */
+
+/*! @name SCR - Scratch Pad Register */
+/*! @{ */
+#define SMARTCARD_SCR_PAD_MASK (0xFFU)
+#define SMARTCARD_SCR_PAD_SHIFT (0U)
+/*! PAD - A readable, writable byte.
+ */
+#define SMARTCARD_SCR_PAD(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK)
+/*! @} */
+
+/*! @name OSR - Oversampling register */
+/*! @{ */
+#define SMARTCARD_OSR_OSFRAC_MASK (0xEU)
+#define SMARTCARD_OSR_OSFRAC_SHIFT (1U)
+/*! OSFRAC - Fractional part of the oversampling ratio, in units of 1/8th of an input clock period.
+ */
+#define SMARTCARD_OSR_OSFRAC(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK)
+#define SMARTCARD_OSR_OSINT_MASK (0xF0U)
+#define SMARTCARD_OSR_OSINT_SHIFT (4U)
+/*! OSINT - Integer part of the oversampling ratio, minus 1.
+ */
+#define SMARTCARD_OSR_OSINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK)
+#define SMARTCARD_OSR_FDINT_MASK (0x7F00U)
+#define SMARTCARD_OSR_FDINT_SHIFT (8U)
+/*! FDINT - These bits act as a more-significant extension of the OSint field, allowing an
+ * oversampling ratio up to 2048 as required by ISO7816-3.
+ */
+#define SMARTCARD_OSR_FDINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK)
+/*! @} */
+
+/*! @name SCICTRL - Smart Card Interface control register */
+/*! @{ */
+#define SMARTCARD_SCICTRL_SCIEN_MASK (0x1U)
+#define SMARTCARD_SCICTRL_SCIEN_SHIFT (0U)
+/*! SCIEN - Smart Card Interface Enable.
+ */
+#define SMARTCARD_SCICTRL_SCIEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK)
+#define SMARTCARD_SCICTRL_NACKDIS_MASK (0x2U)
+#define SMARTCARD_SCICTRL_NACKDIS_SHIFT (1U)
+/*! NACKDIS - NACK response disable.
+ */
+#define SMARTCARD_SCICTRL_NACKDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK)
+#define SMARTCARD_SCICTRL_PROTSEL_MASK (0x4U)
+#define SMARTCARD_SCICTRL_PROTSEL_SHIFT (2U)
+/*! PROTSEL - Protocol selection as defined in the ISO7816-3 standard.
+ */
+#define SMARTCARD_SCICTRL_PROTSEL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK)
+#define SMARTCARD_SCICTRL_TXRETRY_MASK (0xE0U)
+#define SMARTCARD_SCICTRL_TXRETRY_SHIFT (5U)
+/*! TXRETRY - Maximum number of retransmissions in case of a negative acknowledge (protocol T=0).
+ */
+#define SMARTCARD_SCICTRL_TXRETRY(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK)
+#define SMARTCARD_SCICTRL_GUARDTIME_MASK (0xFF00U)
+#define SMARTCARD_SCICTRL_GUARDTIME_SHIFT (8U)
+/*! GUARDTIME - Extra guard time.
+ */
+#define SMARTCARD_SCICTRL_GUARDTIME(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SMARTCARD_Register_Masks */
+
+
+/* SMARTCARD - Peripheral instance base addresses */
+/** Peripheral SMARTCARD0 base address */
+#define SMARTCARD0_BASE (0x40036000u)
+/** Peripheral SMARTCARD0 base pointer */
+#define SMARTCARD0 ((SMARTCARD_Type *)SMARTCARD0_BASE)
+/** Peripheral SMARTCARD1 base address */
+#define SMARTCARD1_BASE (0x40037000u)
+/** Peripheral SMARTCARD1 base pointer */
+#define SMARTCARD1 ((SMARTCARD_Type *)SMARTCARD1_BASE)
+/** Array initializer of SMARTCARD peripheral base addresses */
+#define SMARTCARD_BASE_ADDRS { SMARTCARD0_BASE, SMARTCARD1_BASE }
+/** Array initializer of SMARTCARD peripheral base pointers */
+#define SMARTCARD_BASE_PTRS { SMARTCARD0, SMARTCARD1 }
+/** Interrupt vectors for the SMARTCARD peripheral type */
+#define SMARTCARD_IRQS { SMARTCARD0_IRQn, SMARTCARD1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SMARTCARD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[1024];
+ __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */
+ __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */
+ __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
+ __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
+ __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */
+ __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */
+ uint8_t RESERVED_2[2516];
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
+ uint8_t RESERVED_4[4];
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
+ uint8_t RESERVED_5[12];
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
+ uint8_t RESERVED_6[12];
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+ uint8_t RESERVED_7[440];
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name CFG - SPI Configuration register */
+/*! @{ */
+#define SPI_CFG_ENABLE_MASK (0x1U)
+#define SPI_CFG_ENABLE_SHIFT (0U)
+/*! ENABLE - SPI enable.
+ * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
+ * 0b1..Enabled. The SPI is enabled for operation.
+ */
+#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
+#define SPI_CFG_MASTER_MASK (0x4U)
+#define SPI_CFG_MASTER_SHIFT (2U)
+/*! MASTER - Master mode select.
+ * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
+ * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
+ */
+#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
+#define SPI_CFG_LSBF_MASK (0x8U)
+#define SPI_CFG_LSBF_SHIFT (3U)
+/*! LSBF - LSB First mode enable.
+ * 0b0..Standard. Data is transmitted and received in standard MSB first order.
+ * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
+ */
+#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
+#define SPI_CFG_CPHA_MASK (0x10U)
+#define SPI_CFG_CPHA_SHIFT (4U)
+/*! CPHA - Clock Phase select.
+ * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock
+ * changes away from the rest state). Data is changed on the following edge.
+ * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock
+ * changes away from the rest state). Data is captured on the following edge.
+ */
+#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
+#define SPI_CFG_CPOL_MASK (0x20U)
+#define SPI_CFG_CPOL_SHIFT (5U)
+/*! CPOL - Clock Polarity select.
+ * 0b0..Low. The rest state of the clock (between transfers) is low.
+ * 0b1..High. The rest state of the clock (between transfers) is high.
+ */
+#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
+#define SPI_CFG_LOOP_MASK (0x80U)
+#define SPI_CFG_LOOP_SHIFT (7U)
+/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit
+ * and receive data connected together to allow simple software testing.
+ * 0b0..Disabled.
+ * 0b1..Enabled.
+ */
+#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
+#define SPI_CFG_SPOL0_MASK (0x100U)
+#define SPI_CFG_SPOL0_SHIFT (8U)
+/*! SPOL0 - SSEL0 Polarity select.
+ * 0b0..Low. The SSEL0 pin is active low.
+ * 0b1..High. The SSEL0 pin is active high.
+ */
+#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
+#define SPI_CFG_SPOL1_MASK (0x200U)
+#define SPI_CFG_SPOL1_SHIFT (9U)
+/*! SPOL1 - SSEL1 Polarity select.
+ * 0b0..Low. The SSEL1 pin is active low.
+ * 0b1..High. The SSEL1 pin is active high.
+ */
+#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
+#define SPI_CFG_SPOL2_MASK (0x400U)
+#define SPI_CFG_SPOL2_SHIFT (10U)
+/*! SPOL2 - SSEL2 Polarity select.
+ * 0b0..Low. The SSEL2 pin is active low.
+ * 0b1..High. The SSEL2 pin is active high.
+ */
+#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
+#define SPI_CFG_SPOL3_MASK (0x800U)
+#define SPI_CFG_SPOL3_SHIFT (11U)
+/*! SPOL3 - SSEL3 Polarity select.
+ * 0b0..Low. The SSEL3 pin is active low.
+ * 0b1..High. The SSEL3 pin is active high.
+ */
+#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
+/*! @} */
+
+/*! @name DLY - SPI Delay register */
+/*! @{ */
+#define SPI_DLY_PRE_DELAY_MASK (0xFU)
+#define SPI_DLY_PRE_DELAY_SHIFT (0U)
+/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data
+ * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This
+ * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI
+ * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are
+ * inserted.
+ */
+#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
+#define SPI_DLY_POST_DELAY_MASK (0xF0U)
+#define SPI_DLY_POST_DELAY_SHIFT (4U)
+/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL
+ * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock
+ * times are inserted. 0xF = 15 SPI clock times are inserted.
+ */
+#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
+#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
+#define SPI_DLY_FRAME_DELAY_SHIFT (8U)
+/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current
+ * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1
+ * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock
+ * times are inserted.
+ */
+#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
+#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
+/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between
+ * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1
+ * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that
+ * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16
+ * SPI clock times.
+ */
+#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
+/*! @} */
+
+/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
+/*! @{ */
+#define SPI_STAT_SSA_MASK (0x10U)
+#define SPI_STAT_SSA_SHIFT (4U)
+/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from
+ * deasserted to asserted, in both master and slave modes. This allows determining when the SPI
+ * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a
+ * slave mode access begins. This flag is cleared by software.
+ */
+#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
+#define SPI_STAT_SSD_MASK (0x20U)
+#define SPI_STAT_SSD_SHIFT (5U)
+/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to
+ * deasserted, in both master and slave modes. This allows determining when the SPI
+ * transmit/receive functions become idle. This flag is cleared by software.
+ */
+#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
+#define SPI_STAT_STALLED_MASK (0x40U)
+#define SPI_STAT_STALLED_SHIFT (6U)
+/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition.
+ */
+#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
+#define SPI_STAT_ENDTRANSFER_MASK (0x80U)
+#define SPI_STAT_ENDTRANSFER_SHIFT (7U)
+/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current
+ * transfer when the transmitter finishes any activity already in progress, as if the EOT flag
+ * had been set prior to the last transmission. This capability is included to support cases where
+ * it is not known when transmit data is written that it will be the end of a transfer. The bit
+ * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end
+ * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
+ */
+#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
+#define SPI_STAT_MSTIDLE_MASK (0x100U)
+#define SPI_STAT_MSTIDLE_SHIFT (8U)
+/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle.
+ * This means that the transmit holding register is empty and the transmitter is not in the
+ * process of sending data.
+ */
+#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+/*! @{ */
+#define SPI_INTENSET_SSAEN_MASK (0x10U)
+#define SPI_INTENSET_SSAEN_SHIFT (4U)
+/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.
+ * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
+ * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
+ */
+#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
+#define SPI_INTENSET_SSDEN_MASK (0x20U)
+#define SPI_INTENSET_SSDEN_SHIFT (5U)
+/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.
+ * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
+ * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
+ */
+#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
+#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
+#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
+/*! MSTIDLEEN - Master idle interrupt enable.
+ * 0b0..No interrupt will be generated when the SPI master function is idle.
+ * 0b1..An interrupt will be generated when the SPI master function is fully idle.
+ */
+#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
+/*! @{ */
+#define SPI_INTENCLR_SSAEN_MASK (0x10U)
+#define SPI_INTENCLR_SSAEN_SHIFT (4U)
+/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
+#define SPI_INTENCLR_SSDEN_MASK (0x20U)
+#define SPI_INTENCLR_SSDEN_SHIFT (5U)
+/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
+#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
+#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
+/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name DIV - SPI clock Divider */
+/*! @{ */
+#define SPI_DIV_DIVVAL_MASK (0xFFFFU)
+#define SPI_DIV_DIVVAL_SHIFT (0U)
+/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the
+ * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1,
+ * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results
+ * in FCLK/65536.
+ */
+#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - SPI Interrupt Status */
+/*! @{ */
+#define SPI_INTSTAT_SSA_MASK (0x10U)
+#define SPI_INTSTAT_SSA_SHIFT (4U)
+/*! SSA - Slave Select Assert.
+ */
+#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
+#define SPI_INTSTAT_SSD_MASK (0x20U)
+#define SPI_INTSTAT_SSD_SHIFT (5U)
+/*! SSD - Slave Select Deassert.
+ */
+#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
+#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
+#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
+/*! MSTIDLE - Master Idle status flag.
+ */
+#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+/*! @{ */
+#define SPI_FIFOCFG_ENABLETX_MASK (0x1U)
+#define SPI_FIFOCFG_ENABLETX_SHIFT (0U)
+/*! ENABLETX - Enable the transmit FIFO.
+ * 0b0..The transmit FIFO is not enabled.
+ * 0b1..The transmit FIFO is enabled.
+ */
+#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
+#define SPI_FIFOCFG_ENABLERX_MASK (0x2U)
+#define SPI_FIFOCFG_ENABLERX_SHIFT (1U)
+/*! ENABLERX - Enable the receive FIFO.
+ * 0b0..The receive FIFO is not enabled.
+ * 0b1..The receive FIFO is enabled.
+ */
+#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
+#define SPI_FIFOCFG_SIZE_MASK (0x30U)
+#define SPI_FIFOCFG_SIZE_SHIFT (4U)
+/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
+ * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
+ */
+#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
+#define SPI_FIFOCFG_DMATX_MASK (0x1000U)
+#define SPI_FIFOCFG_DMATX_SHIFT (12U)
+/*! DMATX - DMA configuration for transmit.
+ * 0b0..DMA is not used for the transmit function.
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
+#define SPI_FIFOCFG_DMARX_MASK (0x2000U)
+#define SPI_FIFOCFG_DMARX_SHIFT (13U)
+/*! DMARX - DMA configuration for receive.
+ * 0b0..DMA is not used for the receive function.
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
+#define SPI_FIFOCFG_WAKETX_MASK (0x4000U)
+#define SPI_FIFOCFG_WAKETX_SHIFT (14U)
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ * Wake-up control register.
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
+ * FIFOTRIG, even when the TXLVL interrupt is not enabled.
+ */
+#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
+#define SPI_FIFOCFG_WAKERX_MASK (0x8000U)
+#define SPI_FIFOCFG_WAKERX_SHIFT (15U)
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ * Wake-up control register.
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
+ * FIFOTRIG, even when the RXLVL interrupt is not enabled.
+ */
+#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
+#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
+ */
+#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
+#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
+ */
+#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO status register. */
+/*! @{ */
+#define SPI_FIFOSTAT_TXERR_MASK (0x1U)
+#define SPI_FIFOSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
+ * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
+ * needed. Cleared by writing a 1 to this bit.
+ */
+#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
+#define SPI_FIFOSTAT_RXERR_MASK (0x2U)
+#define SPI_FIFOSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
+ * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
+ */
+#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
+#define SPI_FIFOSTAT_PERINT_MASK (0x8U)
+#define SPI_FIFOSTAT_PERINT_SHIFT (3U)
+/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
+ * an interrupt. The details can be found by reading the peripheral's STAT register.
+ */
+#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
+#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
+ */
+#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
+#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
+ * written. When 0, the transmit FIFO is full and another write would cause it to overflow.
+ */
+#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
+ */
+#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+#define SPI_FIFOSTAT_RXFULL_MASK (0x80U)
+#define SPI_FIFOSTAT_RXFULL_SHIFT (7U)
+/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
+ * prevent the peripheral from causing an overflow.
+ */
+#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
+#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define SPI_FIFOSTAT_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
+ * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
+ * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
+ * 0.
+ */
+#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
+#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define SPI_FIFOSTAT_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
+ * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
+ * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
+ * 1.
+ */
+#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+/*! @{ */
+#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
+ * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
+ */
+#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
+#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
+ * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
+ */
+#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
+#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define SPI_FIFOTRIG_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
+ * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
+ * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
+ * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
+ * FIFO level decreases to 15 entries (is no longer full).
+ */
+#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
+#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define SPI_FIFOTRIG_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
+ * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
+ * can wake up the device just enough to perform DMA, then return to the reduced power mode. See
+ * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
+ * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
+ * FIFO has received 16 entries (has become full).
+ */
+#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+/*! @{ */
+#define SPI_FIFOINTENSET_TXERR_MASK (0x1U)
+#define SPI_FIFOINTENSET_TXERR_SHIFT (0U)
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a transmit error.
+ * 0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
+#define SPI_FIFOINTENSET_RXERR_MASK (0x2U)
+#define SPI_FIFOINTENSET_RXERR_SHIFT (1U)
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a receive error.
+ * 0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
+#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
+ * specified by the TXLVL field in the FIFOTRIG register.
+ * 0b0..No interrupt will be generated based on the TX FIFO level.
+ * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
+ * to the level specified by TXLVL in the FIFOTRIG register.
+ */
+#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
+#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
+ * specified by the TXLVL field in the FIFOTRIG register.
+ * 0b0..No interrupt will be generated based on the RX FIFO level.
+ * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
+ * increases to the level specified by RXLVL in the FIFOTRIG register.
+ */
+#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+/*! @{ */
+#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)
+/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
+#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)
+/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
+#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)
+/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
+#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)
+/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+/*! @{ */
+#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO error.
+ */
+#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
+#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO error.
+ */
+#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
+#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit FIFO level interrupt.
+ */
+#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
+#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive FIFO level interrupt.
+ */
+#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
+#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)
+/*! PERINT - Peripheral interrupt.
+ */
+#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO write data. */
+/*! @{ */
+#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)
+#define SPI_FIFOWR_TXDATA_SHIFT (0U)
+/*! TXDATA - Transmit data to the FIFO.
+ */
+#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
+#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)
+/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.
+ * 0b0..SSEL0 asserted.
+ * 0b1..SSEL0 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
+#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)
+/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.
+ * 0b0..SSEL1 asserted.
+ * 0b1..SSEL1 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
+#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)
+/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.
+ * 0b0..SSEL2 asserted.
+ * 0b1..SSEL2 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
+#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
+/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.
+ * 0b0..SSEL3 asserted.
+ * 0b1..SSEL3 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
+#define SPI_FIFOWR_EOT_MASK (0x100000U)
+#define SPI_FIFOWR_EOT_SHIFT (20U)
+/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain
+ * so far at least the time specified by the Transfer_delay value in the DLY register.
+ * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
+ * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
+ */
+#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
+#define SPI_FIFOWR_EOF_MASK (0x200000U)
+#define SPI_FIFOWR_EOF_SHIFT (21U)
+/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value
+ * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay
+ * value = 0. This control can be used as part of the support for frame lengths greater than 16
+ * bits.
+ * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame.
+ * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be
+ * inserted before subsequent data is transmitted.
+ */
+#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
+#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)
+#define SPI_FIFOWR_RXIGNORE_SHIFT (22U)
+/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to
+ * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can
+ * be used with the DMA.
+ * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit
+ * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data
+ * is not read before new data is received.
+ * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received
+ * data. No receiver flags are generated.
+ */
+#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
+#define SPI_FIFOWR_LEN_MASK (0xF000000U)
+#define SPI_FIFOWR_LEN_SHIFT (24U)
+/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths
+ * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved.
+ * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data
+ * transfer is 16 bits in length.
+ */
+#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO read data. */
+/*! @{ */
+#define SPI_FIFORD_RXDATA_MASK (0xFFFFU)
+#define SPI_FIFORD_RXDATA_SHIFT (0U)
+/*! RXDATA - Received data from the FIFO.
+ */
+#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
+#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)
+/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved
+ * along with received data. The value will reflect the SSEL0 pin for both master and slave
+ * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
+ * pin is configured by the related SPOL bit in CFG.
+ */
+#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
+#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)
+/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved
+ * along with received data. The value will reflect the SSEL1 pin for both master and slave
+ * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
+ * pin is configured by the related SPOL bit in CFG.
+ */
+#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
+#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)
+/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved
+ * along with received data. The value will reflect the SSEL2 pin for both master and slave
+ * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
+ * pin is configured by the related SPOL bit in CFG.
+ */
+#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
+#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
+/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
+ * along with received data. The value will reflect the SSEL3 pin for both master and slave
+ * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
+ * pin is configured by the related SPOL bit in CFG.
+ */
+#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
+#define SPI_FIFORD_SOT_MASK (0x100000U)
+#define SPI_FIFORD_SOT_SHIFT (20U)
+/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
+ * from deasserted to asserted (i.e., any previous transfer has ended). This information can be
+ * used to identify the first piece of data in cases where the transfer length is greater than 16
+ * bits.
+ */
+#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+/*! @{ */
+#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)
+/*! RXDATA - Received data from the FIFO.
+ */
+#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)
+/*! RXSSEL0_N - Slave Select for receive.
+ */
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)
+/*! RXSSEL1_N - Slave Select for receive.
+ */
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)
+/*! RXSSEL2_N - Slave Select for receive.
+ */
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
+/*! RXSSEL3_N - Slave Select for receive.
+ */
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
+#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
+#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
+/*! SOT - Start of transfer flag.
+ */
+#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral identification register. */
+/*! @{ */
+#define SPI_ID_APERTURE_MASK (0xFFU)
+#define SPI_ID_APERTURE_SHIFT (0U)
+/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
+ */
+#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
+#define SPI_ID_MINOR_REV_MASK (0xF00U)
+#define SPI_ID_MINOR_REV_SHIFT (8U)
+/*! MINOR_REV - Minor revision of module implementation.
+ */
+#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
+#define SPI_ID_MAJOR_REV_MASK (0xF000U)
+#define SPI_ID_MAJOR_REV_SHIFT (12U)
+/*! MAJOR_REV - Major revision of module implementation.
+ */
+#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
+#define SPI_ID_ID_MASK (0xFFFF0000U)
+#define SPI_ID_ID_SHIFT (16U)
+/*! ID - Module identifier for the selected function.
+ */
+#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40086000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40087000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE (0x40088000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2 ((SPI_Type *)SPI2_BASE)
+/** Peripheral SPI3 base address */
+#define SPI3_BASE (0x40089000u)
+/** Peripheral SPI3 base pointer */
+#define SPI3 ((SPI_Type *)SPI3_BASE)
+/** Peripheral SPI4 base address */
+#define SPI4_BASE (0x4008A000u)
+/** Peripheral SPI4 base pointer */
+#define SPI4 ((SPI_Type *)SPI4_BASE)
+/** Peripheral SPI5 base address */
+#define SPI5_BASE (0x40096000u)
+/** Peripheral SPI5 base pointer */
+#define SPI5 ((SPI_Type *)SPI5_BASE)
+/** Peripheral SPI6 base address */
+#define SPI6_BASE (0x40097000u)
+/** Peripheral SPI6 base pointer */
+#define SPI6 ((SPI_Type *)SPI6_BASE)
+/** Peripheral SPI7 base address */
+#define SPI7_BASE (0x40098000u)
+/** Peripheral SPI7 base pointer */
+#define SPI7 ((SPI_Type *)SPI7_BASE)
+/** Peripheral SPI8 base address */
+#define SPI8_BASE (0x40099000u)
+/** Peripheral SPI8 base pointer */
+#define SPI8 ((SPI_Type *)SPI8_BASE)
+/** Peripheral SPI9 base address */
+#define SPI9_BASE (0x4009A000u)
+/** Peripheral SPI9 base pointer */
+#define SPI9 ((SPI_Type *)SPI9_BASE)
+/** Peripheral SPI10 base address */
+#define SPI10_BASE (0x4009F000u)
+/** Peripheral SPI10 base pointer */
+#define SPI10 ((SPI_Type *)SPI10_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE, SPI10_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9, SPI10 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPIFI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
+ * @{
+ */
+
+/** SPIFI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */
+ __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */
+ __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */
+ __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */
+ __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */
+ __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */
+ __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */
+ __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */
+} SPIFI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPIFI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Register_Masks SPIFI Register Masks
+ * @{
+ */
+
+/*! @name CTRL - SPIFI control register */
+/*! @{ */
+#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU)
+#define SPIFI_CTRL_TIMEOUT_SHIFT (0U)
+/*! TIMEOUT - This field contains the number of serial clock periods without the processor reading
+ * data in memory mode, which will cause the SPIFI hardware to terminate the command by driving
+ * the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory
+ * to enter a lower-power state.) If the processor reads data from the flash region after a
+ * time-out, the command in the Memory Command Register is issued again.
+ */
+#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
+#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U)
+#define SPIFI_CTRL_CSHIGH_SHIFT (16U)
+/*! CSHIGH - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one.
+ */
+#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
+#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U)
+#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U)
+/*! D_PRFTCH_DIS - This bit allows conditioning of memory mode prefetches based on the AHB HPROT
+ * (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt
+ * a speculative prefetch when it encounters data accesses.
+ */
+#define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_INTEN_MASK (0x400000U)
+#define SPIFI_CTRL_INTEN_SHIFT (22U)
+/*! INTEN - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request
+ * output. See INTRQ in the status register for further details.
+ */
+#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
+#define SPIFI_CTRL_MODE3_MASK (0x800000U)
+#define SPIFI_CTRL_MODE3_SHIFT (23U)
+/*! MODE3 - SPI Mode 3 select.
+ * 0b0..SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is
+ * captured, and keeps it low while CS is HIGH.
+ * 0b1..SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is
+ * HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but
+ * some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be
+ * 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the
+ * frame.
+ */
+#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
+#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U)
+#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U)
+/*! PRFTCH_DIS - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.
+ * 0b0..Enable. Cache prefetching enabled.
+ * 0b1..Disable. Disables prefetching of cache lines.
+ */
+#define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_DUAL_MASK (0x10000000U)
+#define SPIFI_CTRL_DUAL_SHIFT (28U)
+/*! DUAL - Select dual protocol.
+ * 0b0..Quad protocol. This protocol uses IO3:0.
+ * 0b1..Dual protocol. This protocol uses IO1:0.
+ */
+#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
+#define SPIFI_CTRL_RFCLK_MASK (0x20000000U)
+#define SPIFI_CTRL_RFCLK_SHIFT (29U)
+/*! RFCLK - Select active clock edge for input data.
+ * 0b0..Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation.
+ * 0b1..Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time
+ * in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in
+ * this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
+ */
+#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
+#define SPIFI_CTRL_FBCLK_MASK (0x40000000U)
+#define SPIFI_CTRL_FBCLK_SHIFT (30U)
+/*! FBCLK - Feedback clock select.
+ * 0b0..Internal clock. The SPIFI samples read data using an internal clock.
+ * 0b1..Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more
+ * time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no
+ * final falling edge on SCK on which to sample the last data bit of the frame.
+ */
+#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
+#define SPIFI_CTRL_DMAEN_MASK (0x80000000U)
+#define SPIFI_CTRL_DMAEN_SHIFT (31U)
+/*! DMAEN - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a
+ * DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA
+ * channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used
+ * in Command mode.
+ */
+#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
+/*! @} */
+
+/*! @name CMD - SPIFI command register */
+/*! @{ */
+#define SPIFI_CMD_DATALEN_MASK (0x3FFFU)
+#define SPIFI_CMD_DATALEN_SHIFT (0U)
+/*! DATALEN - Except when the POLL bit in this register is 1, this field controls how many data
+ * bytes are in the command. 0 indicates that the command does not contain a data field.
+ */
+#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
+#define SPIFI_CMD_POLL_MASK (0x4000U)
+#define SPIFI_CMD_POLL_SHIFT (14U)
+/*! POLL - This bit should be written as 1 only with an opcode that a) contains an input data field,
+ * and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status
+ * command). When this bit is 1, the SPIFI hardware continues to read bytes until the test
+ * specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by
+ * DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds,
+ * the SPIFI captures the byte that meets this test so that it can be read from the Data
+ * Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to
+ * inform software when this occurs
+ */
+#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
+#define SPIFI_CMD_DOUT_MASK (0x8000U)
+#define SPIFI_CMD_DOUT_SHIFT (15U)
+/*! DOUT - If the DATALEN field is not zero, this bit controls the direction of the data:
+ * 0b0..Input from serial flash.
+ * 0b1..Output to serial flash.
+ */
+#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
+#define SPIFI_CMD_INTLEN_MASK (0x70000U)
+#define SPIFI_CMD_INTLEN_SHIFT (16U)
+/*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may
+ * require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or
+ * 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control
+ * information, dummy and delay bytes. See the description of the Intermediate Data register for
+ * the contents of such bytes.
+ */
+#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
+#define SPIFI_CMD_FIELDFORM_MASK (0x180000U)
+#define SPIFI_CMD_FIELDFORM_SHIFT (19U)
+/*! FIELDFORM - This field controls how the fields of the command are sent.
+ * 0b00..All serial. All fields of the command are serial.
+ * 0b01..Quad/dual data. Data field is quad/dual, other fields are serial.
+ * 0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual.
+ * 0b11..All quad/dual. All fields of the command are in quad/dual format.
+ */
+#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
+#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U)
+#define SPIFI_CMD_FRAMEFORM_SHIFT (21U)
+/*! FRAMEFORM - This field controls the opcode and address fields.
+ * 0b000..Reserved.
+ * 0b001..Opcode. Opcode only, no address.
+ * 0b010..Opcode one byte. Opcode, least significant byte of address.
+ * 0b011..Opcode two bytes. Opcode, two least significant bytes of address.
+ * 0b100..Opcode three bytes. Opcode, three least significant bytes of address.
+ * 0b101..Opcode four bytes. Opcode, 4 bytes of address.
+ * 0b110..No opcode three bytes. No opcode, 3 least significant bytes of address.
+ * 0b111..No opcode four bytes. No opcode, 4 bytes of address.
+ */
+#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
+#define SPIFI_CMD_OPCODE_MASK (0xFF000000U)
+#define SPIFI_CMD_OPCODE_SHIFT (24U)
+/*! OPCODE - The opcode of the command (not used for some FRAMEFORM values).
+ */
+#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
+/*! @} */
+
+/*! @name ADDR - SPIFI address register */
+/*! @{ */
+#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU)
+#define SPIFI_ADDR_ADDRESS_SHIFT (0U)
+/*! ADDRESS - Address.
+ */
+#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IDATA - SPIFI intermediate data register */
+/*! @{ */
+#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU)
+#define SPIFI_IDATA_IDATA_SHIFT (0U)
+/*! IDATA - Value of intermediate bytes.
+ */
+#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
+/*! @} */
+
+/*! @name CLIMIT - SPIFI limit register */
+/*! @{ */
+#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU)
+#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U)
+/*! CLIMIT - Zero-based upper limit of cacheable memory
+ */
+#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
+/*! @} */
+
+/*! @name DATA - SPIFI data register */
+/*! @{ */
+#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU)
+#define SPIFI_DATA_DATA_SHIFT (0U)
+/*! DATA - Input or output data
+ */
+#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
+/*! @} */
+
+/*! @name MCMD - SPIFI memory command register */
+/*! @{ */
+#define SPIFI_MCMD_POLL_MASK (0x4000U)
+#define SPIFI_MCMD_POLL_SHIFT (14U)
+/*! POLL - This bit should be written as 0.
+ */
+#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
+#define SPIFI_MCMD_DOUT_MASK (0x8000U)
+#define SPIFI_MCMD_DOUT_SHIFT (15U)
+/*! DOUT - This bit should be written as 0.
+ */
+#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
+#define SPIFI_MCMD_INTLEN_MASK (0x70000U)
+#define SPIFI_MCMD_INTLEN_SHIFT (16U)
+/*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may
+ * require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or
+ * 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control
+ * information, dummy and delay bytes. See the description of the Intermediate Data register for
+ * the contents of such bytes.
+ */
+#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
+#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U)
+#define SPIFI_MCMD_FIELDFORM_SHIFT (19U)
+/*! FIELDFORM - This field controls how the fields of the command are sent.
+ * 0b00..All serial. All fields of the command are serial.
+ * 0b01..Quad/dual data. Data field is quad/dual, other fields are serial.
+ * 0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual.
+ * 0b11..All quad/dual. All fields of the command are in quad/dual format.
+ */
+#define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
+#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U)
+#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U)
+/*! FRAMEFORM - This field controls the opcode and address fields.
+ * 0b000..Reserved.
+ * 0b001..Opcode. Opcode only, no address.
+ * 0b010..Opcode one byte. Opcode, least-significant byte of address.
+ * 0b011..Opcode two bytes. Opcode, 2 least-significant bytes of address.
+ * 0b100..Opcode three bytes. Opcode, 3 least-significant bytes of address.
+ * 0b101..Opcode four bytes. Opcode, 4 bytes of address.
+ * 0b110..No opcode three bytes. No opcode, 3 least-significant bytes of address.
+ * 0b111..No opcode, 4 bytes of address.
+ */
+#define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
+#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U)
+#define SPIFI_MCMD_OPCODE_SHIFT (24U)
+/*! OPCODE - The opcode of the command (not used for some FRAMEFORM values).
+ */
+#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
+/*! @} */
+
+/*! @name STAT - SPIFI status register */
+/*! @{ */
+#define SPIFI_STAT_MCINIT_MASK (0x1U)
+#define SPIFI_STAT_MCINIT_SHIFT (0U)
+/*! MCINIT - This bit is set when software successfully writes the Memory Command register, and is
+ * cleared by Reset or by writing a 1 to the RESET bit in this register.
+ */
+#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
+#define SPIFI_STAT_CMD_MASK (0x2U)
+#define SPIFI_STAT_CMD_SHIFT (1U)
+/*! CMD - This bit is 1 when the Command register is written. It is cleared by a hardware reset, a
+ * write to the RESET bit in this register, or the deassertion of CS which indicates that the
+ * command has completed communication with the SPI Flash.
+ */
+#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
+#define SPIFI_STAT_RESET_MASK (0x10U)
+#define SPIFI_STAT_RESET_SHIFT (4U)
+/*! RESET - Write a 1 to this bit to abort a current command or memory mode. This bit is cleared
+ * when the hardware is ready for a new command to be written to the Command register.
+ */
+#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
+#define SPIFI_STAT_INTRQ_MASK (0x20U)
+#define SPIFI_STAT_INTRQ_SHIFT (5U)
+/*! INTRQ - This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This
+ * bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS.
+ */
+#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Register_Masks */
+
+
+/* SPIFI - Peripheral instance base addresses */
+/** Peripheral SPIFI0 base address */
+#define SPIFI0_BASE (0x40080000u)
+/** Peripheral SPIFI0 base pointer */
+#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE)
+/** Array initializer of SPIFI peripheral base addresses */
+#define SPIFI_BASE_ADDRS { SPIFI0_BASE }
+/** Array initializer of SPIFI peripheral base pointers */
+#define SPIFI_BASE_PTRS { SPIFI0 }
+/** Interrupt vectors for the SPIFI peripheral type */
+#define SPIFI_IRQS { SPIFI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SYSCON Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCON - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[16];
+ __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */
+ uint8_t RESERVED_1[44];
+ __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */
+ __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */
+ uint8_t RESERVED_3[112];
+ __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */
+ uint8_t RESERVED_5[40];
+ __IO uint32_t PRESETCTRL[3]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */
+ uint8_t RESERVED_6[20];
+ __O uint32_t PRESETCTRLSET[3]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */
+ uint8_t RESERVED_7[20];
+ __O uint32_t PRESETCTRLCLR[3]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */
+ uint8_t RESERVED_8[164];
+ __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */
+ uint8_t RESERVED_9[12];
+ __IO uint32_t AHBCLKCTRL[3]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_10[20];
+ __O uint32_t AHBCLKCTRLSET[3]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */
+ uint8_t RESERVED_11[20];
+ __O uint32_t AHBCLKCTRLCLR[3]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */
+ uint8_t RESERVED_12[48];
+ __IO uint32_t STICKCLKSEL; /**< Systick timer clock source selection, offset: 0x27C */
+ __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */
+ __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */
+ __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */
+ uint8_t RESERVED_13[4];
+ __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */
+ uint8_t RESERVED_14[4];
+ __IO uint32_t AUDPLLCLKSEL; /**< Audio PLL clock source select, offset: 0x298 */
+ uint8_t RESERVED_15[4];
+ __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */
+ __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */
+ __IO uint32_t USB0CLKSEL; /**< USB0 clock source select, offset: 0x2A8 */
+ __IO uint32_t USB1CLKSEL; /**< USB1 clock source select, offset: 0x2AC */
+ __IO uint32_t FCLKSEL[10]; /**< Flexcomm clock source select, array offset: 0x2B0, array step: 0x4 */
+ __IO uint32_t FCLKSEL10; /**< Flexcomm 10 clock source select, offset: 0x2D8 */
+ uint8_t RESERVED_16[4];
+ __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */
+ uint8_t RESERVED_17[4];
+ __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */
+ __IO uint32_t DMICCLKSEL; /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */
+ __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */
+ __IO uint32_t LCDCLKSEL; /**< LCD clock source select, offset: 0x2F4 */
+ __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */
+ uint8_t RESERVED_18[4];
+ __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */
+ __IO uint32_t ARMTRACECLKDIV; /**< ARM Trace clock divider, offset: 0x304 */
+ __IO uint32_t CAN0CLKDIV; /**< MCAN0 clock divider, offset: 0x308 */
+ __IO uint32_t CAN1CLKDIV; /**< MCAN1 clock divider, offset: 0x30C */
+ __IO uint32_t SC0CLKDIV; /**< Smartcard0 clock divider, offset: 0x310 */
+ __IO uint32_t SC1CLKDIV; /**< Smartcard1 clock divider, offset: 0x314 */
+ uint8_t RESERVED_19[104];
+ __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */
+ __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */
+ __IO uint32_t FROHFDIV; /**< FROHF clock divider, offset: 0x388 */
+ uint8_t RESERVED_20[4];
+ __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */
+ __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */
+ __IO uint32_t USB0CLKDIV; /**< USB0 clock divider, offset: 0x398 */
+ __IO uint32_t USB1CLKDIV; /**< USB1 clock divider, offset: 0x39C */
+ __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */
+ uint8_t RESERVED_21[4];
+ __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */
+ __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */
+ __IO uint32_t LCDCLKDIV; /**< LCD clock divider, offset: 0x3B0 */
+ __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */
+ __IO uint32_t EMCCLKDIV; /**< EMC clock divider, offset: 0x3B8 */
+ __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */
+ uint8_t RESERVED_22[76];
+ __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */
+ __IO uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */
+ uint8_t RESERVED_23[4];
+ __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */
+ uint8_t RESERVED_24[4];
+ __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */
+ __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */
+ __IO uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */
+ uint8_t RESERVED_25[24];
+ __IO uint32_t EMCSYSCTRL; /**< EMC system control, offset: 0x444 */
+ __IO uint32_t EMCDYCTRL; /**< EMC clock delay control, offset: 0x448 */
+ __IO uint32_t EMCCAL; /**< EMC delay chain calibration control, offset: 0x44C */
+ __IO uint32_t ETHPHYSEL; /**< Ethernet PHY Selection, offset: 0x450 */
+ __IO uint32_t ETHSBDCTRL; /**< Ethernet SBD flow control, offset: 0x454 */
+ uint8_t RESERVED_26[8];
+ __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
+ uint8_t RESERVED_27[12];
+ __IO uint32_t KEYMUXSEL; /**< AES key source selection, offset: 0x470 */
+ uint8_t RESERVED_28[140];
+ __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */
+ __IO uint32_t SYSOSCCTRL; /**< System oscillator control, offset: 0x504 */
+ __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */
+ __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */
+ uint8_t RESERVED_29[12];
+ __IO uint32_t USBPLLCTRL; /**< USB PLL control, offset: 0x51C */
+ __IO uint32_t USBPLLSTAT; /**< USB PLL status, offset: 0x520 */
+ uint8_t RESERVED_30[92];
+ __IO uint32_t SYSPLLCTRL; /**< System PLL control, offset: 0x580 */
+ __IO uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */
+ __IO uint32_t SYSPLLNDEC; /**< PLL N divider, offset: 0x588 */
+ __IO uint32_t SYSPLLPDEC; /**< PLL P divider, offset: 0x58C */
+ __IO uint32_t SYSPLLMDEC; /**< System PLL M divider, offset: 0x590 */
+ uint8_t RESERVED_31[12];
+ __IO uint32_t AUDPLLCTRL; /**< Audio PLL control, offset: 0x5A0 */
+ __IO uint32_t AUDPLLSTAT; /**< Audio PLL status, offset: 0x5A4 */
+ __IO uint32_t AUDPLLNDEC; /**< Audio PLL N divider, offset: 0x5A8 */
+ __IO uint32_t AUDPLLPDEC; /**< Audio PLL P divider, offset: 0x5AC */
+ __IO uint32_t AUDPLLMDEC; /**< Audio PLL M divider, offset: 0x5B0 */
+ __IO uint32_t AUDPLLFRAC; /**< Audio PLL fractional divider control, offset: 0x5B4 */
+ uint8_t RESERVED_32[72];
+ __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register, array offset: 0x600, array step: 0x4 */
+ uint8_t RESERVED_33[8];
+ __IO uint32_t PDRUNCFG[2]; /**< Power configuration register, array offset: 0x610, array step: 0x4 */
+ uint8_t RESERVED_34[8];
+ __IO uint32_t PDRUNCFGSET[2]; /**< Power configuration set register, array offset: 0x620, array step: 0x4 */
+ uint8_t RESERVED_35[8];
+ __IO uint32_t PDRUNCFGCLR[2]; /**< Power configuration clear register, array offset: 0x630, array step: 0x4 */
+ uint8_t RESERVED_36[72];
+ __IO uint32_t STARTER[2]; /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */
+ uint8_t RESERVED_37[24];
+ __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */
+ uint8_t RESERVED_38[24];
+ __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */
+ uint8_t RESERVED_39[184];
+ __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */
+ uint8_t RESERVED_40[1664];
+ __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */
+ uint8_t RESERVED_41[492];
+ __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */
+ __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */
+ __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */
+ uint8_t RESERVED_42[127044];
+ __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */
+} SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SYSCON Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
+ * @{
+ */
+
+/*! @name AHBMATPRIO - AHB multilayer matrix priority control */
+/*! @{ */
+#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U)
+#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U)
+/*! PRI_ICODE - I-Code bus priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U)
+/*! PRI_DCODE - D-Code bus priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U)
+#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U)
+/*! PRI_SYS - System bus priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC0U)
+#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (6U)
+/*! PRI_DMA - DMA controller priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)
+#define SYSCON_AHBMATPRIO_PRI_ETH_MASK (0x300U)
+#define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT (8U)
+/*! PRI_ETH - Ethernet DMA priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK)
+#define SYSCON_AHBMATPRIO_PRI_LCD_MASK (0xC00U)
+#define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT (10U)
+/*! PRI_LCD - LCD DMA priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB0_MASK (0x3000U)
+#define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT (12U)
+/*! PRI_USB0 - USB0 DMA priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB1_MASK (0xC000U)
+#define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT (14U)
+/*! PRI_USB1 - USB1 DMA priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U)
+/*! PRI_SDIO - SDIO priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK (0xC0000U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT (18U)
+/*! PRI_MCAN1 - MCAN1 priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK (0x300000U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT (20U)
+/*! PRI_MCAN2 - MCAN2 priority.
+ */
+#define SYSCON_AHBMATPRIO_PRI_MCAN2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK)
+/*! @} */
+
+/*! @name SYSTCKCAL - System tick counter calibration */
+/*! @{ */
+#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU)
+#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U)
+/*! CAL - System tick timer calibration value.
+ */
+#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)
+#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U)
+#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U)
+/*! SKEW - Initial value for the Systick timer.
+ */
+#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)
+#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U)
+#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U)
+/*! NOREF - Initial value for the Systick timer.
+ */
+#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)
+/*! @} */
+
+/*! @name NMISRC - NMI Source Select */
+/*! @{ */
+#define SYSCON_NMISRC_IRQM4_MASK (0x3FU)
+#define SYSCON_NMISRC_IRQM4_SHIFT (0U)
+/*! IRQM4 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4.
+ */
+#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)
+#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U)
+#define SYSCON_NMISRC_NMIENM4_SHIFT (31U)
+/*! NMIENM4 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4.
+ */
+#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCTRL - Asynchronous APB Control */
+/*! @{ */
+#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U)
+#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U)
+/*! ENABLE - Enables the asynchronous APB bridge and subsystem.
+ * 0b0..Disabled. Asynchronous APB bridge is disabled.
+ * 0b1..Enabled. Asynchronous APB bridge is enabled.
+ */
+#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)
+/*! @} */
+
+/*! @name PIOPORCAP - POR captured value of port n */
+/*! @{ */
+#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU)
+#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U)
+/*! PIOPORCAP - State of PIOn_31 through PIOn_0 at power-on reset
+ */
+#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)
+/*! @} */
+
+/* The count of SYSCON_PIOPORCAP */
+#define SYSCON_PIOPORCAP_COUNT (2U)
+
+/*! @name PIORESCAP - Reset captured value of port n */
+/*! @{ */
+#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU)
+#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U)
+/*! PIORESCAP - State of PIOn_31 through PIOn_0 for resets other than POR.
+ */
+#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)
+/*! @} */
+
+/* The count of SYSCON_PIORESCAP */
+#define SYSCON_PIORESCAP_COUNT (2U)
+
+/*! @name PRESETCTRL - Peripheral reset control n */
+/*! @{ */
+#define SYSCON_PRESETCTRL_MRT_RST_MASK (0x1U)
+#define SYSCON_PRESETCTRL_MRT_RST_SHIFT (0U)
+/*! MRT_RST - Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK)
+#define SYSCON_PRESETCTRL_LCD_RST_MASK (0x4U)
+#define SYSCON_PRESETCTRL_LCD_RST_SHIFT (2U)
+/*! LCD_RST - LCD reset control.
+ */
+#define SYSCON_PRESETCTRL_LCD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK)
+#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U)
+#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U)
+/*! SCT0_RST - State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)
+#define SYSCON_PRESETCTRL_SDIO_RST_MASK (0x8U)
+#define SYSCON_PRESETCTRL_SDIO_RST_SHIFT (3U)
+/*! SDIO_RST - SDIO reset control.
+ */
+#define SYSCON_PRESETCTRL_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1H_RST_MASK (0x10U)
+#define SYSCON_PRESETCTRL_USB1H_RST_SHIFT (4U)
+/*! USB1H_RST - USB1 Host reset control.
+ */
+#define SYSCON_PRESETCTRL_USB1H_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1D_RST_MASK (0x20U)
+#define SYSCON_PRESETCTRL_USB1D_RST_SHIFT (5U)
+/*! USB1D_RST - USB1 Device reset control.
+ */
+#define SYSCON_PRESETCTRL_USB1D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1RAM_RST_MASK (0x40U)
+#define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT (6U)
+/*! USB1RAM_RST - USB1 RAM reset control.
+ */
+#define SYSCON_PRESETCTRL_USB1RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK)
+#define SYSCON_PRESETCTRL_EMC_RESET_MASK (0x80U)
+#define SYSCON_PRESETCTRL_EMC_RESET_SHIFT (7U)
+/*! EMC_RESET - EMC reset control.
+ */
+#define SYSCON_PRESETCTRL_EMC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK)
+#define SYSCON_PRESETCTRL_MCAN0_RST_MASK (0x80U)
+#define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT (7U)
+/*! MCAN0_RST - 0 = Clear reset to this function.
+ */
+#define SYSCON_PRESETCTRL_MCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK)
+#define SYSCON_PRESETCTRL_ETH_RST_MASK (0x100U)
+#define SYSCON_PRESETCTRL_ETH_RST_SHIFT (8U)
+/*! ETH_RST - Ethernet reset control.
+ */
+#define SYSCON_PRESETCTRL_ETH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK)
+#define SYSCON_PRESETCTRL_MCAN1_RST_MASK (0x100U)
+#define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT (8U)
+/*! MCAN1_RST - 0 = Clear reset to this function.
+ */
+#define SYSCON_PRESETCTRL_MCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO4_RST_MASK (0x200U)
+#define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT (9U)
+/*! GPIO4_RST - GPIO4 reset control.
+ */
+#define SYSCON_PRESETCTRL_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO5_RST_MASK (0x400U)
+#define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT (10U)
+/*! GPIO5_RST - GPIO5 reset control.
+ */
+#define SYSCON_PRESETCTRL_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK)
+#define SYSCON_PRESETCTRL_SPIFI_RST_MASK (0x400U)
+#define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT (10U)
+/*! SPIFI_RST - SPIFI reset control.
+ */
+#define SYSCON_PRESETCTRL_SPIFI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK)
+#define SYSCON_PRESETCTRL_UTICK_RST_MASK (0x400U)
+#define SYSCON_PRESETCTRL_UTICK_RST_SHIFT (10U)
+/*! UTICK_RST - Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK)
+#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U)
+#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U)
+/*! FC0_RST - Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)
+#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U)
+#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U)
+/*! MUX_RST - Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)
+#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U)
+#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U)
+/*! FC1_RST - Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)
+#define SYSCON_PRESETCTRL_OTP_RST_MASK (0x1000U)
+#define SYSCON_PRESETCTRL_OTP_RST_SHIFT (12U)
+/*! OTP_RST - OTP reset control.
+ */
+#define SYSCON_PRESETCTRL_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK)
+#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U)
+#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U)
+/*! FC2_RST - Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)
+#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U)
+#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U)
+/*! IOCON_RST - IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)
+#define SYSCON_PRESETCTRL_RNG_RST_MASK (0x2000U)
+#define SYSCON_PRESETCTRL_RNG_RST_SHIFT (13U)
+/*! RNG_RST - RNG reset control.
+ */
+#define SYSCON_PRESETCTRL_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK)
+#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U)
+#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U)
+/*! FC3_RST - Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)
+#define SYSCON_PRESETCTRL_FC8_RST_MASK (0x4000U)
+#define SYSCON_PRESETCTRL_FC8_RST_SHIFT (14U)
+/*! FC8_RST - Flexcomm 8 reset control.
+ */
+#define SYSCON_PRESETCTRL_FC8_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U)
+#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U)
+/*! GPIO0_RST - GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)
+#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U)
+#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U)
+/*! FC4_RST - Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)
+#define SYSCON_PRESETCTRL_FC9_RST_MASK (0x8000U)
+#define SYSCON_PRESETCTRL_FC9_RST_SHIFT (15U)
+/*! FC9_RST - Flexcomm 9 reset control.
+ */
+#define SYSCON_PRESETCTRL_FC9_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U)
+#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U)
+/*! GPIO1_RST - GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)
+#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U)
+#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U)
+/*! FC5_RST - Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO2_RST_MASK (0x10000U)
+#define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT (16U)
+/*! GPIO2_RST - GPIO2 reset control.
+ */
+#define SYSCON_PRESETCTRL_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0HMR_RST_MASK (0x10000U)
+#define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT (16U)
+/*! USB0HMR_RST - USB0 HOST master reset control.
+ */
+#define SYSCON_PRESETCTRL_USB0HMR_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK)
+#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U)
+#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U)
+/*! FC6_RST - Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO3_RST_MASK (0x20000U)
+#define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT (17U)
+/*! GPIO3_RST - GPIO3 reset control.
+ */
+#define SYSCON_PRESETCTRL_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0HSL_RST_MASK (0x20000U)
+#define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT (17U)
+/*! USB0HSL_RST - USB0 HOST slave reset control.
+ */
+#define SYSCON_PRESETCTRL_USB0HSL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK)
+#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U)
+#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U)
+/*! FC7_RST - Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)
+#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U)
+#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U)
+/*! PINT_RST - Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)
+#define SYSCON_PRESETCTRL_SHA_RST_MASK (0x40000U)
+#define SYSCON_PRESETCTRL_SHA_RST_SHIFT (18U)
+/*! SHA_RST - SHA reset control.
+ */
+#define SYSCON_PRESETCTRL_SHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK)
+#define SYSCON_PRESETCTRL_DMIC_RST_MASK (0x80000U)
+#define SYSCON_PRESETCTRL_DMIC_RST_SHIFT (19U)
+/*! DMIC_RST - Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK)
+#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U)
+#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U)
+/*! GINT_RST - Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)
+#define SYSCON_PRESETCTRL_SC0_RST_MASK (0x80000U)
+#define SYSCON_PRESETCTRL_SC0_RST_SHIFT (19U)
+/*! SC0_RST - Smart card 0 reset control.
+ */
+#define SYSCON_PRESETCTRL_SC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK)
+#define SYSCON_PRESETCTRL_DMA_RST_MASK (0x100000U)
+#define SYSCON_PRESETCTRL_DMA_RST_SHIFT (20U)
+/*! DMA_RST - DMA reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_DMA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA_RST_MASK)
+#define SYSCON_PRESETCTRL_SC1_RST_MASK (0x100000U)
+#define SYSCON_PRESETCTRL_SC1_RST_SHIFT (20U)
+/*! SC1_RST - Smart card 1 reset control.
+ */
+#define SYSCON_PRESETCTRL_SC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK)
+#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U)
+#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U)
+/*! CRC_RST - CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)
+#define SYSCON_PRESETCTRL_FC10_RST_MASK (0x200000U)
+#define SYSCON_PRESETCTRL_FC10_RST_SHIFT (21U)
+/*! FC10_RST - Flexcomm 10 reset control.
+ */
+#define SYSCON_PRESETCTRL_FC10_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC10_RST_SHIFT)) & SYSCON_PRESETCTRL_FC10_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U)
+/*! CTIMER2_RST - CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function
+ */
+#define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)
+#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U)
+#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U)
+/*! WWDT_RST - Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0D_RST_MASK (0x2000000U)
+#define SYSCON_PRESETCTRL_USB0D_RST_SHIFT (25U)
+/*! USB0D_RST - USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_USB0D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U)
+/*! CTIMER0_RST - CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)
+#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U)
+#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U)
+/*! ADC0_RST - ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U)
+/*! CTIMER1_RST - CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)
+/*! @} */
+
+/* The count of SYSCON_PRESETCTRL */
+#define SYSCON_PRESETCTRL_COUNT (3U)
+
+/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */
+/*! @{ */
+#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U)
+/*! RST_SET - Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn
+ * register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn
+ * are reserved and only zeroes should be written to them.
+ */
+#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)
+/*! @} */
+
+/* The count of SYSCON_PRESETCTRLSET */
+#define SYSCON_PRESETCTRLSET_COUNT (3U)
+
+/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */
+/*! @{ */
+#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U)
+/*! RST_CLR - Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn
+ * register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn
+ * are reserved and only zeroes should be written to them.
+ */
+#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)
+/*! @} */
+
+/* The count of SYSCON_PRESETCTRLCLR */
+#define SYSCON_PRESETCTRLCLR_COUNT (3U)
+
+/*! @name SYSRSTSTAT - System reset status register */
+/*! @{ */
+#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U)
+#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U)
+/*! POR - POR reset status
+ * 0b0..No POR detected
+ * 0b1..POR detected. Writing a one clears this reset.
+ */
+#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)
+#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U)
+#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U)
+/*! EXTRST - Status of the external RESET pin. External reset status
+ * 0b0..No reset event detected.
+ * 0b1..Reset detected. Writing a one clears this reset.
+ */
+#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
+#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U)
+#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U)
+/*! WDT - Status of the Watchdog reset
+ * 0b0..No WDT reset detected
+ * 0b1..WDT reset detected. Writing a one clears this reset.
+ */
+#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
+#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U)
+#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U)
+/*! BOD - Status of the Brown-out detect reset
+ * 0b0..No BOD reset detected
+ * 0b1..BOD reset detected. Writing a one clears this reset.
+ */
+#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)
+#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U)
+#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U)
+/*! SYSRST - Status of the software system reset
+ * 0b0..No System reset detected
+ * 0b1..System reset detected. Writing a one clears this reset.
+ */
+#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
+/*! @} */
+
+/*! @name AHBCLKCTRL - AHB Clock control n */
+/*! @{ */
+#define SYSCON_AHBCLKCTRL_MRT_MASK (0x1U)
+#define SYSCON_AHBCLKCTRL_MRT_SHIFT (0U)
+/*! MRT - Enables the clock for the Multi-Rate Timer.
+ */
+#define SYSCON_AHBCLKCTRL_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK)
+#define SYSCON_AHBCLKCTRL_RIT_MASK (0x2U)
+#define SYSCON_AHBCLKCTRL_RIT_SHIFT (1U)
+/*! RIT - Enables the clock for the Repetitive Interrupt Timer.
+ */
+#define SYSCON_AHBCLKCTRL_RIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK)
+#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U)
+#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U)
+/*! ROM - Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)
+#define SYSCON_AHBCLKCTRL_LCD_MASK (0x4U)
+#define SYSCON_AHBCLKCTRL_LCD_SHIFT (2U)
+/*! LCD - Enables the clock for the LCD interface.
+ */
+#define SYSCON_AHBCLKCTRL_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK)
+#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U)
+#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U)
+/*! SCT0 - Enables the clock for SCT0.
+ */
+#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)
+#define SYSCON_AHBCLKCTRL_SDIO_MASK (0x8U)
+#define SYSCON_AHBCLKCTRL_SDIO_SHIFT (3U)
+/*! SDIO - Enables the clock for the SDIO interface.
+ */
+#define SYSCON_AHBCLKCTRL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U)
+#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U)
+/*! SRAM1 - Enables the clock for SRAM1. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U)
+#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U)
+/*! SRAM2 - Enables the clock for SRAM2. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)
+#define SYSCON_AHBCLKCTRL_USB1H_MASK (0x10U)
+#define SYSCON_AHBCLKCTRL_USB1H_SHIFT (4U)
+/*! USB1H - Enables the clock for the USB1 host interface.
+ */
+#define SYSCON_AHBCLKCTRL_USB1H(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM3_MASK (0x20U)
+#define SYSCON_AHBCLKCTRL_SRAM3_SHIFT (5U)
+/*! SRAM3 - Enables the clock for SRAM3.
+ */
+#define SYSCON_AHBCLKCTRL_SRAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK)
+#define SYSCON_AHBCLKCTRL_USB1D_MASK (0x20U)
+#define SYSCON_AHBCLKCTRL_USB1D_SHIFT (5U)
+/*! USB1D - Enables the clock for the USB1 device interface.
+ */
+#define SYSCON_AHBCLKCTRL_USB1D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK)
+#define SYSCON_AHBCLKCTRL_USB1RAM_MASK (0x40U)
+#define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT (6U)
+/*! USB1RAM - Enables the clock for the USB1 RAM interface.
+ */
+#define SYSCON_AHBCLKCTRL_USB1RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK)
+#define SYSCON_AHBCLKCTRL_EMC_MASK (0x80U)
+#define SYSCON_AHBCLKCTRL_EMC_SHIFT (7U)
+/*! EMC - Enables the clock for the EMC interface.
+ */
+#define SYSCON_AHBCLKCTRL_EMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK)
+#define SYSCON_AHBCLKCTRL_MCAN0_MASK (0x80U)
+#define SYSCON_AHBCLKCTRL_MCAN0_SHIFT (7U)
+/*! MCAN0 - Enables the clock for MCAN0.
+ */
+#define SYSCON_AHBCLKCTRL_MCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK)
+#define SYSCON_AHBCLKCTRL_ETH_MASK (0x100U)
+#define SYSCON_AHBCLKCTRL_ETH_SHIFT (8U)
+/*! ETH - Enables the clock for the ethernet interface.
+ */
+#define SYSCON_AHBCLKCTRL_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK)
+#define SYSCON_AHBCLKCTRL_MCAN1_MASK (0x100U)
+#define SYSCON_AHBCLKCTRL_MCAN1_SHIFT (8U)
+/*! MCAN1 - Enables the clock for MCAN1.
+ */
+#define SYSCON_AHBCLKCTRL_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO4_MASK (0x200U)
+#define SYSCON_AHBCLKCTRL_GPIO4_SHIFT (9U)
+/*! GPIO4 - Enables the clock for the GPIO4 interface.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO5_MASK (0x400U)
+#define SYSCON_AHBCLKCTRL_GPIO5_SHIFT (10U)
+/*! GPIO5 - Enables the clock for the GPIO5 interface.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK)
+#define SYSCON_AHBCLKCTRL_SPIFI_MASK (0x400U)
+#define SYSCON_AHBCLKCTRL_SPIFI_SHIFT (10U)
+/*! SPIFI - Enables the clock for the SPIFI. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK)
+#define SYSCON_AHBCLKCTRL_UTICK_MASK (0x400U)
+#define SYSCON_AHBCLKCTRL_UTICK_SHIFT (10U)
+/*! UTICK - Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U)
+/*! FLEXCOMM0 - Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U)
+/*! INPUTMUX - Enables the clock for the input muxes. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U)
+/*! FLEXCOMM1 - Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)
+#define SYSCON_AHBCLKCTRL_OTP_MASK (0x1000U)
+#define SYSCON_AHBCLKCTRL_OTP_SHIFT (12U)
+/*! OTP - Enables the clock for the OTP interface.
+ */
+#define SYSCON_AHBCLKCTRL_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U)
+/*! FLEXCOMM2 - Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)
+#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U)
+#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U)
+/*! IOCON - Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)
+#define SYSCON_AHBCLKCTRL_RNG_MASK (0x2000U)
+#define SYSCON_AHBCLKCTRL_RNG_SHIFT (13U)
+/*! RNG - Enables the clock for the RNG interface.
+ */
+#define SYSCON_AHBCLKCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U)
+/*! FLEXCOMM3 - Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT (14U)
+/*! FLEXCOMM8 - Enables the clock for the Flexcomm8 interface.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U)
+#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U)
+/*! GPIO0 - Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U)
+/*! FLEXCOMM4 - Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT (15U)
+/*! FLEXCOMM9 - Enables the clock for the Flexcomm9 interface.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U)
+#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U)
+/*! GPIO1 - Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U)
+/*! FLEXCOMM5 - Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO2_MASK (0x10000U)
+#define SYSCON_AHBCLKCTRL_GPIO2_SHIFT (16U)
+/*! GPIO2 - Enables the clock for the GPIO2 port registers.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK)
+#define SYSCON_AHBCLKCTRL_USB0HMR_MASK (0x10000U)
+#define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT (16U)
+/*! USB0HMR - Enables the clock for the USB host master interface.
+ */
+#define SYSCON_AHBCLKCTRL_USB0HMR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U)
+/*! FLEXCOMM6 - Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO3_MASK (0x20000U)
+#define SYSCON_AHBCLKCTRL_GPIO3_SHIFT (17U)
+/*! GPIO3 - Enables the clock for the GPIO3 port registers.
+ */
+#define SYSCON_AHBCLKCTRL_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK)
+#define SYSCON_AHBCLKCTRL_USB0HSL_MASK (0x20000U)
+#define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT (17U)
+/*! USB0HSL - Enables the clock for the USB host slave interface.
+ */
+#define SYSCON_AHBCLKCTRL_USB0HSL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U)
+/*! FLEXCOMM7 - Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)
+#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U)
+#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U)
+/*! PINT - Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)
+#define SYSCON_AHBCLKCTRL_SHA_MASK (0x40000U)
+#define SYSCON_AHBCLKCTRL_SHA_SHIFT (18U)
+/*! SHA - Enables the clock for the SHA interface.
+ */
+#define SYSCON_AHBCLKCTRL_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA_SHIFT)) & SYSCON_AHBCLKCTRL_SHA_MASK)
+#define SYSCON_AHBCLKCTRL_DMIC_MASK (0x80000U)
+#define SYSCON_AHBCLKCTRL_DMIC_SHIFT (19U)
+/*! DMIC - Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK)
+#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U)
+#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U)
+/*! GINT - Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)
+#define SYSCON_AHBCLKCTRL_SC0_MASK (0x80000U)
+#define SYSCON_AHBCLKCTRL_SC0_SHIFT (19U)
+/*! SC0 - Enables the clock for the Smart card0 interface.
+ */
+#define SYSCON_AHBCLKCTRL_SC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK)
+#define SYSCON_AHBCLKCTRL_DMA_MASK (0x100000U)
+#define SYSCON_AHBCLKCTRL_DMA_SHIFT (20U)
+/*! DMA - Enables the clock for the DMA controller. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK)
+#define SYSCON_AHBCLKCTRL_SC1_MASK (0x100000U)
+#define SYSCON_AHBCLKCTRL_SC1_SHIFT (20U)
+/*! SC1 - Enables the clock for the Smart card1 interface.
+ */
+#define SYSCON_AHBCLKCTRL_SC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK)
+#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U)
+#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U)
+/*! CRC - Enables the clock for the CRC engine. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM10_MASK (0x200000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM10_SHIFT (21U)
+/*! FLEXCOMM10 - Enables the clock for the Flexcomm10 interface.
+ */
+#define SYSCON_AHBCLKCTRL_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM10_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM10_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U)
+#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U)
+/*! CTIMER2 - Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)
+#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U)
+#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U)
+/*! WWDT - Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)
+#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U)
+#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U)
+/*! RTC - Enables the bus clock for the RTC. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)
+#define SYSCON_AHBCLKCTRL_USB0D_MASK (0x2000000U)
+#define SYSCON_AHBCLKCTRL_USB0D_SHIFT (25U)
+/*! USB0D - Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_USB0D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U)
+/*! CTIMER0 - Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)
+#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U)
+#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U)
+/*! ADC0 - Enables the clock for the ADC0 register interface.
+ */
+#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U)
+/*! CTIMER1 - Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable.
+ */
+#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)
+/*! @} */
+
+/* The count of SYSCON_AHBCLKCTRL */
+#define SYSCON_AHBCLKCTRL_COUNT (3U)
+
+/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */
+/*! @{ */
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U)
+/*! CLK_SET - Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn
+ * register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn
+ * are reserved and only zeroes should be written to them.
+ */
+#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)
+/*! @} */
+
+/* The count of SYSCON_AHBCLKCTRLSET */
+#define SYSCON_AHBCLKCTRLSET_COUNT (3U)
+
+/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */
+/*! @{ */
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U)
+/*! CLK_CLR - Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn
+ * register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn
+ * are reserved and only zeroes should be written to them.
+ */
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)
+/*! @} */
+
+/* The count of SYSCON_AHBCLKCTRLCLR */
+#define SYSCON_AHBCLKCTRLCLR_COUNT (3U)
+
+/*! @name STICKCLKSEL - Systick timer clock source selection */
+/*! @{ */
+#define SYSCON_STICKCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_STICKCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Systick timer clock source selection
+ * 0b000..Main clock (main_clk)
+ * 0b001..Watchdog oscillator (wdt_clk)
+ * 0b010..RTC oscillator 32 kHz output (32k_clk)
+ * 0b011..FRO 12 MHz (fro_12m)
+ * 0b100..Reserved setting
+ * 0b101..Reserved setting
+ * 0b110..Reserved setting
+ * 0b111..None, this may be selected to reduce power when no output is needed.
+ */
+#define SYSCON_STICKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STICKCLKSEL_SEL_SHIFT)) & SYSCON_STICKCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name MAINCLKSELA - Main clock source select A */
+/*! @{ */
+#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U)
+#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U)
+/*! SEL - Clock source for main clock source selector A
+ * 0b00..FRO 12 MHz (fro_12m)
+ * 0b01..CLKIN (clk_in)
+ * 0b10..Watchdog oscillator (wdt_clk)
+ * 0b11..FRO 96 or 48 MHz (fro_hf)
+ */
+#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
+/*! @} */
+
+/*! @name MAINCLKSELB - Main clock source select B */
+/*! @{ */
+#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U)
+#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U)
+/*! SEL - Clock source for main clock source selector B. Selects the clock source for the main clock.
+ * 0b00..MAINCLKSELA. Use the clock source selected in MAINCLKSELA register.
+ * 0b01..Reserved setting
+ * 0b10..System PLL output (pll_clk)
+ * 0b11..RTC oscillator 32 kHz output (32k_clk)
+ */
+#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
+/*! @} */
+
+/*! @name CLKOUTSELA - CLKOUT clock source select A */
+/*! @{ */
+#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U)
+#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U)
+/*! SEL - CLKOUT clock source selection
+ * 0b000..Main clock (main_clk)
+ * 0b001..CLKIN (clk_in)
+ * 0b010..Watchdog oscillator (wdt_clk)
+ * 0b011..FRO 96 or 48 MHz (fro_hf)
+ * 0b100..PLL output (pll_clk)
+ * 0b101..USB PLL clock (usb_pll_clk)
+ * 0b110..Audio PLL clock (audio_pll_clk)
+ * 0b111..RTC oscillator 32 kHz output (32k_clk)
+ */
+#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)
+/*! @} */
+
+/*! @name SYSPLLCLKSEL - PLL clock source select */
+/*! @{ */
+#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U)
+/*! SEL - System PLL clock source selection.
+ * 0b000..FRO 12 MHz (fro_12m)
+ * 0b001..CLKIN (clk_in)
+ * 0b011..RTC oscillator 32 kHz output (32k_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name AUDPLLCLKSEL - Audio PLL clock source select */
+/*! @{ */
+#define SYSCON_AUDPLLCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_AUDPLLCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Audio PLL clock source selection.
+ * 0b000..FRO 12 MHz (fro_12m)
+ * 0b001..CLKIN (clk_in)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_AUDPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SPIFICLKSEL - SPIFI clock source select */
+/*! @{ */
+#define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U)
+#define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U)
+/*! SEL - System PLL clock source selection
+ * 0b000..Main clock (main_clk)
+ * 0b001..System PLL output (pll_clk)
+ * 0b010..USB PLL clock (usb_pll_clk)
+ * 0b011..FRO 96 or 48 MHz (fro_hf)
+ * 0b100..Audio PLL clock (audio_pll_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name ADCCLKSEL - ADC clock source select */
+/*! @{ */
+#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U)
+/*! SEL - ADC clock source selection
+ * 0b000..FRO 96 or 48 MHz (fro_hf)
+ * 0b001..System PLL output (pll_clk)
+ * 0b010..USB PLL clock (usb_pll_clk)
+ * 0b011..Audio PLL clock (audio_pll_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name USB0CLKSEL - USB0 clock source select */
+/*! @{ */
+#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U)
+#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U)
+/*! SEL - USB0 device clock source selection.
+ * 0b000..FRO 96 or 48 MHz (fro_hf)
+ * 0b001..System PLL output (pll_clk)
+ * 0b010..USB PLL clock (usb_pll_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name USB1CLKSEL - USB1 clock source select */
+/*! @{ */
+#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U)
+#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U)
+/*! SEL - USB1 PHY clock source selection.
+ * 0b000..Main clock (main_clk)
+ * 0b001..System PLL output (pll_clk)
+ * 0b010..USB PLL clock (usb_pll_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FCLKSEL - Flexcomm clock source select */
+/*! @{ */
+#define SYSCON_FCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_FCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Flexcomm clock source selection. One per Flexcomm.
+ * 0b000..FRO 12 MHz (fro_12m)
+ * 0b001..FRO HF DIV (fro_hf_div)
+ * 0b010..Audio PLL clock (audio_pll_clk)
+ * 0b011..MCLK pin input, when selected in IOCON (mclk_in)
+ * 0b100..FRG clock, the output of the fractional rate generator (frg_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK)
+/*! @} */
+
+/* The count of SYSCON_FCLKSEL */
+#define SYSCON_FCLKSEL_COUNT (10U)
+
+/*! @name FCLKSEL10 - Flexcomm 10 clock source select */
+/*! @{ */
+#define SYSCON_FCLKSEL10_SEL_MASK (0x7U)
+#define SYSCON_FCLKSEL10_SEL_SHIFT (0U)
+/*! SEL - Flexcomm clock source selection. One per Flexcomm.
+ * 0b000..Main clock (main_clk)
+ * 0b001..System PLL output (pll_clk)
+ * 0b010..USB PLL clock (usb_pll_clk)
+ * 0b011..FRO 96 or 48 MHz (fro_hf)
+ * 0b100..Audio PLL clock (audio_pll_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_FCLKSEL10_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL10_SEL_SHIFT)) & SYSCON_FCLKSEL10_SEL_MASK)
+/*! @} */
+
+/*! @name MCLKCLKSEL - MCLK clock source select */
+/*! @{ */
+#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U)
+/*! SEL - MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem.
+ * 0b000..FRO HF DIV (fro_hf_div)
+ * 0b001..Audio PLL clock (audio_pll_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */
+/*! @{ */
+#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Fractional Rate Generator clock source select.
+ * 0b000..Main clock (main_clk)
+ * 0b001..System PLL output (pll_clk)
+ * 0b010..FRO 12 MHz (fro_12m)
+ * 0b011..FRO 96 or 48 MHz (fro_hf)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */
+/*! @{ */
+#define SYSCON_DMICCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_DMICCLKSEL_SEL_SHIFT (0U)
+/*! SEL - DMIC (audio subsystem) clock source select.
+ * 0b000..FRO 12 MHz (fro_12m)
+ * 0b001..FRO HF DIV (fro_hf_div)
+ * 0b010..Audio PLL clock (audio_pll_clk)
+ * 0b011..MCLK pin input, when selected in IOCON (mclk_in)
+ * 0b100..Main clock (main_clk)
+ * 0b101..Watchdog oscillator (wdt_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SCTCLKSEL - SCTimer/PWM clock source select */
+/*! @{ */
+#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U)
+/*! SEL - SCT clock source select.
+ * 0b000..Main clock (main_clk)
+ * 0b001..System PLL output (pll_clk)
+ * 0b010..FRO 96 or 48 MHz (fro_hf)
+ * 0b011..Audio PLL clock (audio_pll_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name LCDCLKSEL - LCD clock source select */
+/*! @{ */
+#define SYSCON_LCDCLKSEL_SEL_MASK (0x3U)
+#define SYSCON_LCDCLKSEL_SEL_SHIFT (0U)
+/*! SEL - LCD clock source select.
+ * 0b00..Main clock (main_clk)
+ * 0b01..LCDCLKIN (LCDCLK_EXT)
+ * 0b10..FRO 96 or 48 MHz (fro_hf)
+ * 0b11..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_LCDCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SDIOCLKSEL - SDIO clock source select */
+/*! @{ */
+#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U)
+/*! SEL - SDIO clock source select.
+ * 0b000..Main clock (main_clk)
+ * 0b001..System PLL output (pll_clk)
+ * 0b010..USB PLL clock (usb_pll_clk)
+ * 0b011..FRO 96 or 48 MHz (fro_hf)
+ * 0b100..Audio PLL clock (audio_pll_clk)
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.
+ */
+#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SYSTICKCLKDIV - SYSTICK clock divider */
+/*! @{ */
+#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
+#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ * away rather than completing the previous count.
+ */
+#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
+#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SYSTICKCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name ARMTRACECLKDIV - ARM Trace clock divider */
+/*! @{ */
+#define SYSCON_ARMTRACECLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_ARMTRACECLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_ARMTRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK)
+#define SYSCON_ARMTRACECLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_ARMTRACECLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_ARMTRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK)
+#define SYSCON_ARMTRACECLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_ARMTRACECLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_ARMTRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_ARMTRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CAN0CLKDIV - MCAN0 clock divider */
+/*! @{ */
+#define SYSCON_CAN0CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_CAN0CLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_CAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK)
+#define SYSCON_CAN0CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_CAN0CLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_CAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK)
+#define SYSCON_CAN0CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_CAN0CLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_CAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK)
+#define SYSCON_CAN0CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_CAN0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CAN1CLKDIV - MCAN1 clock divider */
+/*! @{ */
+#define SYSCON_CAN1CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_CAN1CLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_CAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK)
+#define SYSCON_CAN1CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_CAN1CLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ * away rather than completing the previous count.
+ */
+#define SYSCON_CAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK)
+#define SYSCON_CAN1CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_CAN1CLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_CAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK)
+#define SYSCON_CAN1CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_CAN1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SC0CLKDIV - Smartcard0 clock divider */
+/*! @{ */
+#define SYSCON_SC0CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SC0CLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_SC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK)
+#define SYSCON_SC0CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SC0CLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_SC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK)
+#define SYSCON_SC0CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SC0CLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_SC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK)
+#define SYSCON_SC0CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SC0CLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SC0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SC1CLKDIV - Smartcard1 clock divider */
+/*! @{ */
+#define SYSCON_SC1CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SC1CLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_SC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK)
+#define SYSCON_SC1CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SC1CLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_SC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK)
+#define SYSCON_SC1CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SC1CLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_SC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK)
+#define SYSCON_SC1CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SC1CLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SC1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name AHBCLKDIV - AHB clock divider */
+/*! @{ */
+#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
+#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CLKOUTDIV - CLKOUT clock divider */
+/*! @{ */
+#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU)
+#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
+#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U)
+#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ * away rather than completing the previous count.
+ */
+#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
+#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U)
+#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ * without the risk of a glitch at the output.
+ */
+#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
+#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name FROHFDIV - FROHF clock divider */
+/*! @{ */
+#define SYSCON_FROHFDIV_DIV_MASK (0xFFU)
+#define SYSCON_FROHFDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)
+#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U)
+#define SYSCON_FROHFDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK)
+#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U)
+#define SYSCON_FROHFDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)
+#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SPIFICLKDIV - SPIFI clock divider */
+/*! @{ */
+#define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)
+#define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ * away rather than completing the previous count.
+ */
+#define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)
+#define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ * without the risk of a glitch at the output.
+ */
+#define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
+#define SYSCON_SPIFICLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SPIFICLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name ADCCLKDIV - ADC clock divider */
+/*! @{ */
+#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
+#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
+#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
+#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name USB0CLKDIV - USB0 clock divider */
+/*! @{ */
+#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
+#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
+#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
+#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name USB1CLKDIV - USB1 clock divider */
+/*! @{ */
+#define SYSCON_USB1CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_USB1CLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_USB1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK)
+#define SYSCON_USB1CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_USB1CLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_USB1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK)
+#define SYSCON_USB1CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_USB1CLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_USB1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK)
+#define SYSCON_USB1CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_USB1CLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_USB1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name FRGCTRL - Fractional rate divider */
+/*! @{ */
+#define SYSCON_FRGCTRL_DIV_MASK (0xFFU)
+#define SYSCON_FRGCTRL_DIV_SHIFT (0U)
+/*! DIV - Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set
+ * to 0xFF to use with the fractional baud rate generator.
+ */
+#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)
+#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U)
+#define SYSCON_FRGCTRL_MULT_SHIFT (8U)
+/*! MULT - Numerator of the fractional divider. MULT is equal to the programmed value.
+ */
+#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
+/*! @} */
+
+/*! @name DMICCLKDIV - DMIC clock divider */
+/*! @{ */
+#define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_DMICCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)
+#define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_DMICCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ * away rather than completing the previous count.
+ */
+#define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)
+#define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_DMICCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ * without the risk of a glitch at the output.
+ */
+#define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)
+#define SYSCON_DMICCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_DMICCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_DMICCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name MCLKDIV - I2S MCLK clock divider */
+/*! @{ */
+#define SYSCON_MCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_MCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
+ */
+#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
+#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_MCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
+#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_MCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
+#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name LCDCLKDIV - LCD clock divider */
+/*! @{ */
+#define SYSCON_LCDCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_LCDCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_LCDCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK)
+#define SYSCON_LCDCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_LCDCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_LCDCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK)
+#define SYSCON_LCDCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_LCDCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_LCDCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK)
+#define SYSCON_LCDCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_LCDCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_LCDCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SCTCLKDIV - SCT/PWM clock divider */
+/*! @{ */
+#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
+#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
+#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
+#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name EMCCLKDIV - EMC clock divider */
+/*! @{ */
+#define SYSCON_EMCCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_EMCCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_EMCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK)
+#define SYSCON_EMCCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_EMCCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_EMCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK)
+#define SYSCON_EMCCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_EMCCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_EMCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK)
+#define SYSCON_EMCCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_EMCCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_EMCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SDIOCLKDIV - SDIO clock divider */
+/*! @{ */
+#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value.
+ */
+#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
+#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter.
+ */
+#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
+#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter.
+ */
+#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
+#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag.
+ */
+#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name USB0CLKCTRL - USB0 clock control */
+/*! @{ */
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)
+/*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control.
+ */
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)
+/*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt.
+ */
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)
+/*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control.
+ */
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+/*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt.
+ */
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U)
+/*! PU_DISABLE - Internal pull-up disable control.
+ */
+#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)
+/*! @} */
+
+/*! @name USB0CLKSTAT - USB0 clock status */
+/*! @{ */
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)
+/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status.
+ */
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+/*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status.
+ */
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
+/*! @} */
+
+/*! @name FREQMECTRL - Frequency measure register */
+/*! @{ */
+#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU)
+#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U)
+/*! CAPVAL - Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only.
+ */
+#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)
+#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U)
+#define SYSCON_FREQMECTRL_PROG_SHIFT (31U)
+/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit
+ * when the measurement cycle has completed and there is valid capture data in the CAPVAL field
+ * (bits 13:0).
+ */
+#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)
+/*! @} */
+
+/*! @name MCLKIO - MCLK input/output control */
+/*! @{ */
+#define SYSCON_MCLKIO_DIR_MASK (0x1U)
+#define SYSCON_MCLKIO_DIR_SHIFT (0U)
+/*! DIR - MCLK direction control.
+ */
+#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)
+/*! @} */
+
+/*! @name USB1CLKCTRL - USB1 clock control */
+/*! @{ */
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)
+/*! AP_FS_DEV_CLK - USB1 Device need_clock signal control.
+ */
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)
+/*! POL_FS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt.
+ */
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)
+/*! AP_FS_HOST_CLK - USB1 Host need_clock signal control.
+ */
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+/*! POL_FS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt.
+ */
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
+/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active
+ * low) will result in exiting the low power mode; input to asynchronous control logic.
+ */
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)
+/*! @} */
+
+/*! @name USB1CLKSTAT - USB1 clock status */
+/*! @{ */
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)
+/*! DEV_NEED_CLKST - USB1 Device USB1_NEEDCLK signal status.
+ */
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+/*! HOST_NEED_CLKST - USB1 Device host USB1_NEEDCLK signal status.
+ */
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)
+/*! @} */
+
+/*! @name EMCSYSCTRL - EMC system control */
+/*! @{ */
+#define SYSCON_EMCSYSCTRL_EMCSC_MASK (0x1U)
+#define SYSCON_EMCSYSCTRL_EMCSC_SHIFT (0U)
+/*! EMCSC - EMC Shift Control.
+ */
+#define SYSCON_EMCSYSCTRL_EMCSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK)
+#define SYSCON_EMCSYSCTRL_EMCRD_MASK (0x2U)
+#define SYSCON_EMCSYSCTRL_EMCRD_SHIFT (1U)
+/*! EMCRD - EMC Reset Disable.
+ */
+#define SYSCON_EMCSYSCTRL_EMCRD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK)
+#define SYSCON_EMCSYSCTRL_EMCBC_MASK (0x4U)
+#define SYSCON_EMCSYSCTRL_EMCBC_SHIFT (2U)
+/*! EMCBC - External Memory Controller burst control.
+ */
+#define SYSCON_EMCSYSCTRL_EMCBC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK (0x8U)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT (3U)
+/*! EMCFBCLKINSEL - External Memory Controller clock select.
+ */
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK)
+/*! @} */
+
+/*! @name EMCDYCTRL - EMC clock delay control */
+/*! @{ */
+#define SYSCON_EMCDYCTRL_CMD_DELAY_MASK (0x1FU)
+#define SYSCON_EMCDYCTRL_CMD_DELAY_SHIFT (0U)
+/*! CMD_DELAY - Programmable delay value for EMC outputs in command delayed mode.
+ */
+#define SYSCON_EMCDYCTRL_CMD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDYCTRL_CMD_DELAY_MASK)
+#define SYSCON_EMCDYCTRL_FBCLK_DELAY_MASK (0x1F00U)
+#define SYSCON_EMCDYCTRL_FBCLK_DELAY_SHIFT (8U)
+/*! FBCLK_DELAY - Programmable delay value for the feedback clock that controls input data sampling.
+ */
+#define SYSCON_EMCDYCTRL_FBCLK_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDYCTRL_FBCLK_DELAY_MASK)
+/*! @} */
+
+/*! @name EMCCAL - EMC delay chain calibration control */
+/*! @{ */
+#define SYSCON_EMCCAL_CALVALUE_MASK (0xFFU)
+#define SYSCON_EMCCAL_CALVALUE_SHIFT (0U)
+/*! CALVALUE - Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz.
+ */
+#define SYSCON_EMCCAL_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_CALVALUE_SHIFT)) & SYSCON_EMCCAL_CALVALUE_MASK)
+#define SYSCON_EMCCAL_START_MASK (0x4000U)
+#define SYSCON_EMCCAL_START_SHIFT (14U)
+/*! START - Start control bit for the EMC calibration counter.
+ */
+#define SYSCON_EMCCAL_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_START_SHIFT)) & SYSCON_EMCCAL_START_MASK)
+#define SYSCON_EMCCAL_DONE_MASK (0x8000U)
+#define SYSCON_EMCCAL_DONE_SHIFT (15U)
+/*! DONE - Measurement completion flag.
+ */
+#define SYSCON_EMCCAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_DONE_SHIFT)) & SYSCON_EMCCAL_DONE_MASK)
+/*! @} */
+
+/*! @name ETHPHYSEL - Ethernet PHY Selection */
+/*! @{ */
+#define SYSCON_ETHPHYSEL_PHY_SEL_MASK (0x4U)
+#define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT (2U)
+/*! PHY_SEL - PHY interface select.
+ */
+#define SYSCON_ETHPHYSEL_PHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK)
+/*! @} */
+
+/*! @name ETHSBDCTRL - Ethernet SBD flow control */
+/*! @{ */
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK (0x3U)
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT (0U)
+/*! SBD_CTRL - Sideband Flow Control.
+ */
+#define SYSCON_ETHSBDCTRL_SBD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK)
+/*! @} */
+
+/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */
+/*! @{ */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U)
+/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)
+/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U)
+/*! PHASE_ACTIVE - sdio_clk by 2, before feeding into ccl_in, cclk_in_sample, and cclk_in_drv.
+ */
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U)
+/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)
+/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)
+/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)
+/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
+ */
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
+/*! @} */
+
+/*! @name KEYMUXSEL - AES key source selection */
+/*! @{ */
+#define SYSCON_KEYMUXSEL_SEL_MASK (0x3U)
+#define SYSCON_KEYMUXSEL_SEL_SHIFT (0U)
+/*! SEL - PHY interface select.
+ */
+#define SYSCON_KEYMUXSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEYMUXSEL_SEL_SHIFT)) & SYSCON_KEYMUXSEL_SEL_MASK)
+#define SYSCON_KEYMUXSEL_LOCK_MASK (0x80U)
+#define SYSCON_KEYMUXSEL_LOCK_SHIFT (7U)
+/*! LOCK - LOCK stat.
+ */
+#define SYSCON_KEYMUXSEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEYMUXSEL_LOCK_SHIFT)) & SYSCON_KEYMUXSEL_LOCK_MASK)
+/*! @} */
+
+/*! @name FROCTRL - FRO oscillator control */
+/*! @{ */
+#define SYSCON_FROCTRL_SEL_MASK (0x4000U)
+#define SYSCON_FROCTRL_SEL_SHIFT (14U)
+/*! SEL - Select the FRO HF output frequency.
+ */
+#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)
+#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U)
+#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U)
+/*! FREQTRIM - Frequency trim.
+ */
+#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)
+#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U)
+#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U)
+/*! USBCLKADJ - USB clock adjust mode.
+ */
+#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)
+#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U)
+#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U)
+/*! USBMODCHG - USB Mode value Change flag.
+ */
+#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)
+#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U)
+#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U)
+/*! HSPDCLK - High speed clock enable.
+ */
+#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)
+/*! @} */
+
+/*! @name SYSOSCCTRL - System oscillator control */
+/*! @{ */
+#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U)
+#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U)
+/*! FREQRANGE - Determines frequency range for system oscillator.
+ */
+#define SYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)
+/*! @} */
+
+/*! @name WDTOSCCTRL - Watchdog oscillator control */
+/*! @{ */
+#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU)
+#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U)
+/*! DIVSEL - Divider select.
+ */
+#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
+#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U)
+#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U)
+/*! FREQSEL - Frequency select.
+ */
+#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
+/*! @} */
+
+/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */
+/*! @{ */
+#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U)
+#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U)
+/*! EN - RTC 32 kHz clock enable.
+ */
+#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)
+/*! @} */
+
+/*! @name USBPLLCTRL - USB PLL control */
+/*! @{ */
+#define SYSCON_USBPLLCTRL_MSEL_MASK (0xFFU)
+#define SYSCON_USBPLLCTRL_MSEL_SHIFT (0U)
+/*! MSEL - PLL feedback Divider value.
+ */
+#define SYSCON_USBPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK)
+#define SYSCON_USBPLLCTRL_PSEL_MASK (0x300U)
+#define SYSCON_USBPLLCTRL_PSEL_SHIFT (8U)
+/*! PSEL - PLL Divider value.
+ */
+#define SYSCON_USBPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK)
+#define SYSCON_USBPLLCTRL_NSEL_MASK (0xC00U)
+#define SYSCON_USBPLLCTRL_NSEL_SHIFT (10U)
+/*! NSEL - PLL feedback Divider value.
+ */
+#define SYSCON_USBPLLCTRL_NSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK)
+#define SYSCON_USBPLLCTRL_DIRECT_MASK (0x1000U)
+#define SYSCON_USBPLLCTRL_DIRECT_SHIFT (12U)
+/*! DIRECT - Direct CCO clock output control.
+ * 0b0..CCO Clock signal goes through post divider.
+ * 0b1..CCO Clock signal goes directly to output(s)..
+ */
+#define SYSCON_USBPLLCTRL_DIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK)
+#define SYSCON_USBPLLCTRL_BYPASS_MASK (0x2000U)
+#define SYSCON_USBPLLCTRL_BYPASS_SHIFT (13U)
+/*! BYPASS - Input clock bypass control.
+ * 0b0..CCO clock is sent to post dividers..
+ * 0b1..PLL input clock is sent to post dividers..
+ */
+#define SYSCON_USBPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK)
+#define SYSCON_USBPLLCTRL_FBSEL_MASK (0x4000U)
+#define SYSCON_USBPLLCTRL_FBSEL_SHIFT (14U)
+/*! FBSEL - Feedback divider input clock control.
+ */
+#define SYSCON_USBPLLCTRL_FBSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK)
+/*! @} */
+
+/*! @name USBPLLSTAT - USB PLL status */
+/*! @{ */
+#define SYSCON_USBPLLSTAT_LOCK_MASK (0x1U)
+#define SYSCON_USBPLLSTAT_LOCK_SHIFT (0U)
+/*! LOCK - USBPLL lock indicator.
+ */
+#define SYSCON_USBPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK)
+/*! @} */
+
+/*! @name SYSPLLCTRL - System PLL control */
+/*! @{ */
+#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU)
+#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U)
+/*! SELR - Bandwidth select R value.
+ */
+#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)
+#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U)
+#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U)
+/*! SELI - Bandwidth select I value.
+ */
+#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)
+#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U)
+#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U)
+/*! SELP - Bandwidth select P value.
+ */
+#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)
+#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U)
+#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U)
+/*! BYPASS - PLL bypass control.
+ * 0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers.
+ * 0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default).
+ */
+#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U)
+/*! UPLIMOFF - Disable upper frequency limiter.
+ */
+#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U)
+#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U)
+/*! DIRECTI - PLL0 direct input enable.
+ */
+#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U)
+#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U)
+/*! DIRECTO - PLL0 direct output enable.
+ * 0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output.
+ * 0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.
+ */
+#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)
+/*! @} */
+
+/*! @name SYSPLLSTAT - PLL status */
+/*! @{ */
+#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U)
+#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U)
+/*! LOCK - PLL lock indicator.
+ */
+#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
+/*! @} */
+
+/*! @name SYSPLLNDEC - PLL N divider */
+/*! @{ */
+#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU)
+#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U)
+/*! NDEC - Decoded N-divider coefficient value.
+ */
+#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)
+#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U)
+#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U)
+/*! NREQ - NDEC reload request.
+ */
+#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)
+/*! @} */
+
+/*! @name SYSPLLPDEC - PLL P divider */
+/*! @{ */
+#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU)
+#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U)
+/*! PDEC - Decoded P-divider coefficient value.
+ */
+#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)
+#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U)
+#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U)
+/*! PREQ - .
+ */
+#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)
+/*! @} */
+
+/*! @name SYSPLLMDEC - System PLL M divider */
+/*! @{ */
+#define SYSCON_SYSPLLMDEC_MDEC_MASK (0x1FFFFU)
+#define SYSCON_SYSPLLMDEC_MDEC_SHIFT (0U)
+/*! MDEC - Decoded M-divider coefficient value.
+ */
+#define SYSCON_SYSPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK)
+#define SYSCON_SYSPLLMDEC_MREQ_MASK (0x20000U)
+#define SYSCON_SYSPLLMDEC_MREQ_SHIFT (17U)
+/*! MREQ - MDEC reload request.
+ */
+#define SYSCON_SYSPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK)
+/*! @} */
+
+/*! @name AUDPLLCTRL - Audio PLL control */
+/*! @{ */
+#define SYSCON_AUDPLLCTRL_SELR_MASK (0xFU)
+#define SYSCON_AUDPLLCTRL_SELR_SHIFT (0U)
+/*! SELR - Bandwidth select R value.
+ */
+#define SYSCON_AUDPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK)
+#define SYSCON_AUDPLLCTRL_SELI_MASK (0x3F0U)
+#define SYSCON_AUDPLLCTRL_SELI_SHIFT (4U)
+/*! SELI - Bandwidth select I value.
+ */
+#define SYSCON_AUDPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK)
+#define SYSCON_AUDPLLCTRL_SELP_MASK (0x7C00U)
+#define SYSCON_AUDPLLCTRL_SELP_SHIFT (10U)
+/*! SELP - .
+ */
+#define SYSCON_AUDPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK)
+#define SYSCON_AUDPLLCTRL_BYPASS_MASK (0x8000U)
+#define SYSCON_AUDPLLCTRL_BYPASS_SHIFT (15U)
+/*! BYPASS - PLL bypass control.
+ * 0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers.
+ * 0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default).
+ */
+#define SYSCON_AUDPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK (0x20000U)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT (17U)
+/*! UPLIMOFF - Disable upper frequency limiter.
+ */
+#define SYSCON_AUDPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_AUDPLLCTRL_DIRECTI_MASK (0x80000U)
+#define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT (19U)
+/*! DIRECTI - PLL direct input enable.
+ */
+#define SYSCON_AUDPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK)
+#define SYSCON_AUDPLLCTRL_DIRECTO_MASK (0x100000U)
+#define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT (20U)
+/*! DIRECTO - PLL direct output enable
+ * 0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output.
+ * 0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.
+ */
+#define SYSCON_AUDPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK)
+/*! @} */
+
+/*! @name AUDPLLSTAT - Audio PLL status */
+/*! @{ */
+#define SYSCON_AUDPLLSTAT_LOCK_MASK (0x1U)
+#define SYSCON_AUDPLLSTAT_LOCK_SHIFT (0U)
+/*! LOCK - PLL lock indicator.
+ */
+#define SYSCON_AUDPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK)
+/*! @} */
+
+/*! @name AUDPLLNDEC - Audio PLL N divider */
+/*! @{ */
+#define SYSCON_AUDPLLNDEC_NDEC_MASK (0x3FFU)
+#define SYSCON_AUDPLLNDEC_NDEC_SHIFT (0U)
+/*! NDEC - Decoded N-divider coefficient value.
+ */
+#define SYSCON_AUDPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK)
+#define SYSCON_AUDPLLNDEC_NREQ_MASK (0x400U)
+#define SYSCON_AUDPLLNDEC_NREQ_SHIFT (10U)
+/*! NREQ - NDEC reload request.
+ */
+#define SYSCON_AUDPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK)
+/*! @} */
+
+/*! @name AUDPLLPDEC - Audio PLL P divider */
+/*! @{ */
+#define SYSCON_AUDPLLPDEC_PDEC_MASK (0x7FU)
+#define SYSCON_AUDPLLPDEC_PDEC_SHIFT (0U)
+/*! PDEC - Decoded P-divider coefficient value.
+ */
+#define SYSCON_AUDPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK)
+#define SYSCON_AUDPLLPDEC_PREQ_MASK (0x80U)
+#define SYSCON_AUDPLLPDEC_PREQ_SHIFT (7U)
+/*! PREQ - PDEC reload request.
+ */
+#define SYSCON_AUDPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK)
+/*! @} */
+
+/*! @name AUDPLLMDEC - Audio PLL M divider */
+/*! @{ */
+#define SYSCON_AUDPLLMDEC_MDEC_MASK (0x1FFFFU)
+#define SYSCON_AUDPLLMDEC_MDEC_SHIFT (0U)
+/*! MDEC - Decoded M-divider coefficient value.
+ */
+#define SYSCON_AUDPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK)
+#define SYSCON_AUDPLLMDEC_MREQ_MASK (0x20000U)
+#define SYSCON_AUDPLLMDEC_MREQ_SHIFT (17U)
+/*! MREQ - MDEC reload request.
+ */
+#define SYSCON_AUDPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK)
+/*! @} */
+
+/*! @name AUDPLLFRAC - Audio PLL fractional divider control */
+/*! @{ */
+#define SYSCON_AUDPLLFRAC_CTRL_MASK (0x3FFFFFU)
+#define SYSCON_AUDPLLFRAC_CTRL_SHIFT (0U)
+/*! CTRL - PLL fractional divider control word
+ */
+#define SYSCON_AUDPLLFRAC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK)
+#define SYSCON_AUDPLLFRAC_REQ_MASK (0x400000U)
+#define SYSCON_AUDPLLFRAC_REQ_SHIFT (22U)
+/*! REQ - Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator.
+ */
+#define SYSCON_AUDPLLFRAC_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK)
+#define SYSCON_AUDPLLFRAC_SEL_EXT_MASK (0x800000U)
+#define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT (23U)
+/*! SEL_EXT - Select fractional divider.
+ */
+#define SYSCON_AUDPLLFRAC_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK)
+/*! @} */
+
+/*! @name PDSLEEPCFG - Sleep configuration register */
+/*! @{ */
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK (0x1U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT (0U)
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK (0x2U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT (1U)
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK (0x4U)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT (2U)
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK (0x8U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT (3U)
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK (0x10U)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT (4U)
+/*! PDEN_FRO - FRO oscillator.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_TS_MASK (0x40U)
+#define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT (6U)
+/*! PDEN_TS - Temp sensor.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK (0x80U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT (7U)
+/*! PDEN_BOD_RST - Brown-out Detect reset.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK (0x80U)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT (7U)
+/*! PDEN_RNG - Random Number Generator Power.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK (0x100U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT (8U)
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK (0x200U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT (9U)
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
+ * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
+ * and 23).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK (0x400U)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT (10U)
+/*! PDEN_ADC0 - ADC power.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK (0x2000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT (13U)
+/*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK (0x4000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT (14U)
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK (0x8000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT (15U)
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK (0x10000U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT (16U)
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK (0x20000U)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT (17U)
+/*! PDEN_ROM - ROM (also enable/disable bit 27).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK (0x80000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT (19U)
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK (0x100000U)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT (20U)
+/*! PDEN_WDT_OSC - Watchdog oscillator.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK (0x200000U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT (21U)
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK (0x400000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT (22U)
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK (0x800000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT (23U)
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK (0x4000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT (26U)
+/*! PDEN_VD3 - Power control for all PLLs.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK (0x8000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT (27U)
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK (0x10000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT (28U)
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK (0x20000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT (29U)
+/*! PDEN_VD6 - Power control for EEPROM.
+ */
+#define SYSCON_PDSLEEPCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK)
+/*! @} */
+
+/* The count of SYSCON_PDSLEEPCFG */
+#define SYSCON_PDSLEEPCFG_COUNT (2U)
+
+/*! @name PDRUNCFG - Power configuration register */
+/*! @{ */
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK (0x1U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT (0U)
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK (0x2U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT (1U)
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK (0x4U)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT (2U)
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK (0x8U)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT (3U)
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U)
+#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U)
+/*! PDEN_FRO - FRO oscillator.
+ */
+#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U)
+#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U)
+/*! PDEN_TS - Temp sensor.
+ */
+#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U)
+/*! PDEN_BOD_RST - Brown-out Detect reset.
+ */
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFG_PDEN_RNG_MASK (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT (7U)
+/*! PDEN_RNG - Random Number Generator Power.
+ */
+#define SYSCON_PDRUNCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U)
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.
+ */
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK (0x200U)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT (9U)
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
+ * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
+ * and 23).
+ */
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U)
+/*! PDEN_ADC0 - ADC power.
+ */
+#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x2000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (13U)
+/*! PDEN_SRAMX - PPDEN_SRAMX controls only SRAMX address 0x0 to 0x0000FFFF.Bit 29 (PDEN_VD6)
+ * controls SRAMX address 0x00010000 to 0x0002FFFF..
+ */
+#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x4000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (14U)
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK (0x8000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT (15U)
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK (0x10000U)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT (16U)
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U)
+#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U)
+/*! PDEN_ROM - ROM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U)
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
+ */
+#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U)
+/*! PDEN_WDT_OSC - Watchdog oscillator.
+ */
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK (0x200000U)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT (21U)
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
+ */
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U)
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
+ */
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U)
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
+ */
+#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD3_MASK (0x4000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT (26U)
+/*! PDEN_VD3 - Power control for all PLLs.
+ */
+#define SYSCON_PDRUNCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD4_MASK (0x8000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT (27U)
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.
+ */
+#define SYSCON_PDRUNCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD5_MASK (0x10000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT (28U)
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
+ */
+#define SYSCON_PDRUNCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD6_MASK (0x20000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT (29U)
+/*! PDEN_VD6 - Power control for OTP and SRAMX from address 0x00010000 to 0x0002FFFF.
+ */
+#define SYSCON_PDRUNCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK)
+/*! @} */
+
+/* The count of SYSCON_PDRUNCFG */
+#define SYSCON_PDRUNCFG_COUNT (2U)
+
+/*! @name PDRUNCFGSET - Power configuration set register */
+/*! @{ */
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK (0x1U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT (0U)
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK (0x2U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT (1U)
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK (0x4U)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT (2U)
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK (0x8U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT (3U)
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK (0x10U)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT (4U)
+/*! PDEN_FRO - FRO oscillator.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_TS_MASK (0x40U)
+#define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT (6U)
+/*! PDEN_TS - Temp sensor.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK (0x80U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT (7U)
+/*! PDEN_BOD_RST - Brown-out Detect reset.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK (0x80U)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT (7U)
+/*! PDEN_RNG - Random Number Generator Power.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK (0x100U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT (8U)
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK (0x200U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT (9U)
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
+ * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
+ * and 23).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK (0x400U)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT (10U)
+/*! PDEN_ADC0 - ADC power.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK (0x2000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT (13U)
+/*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK (0x4000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT (14U)
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK (0x8000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT (15U)
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK (0x10000U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT (16U)
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK (0x20000U)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT (17U)
+/*! PDEN_ROM - ROM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK (0x80000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT (19U)
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK (0x100000U)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT (20U)
+/*! PDEN_WDT_OSC - Watchdog oscillator.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK (0x200000U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT (21U)
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK (0x400000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT (22U)
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK (0x800000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT (23U)
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK (0x4000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT (26U)
+/*! PDEN_VD3 - Power control for all PLLs.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK (0x8000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT (27U)
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK (0x10000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT (28U)
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK (0x20000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT (29U)
+/*! PDEN_VD6 - Power control for EEPROM.
+ */
+#define SYSCON_PDRUNCFGSET_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK)
+/*! @} */
+
+/* The count of SYSCON_PDRUNCFGSET */
+#define SYSCON_PDRUNCFGSET_COUNT (2U)
+
+/*! @name PDRUNCFGCLR - Power configuration clear register */
+/*! @{ */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK (0x1U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT (0U)
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK (0x2U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT (1U)
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK (0x4U)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT (2U)
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK (0x8U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT (3U)
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK (0x10U)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT (4U)
+/*! PDEN_FRO - FRO oscillator.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK (0x40U)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT (6U)
+/*! PDEN_TS - Temp sensor.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK (0x80U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT (7U)
+/*! PDEN_BOD_RST - Brown-out Detect reset.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK (0x80U)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT (7U)
+/*! PDEN_RNG - Random Number Generator Power.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK (0x100U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT (8U)
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK (0x200U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT (9U)
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
+ * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
+ * and 23).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK (0x400U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT (10U)
+/*! PDEN_ADC0 - ADC power.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK (0x2000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT (13U)
+/*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK (0x4000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT (14U)
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK (0x8000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT (15U)
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK (0x10000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT (16U)
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK (0x20000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT (17U)
+/*! PDEN_ROM - ROM (also enable/disable bit 27).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK (0x80000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT (19U)
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK (0x100000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT (20U)
+/*! PDEN_WDT_OSC - Watchdog oscillator.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK (0x200000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT (21U)
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK (0x400000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT (22U)
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK (0x800000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT (23U)
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK (0x4000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT (26U)
+/*! PDEN_VD3 - Power control for all PLLs.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK (0x8000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT (27U)
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK (0x10000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT (28U)
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK (0x20000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT (29U)
+/*! PDEN_VD6 - Power control for EEPROM.
+ */
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK)
+/*! @} */
+
+/* The count of SYSCON_PDRUNCFGCLR */
+#define SYSCON_PDRUNCFGCLR_COUNT (2U)
+
+/*! @name STARTER - Start logic 0 wake-up enable register */
+/*! @{ */
+#define SYSCON_STARTER_PINT4_MASK (0x1U)
+#define SYSCON_STARTER_PINT4_SHIFT (0U)
+/*! PINT4 - GPIO pin interrupt 4 wake-up.
+ */
+#define SYSCON_STARTER_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK)
+#define SYSCON_STARTER_WDT_BOD_MASK (0x1U)
+#define SYSCON_STARTER_WDT_BOD_SHIFT (0U)
+/*! WDT_BOD - WWDT and BOD interrupt wake-up.
+ */
+#define SYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK)
+#define SYSCON_STARTER_DMA_MASK (0x2U)
+#define SYSCON_STARTER_DMA_SHIFT (1U)
+/*! DMA - DMA wake-up.
+ */
+#define SYSCON_STARTER_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK)
+#define SYSCON_STARTER_PINT5_MASK (0x2U)
+#define SYSCON_STARTER_PINT5_SHIFT (1U)
+/*! PINT5 - GPIO pin interrupt 5 wake-up.
+ */
+#define SYSCON_STARTER_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK)
+#define SYSCON_STARTER_GINT0_MASK (0x4U)
+#define SYSCON_STARTER_GINT0_SHIFT (2U)
+/*! GINT0 - Group interrupt 0 wake-up.
+ */
+#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)
+#define SYSCON_STARTER_PINT6_MASK (0x4U)
+#define SYSCON_STARTER_PINT6_SHIFT (2U)
+/*! PINT6 - GPIO pin interrupt 6 wake-up.
+ */
+#define SYSCON_STARTER_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK)
+#define SYSCON_STARTER_GINT1_MASK (0x8U)
+#define SYSCON_STARTER_GINT1_SHIFT (3U)
+/*! GINT1 - Group interrupt 1 wake-up.
+ */
+#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)
+#define SYSCON_STARTER_PINT7_MASK (0x8U)
+#define SYSCON_STARTER_PINT7_SHIFT (3U)
+/*! PINT7 - GPIO pin interrupt 7 wake-up.
+ */
+#define SYSCON_STARTER_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK)
+#define SYSCON_STARTER_PIN_INT0_MASK (0x10U)
+#define SYSCON_STARTER_PIN_INT0_SHIFT (4U)
+/*! PIN_INT0 - GPIO pin interrupt 0 wake-up.
+ */
+#define SYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK)
+#define SYSCON_STARTER_PIN_INT1_MASK (0x20U)
+#define SYSCON_STARTER_PIN_INT1_SHIFT (5U)
+/*! PIN_INT1 - GPIO pin interrupt 1 wake-up.
+ */
+#define SYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK)
+#define SYSCON_STARTER_PIN_INT2_MASK (0x40U)
+#define SYSCON_STARTER_PIN_INT2_SHIFT (6U)
+/*! PIN_INT2 - GPIO pin interrupt 2 wake-up.
+ */
+#define SYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK)
+#define SYSCON_STARTER_PIN_INT3_MASK (0x80U)
+#define SYSCON_STARTER_PIN_INT3_SHIFT (7U)
+/*! PIN_INT3 - GPIO pin interrupt 3 wake-up.
+ */
+#define SYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK)
+#define SYSCON_STARTER_FLEXCOMM8_MASK (0x100U)
+#define SYSCON_STARTER_FLEXCOMM8_SHIFT (8U)
+/*! FLEXCOMM8 - Flexcomm Interface 8 wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK)
+#define SYSCON_STARTER_UTICK_MASK (0x100U)
+#define SYSCON_STARTER_UTICK_SHIFT (8U)
+/*! UTICK - Micro-tick Timer wake-up.
+ */
+#define SYSCON_STARTER_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK)
+#define SYSCON_STARTER_FLEXCOMM9_MASK (0x200U)
+#define SYSCON_STARTER_FLEXCOMM9_SHIFT (9U)
+/*! FLEXCOMM9 - Flexcomm Interface 9 wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK)
+#define SYSCON_STARTER_FLEXCOMM0_MASK (0x4000U)
+#define SYSCON_STARTER_FLEXCOMM0_SHIFT (14U)
+/*! FLEXCOMM0 - Flexcomm0 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK)
+#define SYSCON_STARTER_FLEXCOMM1_MASK (0x8000U)
+#define SYSCON_STARTER_FLEXCOMM1_SHIFT (15U)
+/*! FLEXCOMM1 - Flexcomm1 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK)
+#define SYSCON_STARTER_USB1_MASK (0x8000U)
+#define SYSCON_STARTER_USB1_SHIFT (15U)
+/*! USB1 - USB 1 wake-up.
+ */
+#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)
+#define SYSCON_STARTER_FLEXCOMM2_MASK (0x10000U)
+#define SYSCON_STARTER_FLEXCOMM2_SHIFT (16U)
+/*! FLEXCOMM2 - Flexcomm2 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK)
+#define SYSCON_STARTER_USB1_ACT_MASK (0x10000U)
+#define SYSCON_STARTER_USB1_ACT_SHIFT (16U)
+/*! USB1_ACT - USB 1 activity wake-up.
+ */
+#define SYSCON_STARTER_USB1_ACT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK)
+#define SYSCON_STARTER_FLEXCOMM3_MASK (0x20000U)
+#define SYSCON_STARTER_FLEXCOMM3_SHIFT (17U)
+/*! FLEXCOMM3 - Flexcomm3 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK)
+#define SYSCON_STARTER_FLEXCOMM4_MASK (0x40000U)
+#define SYSCON_STARTER_FLEXCOMM4_SHIFT (18U)
+/*! FLEXCOMM4 - Flexcomm4 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK)
+#define SYSCON_STARTER_FLEXCOMM5_MASK (0x80000U)
+#define SYSCON_STARTER_FLEXCOMM5_SHIFT (19U)
+/*! FLEXCOMM5 - Flexcomm5 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK)
+#define SYSCON_STARTER_FLEXCOMM6_MASK (0x100000U)
+#define SYSCON_STARTER_FLEXCOMM6_SHIFT (20U)
+/*! FLEXCOMM6 - Flexcomm6 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK)
+#define SYSCON_STARTER_FLEXCOMM7_MASK (0x200000U)
+#define SYSCON_STARTER_FLEXCOMM7_SHIFT (21U)
+/*! FLEXCOMM7 - Flexcomm7 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK)
+#define SYSCON_STARTER_DMIC_MASK (0x2000000U)
+#define SYSCON_STARTER_DMIC_SHIFT (25U)
+/*! DMIC - Digital microphone interrupt wake-up.
+ */
+#define SYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)
+#define SYSCON_STARTER_HWVAD_MASK (0x4000000U)
+#define SYSCON_STARTER_HWVAD_SHIFT (26U)
+/*! HWVAD - Hardware voice activity detect interrupt wake-up.
+ */
+#define SYSCON_STARTER_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK)
+#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U)
+#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U)
+/*! USB0_NEEDCLK - USB activity interrupt wake-up.
+ */
+#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)
+#define SYSCON_STARTER_USB0_MASK (0x10000000U)
+#define SYSCON_STARTER_USB0_SHIFT (28U)
+/*! USB0 - USB function interrupt wake-up.
+ */
+#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)
+#define SYSCON_STARTER_RTC_MASK (0x20000000U)
+#define SYSCON_STARTER_RTC_SHIFT (29U)
+/*! RTC - RTC interrupt alarm and wake-up timer.
+ */
+#define SYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK)
+#define SYSCON_STARTER_FLEXCOMM10_MASK (0x40000000U)
+#define SYSCON_STARTER_FLEXCOMM10_SHIFT (30U)
+/*! FLEXCOMM10 - Flexcomm10 peripheral interrupt wake-up.
+ */
+#define SYSCON_STARTER_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM10_SHIFT)) & SYSCON_STARTER_FLEXCOMM10_MASK)
+/*! @} */
+
+/* The count of SYSCON_STARTER */
+#define SYSCON_STARTER_COUNT (2U)
+
+/*! @name STARTERSET - Set bits in STARTER */
+/*! @{ */
+#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU)
+#define SYSCON_STARTERSET_START_SET_SHIFT (0U)
+/*! START_SET - Writing ones to this register sets the corresponding bit or bits in the STARTER0 register, if they are implemented.
+ */
+#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)
+/*! @} */
+
+/* The count of SYSCON_STARTERSET */
+#define SYSCON_STARTERSET_COUNT (2U)
+
+/*! @name STARTERCLR - Clear bits in STARTER0 */
+/*! @{ */
+#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU)
+#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U)
+/*! START_CLR - Writing ones to this register clears the corresponding bit or bits in the STARTER0 register, if they are implemented.
+ */
+#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)
+/*! @} */
+
+/* The count of SYSCON_STARTERCLR */
+#define SYSCON_STARTERCLR_COUNT (2U)
+
+/*! @name HWWAKE - Configures special cases of hardware wake-up */
+/*! @{ */
+#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U)
+#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U)
+/*! FORCEWAKE - Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1,
+ * clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and
+ * Power-down modes. This is intended to allow a coprocessor to continue operating while the main
+ * CPU(s) are shut down.
+ */
+#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)
+#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U)
+#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U)
+/*! FCWAKE - Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own
+ * TXLVL will cause peripheral clocking to wake up temporarily while the related status is
+ * asserted.
+ */
+#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)
+#define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U)
+#define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U)
+/*! WAKEDMIC - Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the
+ * level specified by TRIGLVL of either channel will cause peripheral clocking to wake up
+ * temporarily while the related status is asserted.
+ */
+#define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)
+#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U)
+#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U)
+/*! WAKEDMA - Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running
+ * until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to
+ * prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but
+ * before DMA has completed its related activity.
+ */
+#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)
+/*! @} */
+
+/*! @name AUTOCGOR - Auto Clock-Gate Override Register */
+/*! @{ */
+#define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U)
+#define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U)
+/*! RAM0X - When 1, automatic clock gating for RAMX and RAM0 are turned off.
+ */
+#define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)
+#define SYSCON_AUTOCGOR_RAM1_MASK (0x4U)
+#define SYSCON_AUTOCGOR_RAM1_SHIFT (2U)
+/*! RAM1 - When 1, automatic clock gating for RAM1 are turned off.
+ */
+#define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)
+#define SYSCON_AUTOCGOR_RAM2_MASK (0x8U)
+#define SYSCON_AUTOCGOR_RAM2_SHIFT (3U)
+/*! RAM2 - When 1, automatic clock gating for RAM1 are turned off.
+ */
+#define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)
+#define SYSCON_AUTOCGOR_RAM3_MASK (0x10U)
+#define SYSCON_AUTOCGOR_RAM3_SHIFT (4U)
+/*! RAM3 - When 1, automatic clock gating for RAM1 are turned off.
+ */
+#define SYSCON_AUTOCGOR_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK)
+/*! @} */
+
+/*! @name JTAGIDCODE - JTAG ID code register */
+/*! @{ */
+#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU)
+#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U)
+/*! JTAGID - JTAG ID code.
+ */
+#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)
+/*! @} */
+
+/*! @name DEVICE_ID0 - Part ID register */
+/*! @{ */
+#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U)
+/*! PARTID - Part ID
+ */
+#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)
+/*! @} */
+
+/*! @name DEVICE_ID1 - Boot ROM and die revision register */
+/*! @{ */
+#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U)
+/*! REVID - Revision.
+ */
+#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)
+/*! @} */
+
+/*! @name BODCTRL - Brown-Out Detect control */
+/*! @{ */
+#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U)
+#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U)
+/*! BODRSTLEV - BOD reset level
+ * 0b00..Level 0: 1.5 V
+ * 0b01..Level 1: 1.85 V
+ * 0b10..Level 2: 2.0 V
+ * 0b11..Level 3: 2.3 V
+ */
+#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)
+#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U)
+#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U)
+/*! BODRSTENA - BOD reset enable
+ * 0b0..Disable reset function.
+ * 0b1..Enable reset function.
+ */
+#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)
+#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U)
+#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U)
+/*! BODINTLEV - BOD interrupt level
+ * 0b00..Level 0: 2.05 V
+ * 0b01..Level 1: 2.45 V
+ * 0b10..Level 2: 2.75 V
+ * 0b11..Level 3: 3.05 V
+ */
+#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)
+#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U)
+#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U)
+/*! BODINTENA - BOD interrupt enable
+ * 0b0..Disable interrupt function.
+ * 0b1..Enable interrupt function.
+ */
+#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)
+#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U)
+#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U)
+/*! BODRSTSTAT - BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit.
+ */
+#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)
+#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U)
+#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U)
+/*! BODINTSTAT - BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit.
+ */
+#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Register_Masks */
+
+
+/* SYSCON - Peripheral instance base addresses */
+/** Peripheral SYSCON base address */
+#define SYSCON_BASE (0x40000000u)
+/** Peripheral SYSCON base pointer */
+#define SYSCON ((SYSCON_Type *)SYSCON_BASE)
+/** Array initializer of SYSCON peripheral base addresses */
+#define SYSCON_BASE_ADDRS { SYSCON_BASE }
+/** Array initializer of SYSCON peripheral base pointers */
+#define SYSCON_BASE_PTRS { SYSCON }
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
+ * @{
+ */
+
+/** USART - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
+ __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
+ __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
+ __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
+ __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */
+ __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */
+ uint8_t RESERVED_1[3536];
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
+ uint8_t RESERVED_3[4];
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
+ uint8_t RESERVED_4[12];
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
+ uint8_t RESERVED_5[12];
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+ uint8_t RESERVED_6[440];
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
+} USART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Register_Masks USART Register Masks
+ * @{
+ */
+
+/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
+/*! @{ */
+#define USART_CFG_ENABLE_MASK (0x1U)
+#define USART_CFG_ENABLE_SHIFT (0U)
+/*! ENABLE - USART Enable.
+ * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0,
+ * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control
+ * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the
+ * transmitter has been reset and is therefore available.
+ * 0b1..Enabled. The USART is enabled for operation.
+ */
+#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
+#define USART_CFG_DATALEN_MASK (0xCU)
+#define USART_CFG_DATALEN_SHIFT (2U)
+/*! DATALEN - Selects the data size for the USART.
+ * 0b00..7 bit Data length.
+ * 0b01..8 bit Data length.
+ * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
+ * 0b11..Reserved.
+ */
+#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
+#define USART_CFG_PARITYSEL_MASK (0x30U)
+#define USART_CFG_PARITYSEL_SHIFT (4U)
+/*! PARITYSEL - Selects what type of parity is used by the USART.
+ * 0b00..No parity.
+ * 0b01..Reserved.
+ * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even,
+ * and the number of 1s in a received character is expected to be even.
+ * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd,
+ * and the number of 1s in a received character is expected to be odd.
+ */
+#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
+#define USART_CFG_STOPLEN_MASK (0x40U)
+#define USART_CFG_STOPLEN_SHIFT (6U)
+/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
+ * 0b0..1 stop bit.
+ * 0b1..2 stop bits. This setting should only be used for asynchronous communication.
+ */
+#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
+#define USART_CFG_MODE32K_MASK (0x80U)
+#define USART_CFG_MODE32K_SHIFT (7U)
+/*! MODE32K - Selects standard or 32 kHz clocking mode.
+ * 0b0..Disabled. USART uses standard clocking.
+ * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.
+ */
+#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
+#define USART_CFG_LINMODE_MASK (0x100U)
+#define USART_CFG_LINMODE_SHIFT (8U)
+/*! LINMODE - LIN break mode enable.
+ * 0b0..Disabled. Break detect and generate is configured for normal operation.
+ * 0b1..Enabled. Break detect and generate is configured for LIN bus operation.
+ */
+#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
+#define USART_CFG_CTSEN_MASK (0x200U)
+#define USART_CFG_CTSEN_SHIFT (9U)
+/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input
+ * pin, or from the USART's own RTS if loopback mode is enabled.
+ * 0b0..No flow control. The transmitter does not receive any automatic flow control signal.
+ * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
+ */
+#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
+#define USART_CFG_SYNCEN_MASK (0x800U)
+#define USART_CFG_SYNCEN_SHIFT (11U)
+/*! SYNCEN - Selects synchronous or asynchronous operation.
+ * 0b0..Asynchronous mode.
+ * 0b1..Synchronous mode.
+ */
+#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
+#define USART_CFG_CLKPOL_MASK (0x1000U)
+#define USART_CFG_CLKPOL_SHIFT (12U)
+/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode.
+ * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK.
+ * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK.
+ */
+#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
+#define USART_CFG_SYNCMST_MASK (0x4000U)
+#define USART_CFG_SYNCMST_SHIFT (14U)
+/*! SYNCMST - Synchronous mode Master select.
+ * 0b0..Slave. When synchronous mode is enabled, the USART is a slave.
+ * 0b1..Master. When synchronous mode is enabled, the USART is a master.
+ */
+#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
+#define USART_CFG_LOOP_MASK (0x8000U)
+#define USART_CFG_LOOP_SHIFT (15U)
+/*! LOOP - Selects data loopback mode.
+ * 0b0..Normal operation.
+ * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial
+ * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD
+ * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device
+ * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
+ */
+#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
+#define USART_CFG_OETA_MASK (0x40000U)
+#define USART_CFG_OETA_SHIFT (18U)
+/*! OETA - Output Enable Turnaround time enable for RS-485 operation.
+ * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
+ * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the
+ * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins
+ * before it is deasserted.
+ */
+#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
+#define USART_CFG_AUTOADDR_MASK (0x80000U)
+#define USART_CFG_AUTOADDR_SHIFT (19U)
+/*! AUTOADDR - Automatic Address matching enable.
+ * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the
+ * possibility of versatile addressing (e.g. respond to more than one address).
+ * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in
+ * the ADDR register as the address to match.
+ */
+#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
+#define USART_CFG_OESEL_MASK (0x100000U)
+#define USART_CFG_OESEL_SHIFT (20U)
+/*! OESEL - Output Enable Select.
+ * 0b0..Standard. The RTS signal is used as the standard flow control function.
+ * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.
+ */
+#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
+#define USART_CFG_OEPOL_MASK (0x200000U)
+#define USART_CFG_OEPOL_SHIFT (21U)
+/*! OEPOL - Output Enable Polarity.
+ * 0b0..Low. If selected by OESEL, the output enable is active low.
+ * 0b1..High. If selected by OESEL, the output enable is active high.
+ */
+#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
+#define USART_CFG_RXPOL_MASK (0x400000U)
+#define USART_CFG_RXPOL_SHIFT (22U)
+/*! RXPOL - Receive data polarity.
+ * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start
+ * bit is 0, data is not inverted, and the stop bit is 1.
+ * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is
+ * 0, start bit is 1, data is inverted, and the stop bit is 0.
+ */
+#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
+#define USART_CFG_TXPOL_MASK (0x800000U)
+#define USART_CFG_TXPOL_SHIFT (23U)
+/*! TXPOL - Transmit data polarity.
+ * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is
+ * 0, data is not inverted, and the stop bit is 1.
+ * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value
+ * is 0, start bit is 1, data is inverted, and the stop bit is 0.
+ */
+#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
+/*! @} */
+
+/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
+/*! @{ */
+#define USART_CTL_TXBRKEN_MASK (0x2U)
+#define USART_CTL_TXBRKEN_SHIFT (1U)
+/*! TXBRKEN - Break Enable.
+ * 0b0..Normal operation.
+ * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit
+ * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the
+ * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled
+ * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
+ */
+#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
+#define USART_CTL_ADDRDET_MASK (0x4U)
+#define USART_CTL_ADDRDET_SHIFT (2U)
+/*! ADDRDET - Enable address detect mode.
+ * 0b0..Disabled. The USART presents all incoming data.
+ * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data
+ * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally,
+ * generating a received data interrupt. Software can then check the data to see if this is an address that
+ * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled
+ * normally.
+ */
+#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
+#define USART_CTL_TXDIS_MASK (0x40U)
+#define USART_CTL_TXDIS_SHIFT (6U)
+/*! TXDIS - Transmit Disable.
+ * 0b0..Not disabled. USART transmitter is not disabled.
+ * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This
+ * feature can be used to facilitate software flow control.
+ */
+#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
+#define USART_CTL_CC_MASK (0x100U)
+#define USART_CTL_CC_SHIFT (8U)
+/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
+ * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to
+ * complete a character that is being received.
+ * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on
+ * Un_RxD independently from transmission on Un_TXD).
+ */
+#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
+#define USART_CTL_CLRCCONRX_MASK (0x200U)
+#define USART_CTL_CLRCCONRX_SHIFT (9U)
+/*! CLRCCONRX - Clear Continuous Clock.
+ * 0b0..No effect. No effect on the CC bit.
+ * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
+ */
+#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
+#define USART_CTL_AUTOBAUD_MASK (0x10000U)
+#define USART_CTL_AUTOBAUD_SHIFT (16U)
+/*! AUTOBAUD - Autobaud enable.
+ * 0b0..Disabled. USART is in normal operating mode.
+ * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The
+ * first start bit of RX is measured and used the update the BRG register to match the received data rate.
+ * AUTOBAUD is cleared once this process is complete, or if there is an AERR.
+ */
+#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
+/*! @} */
+
+/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
+/*! @{ */
+#define USART_STAT_RXIDLE_MASK (0x2U)
+#define USART_STAT_RXIDLE_SHIFT (1U)
+/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of
+ * receiving data. When 1, indicates that the receiver is not currently in the process of receiving
+ * data.
+ */
+#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
+#define USART_STAT_TXIDLE_MASK (0x8U)
+#define USART_STAT_TXIDLE_SHIFT (3U)
+/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of
+ * sending data.When 1, indicate that the transmitter is not currently in the process of sending
+ * data.
+ */
+#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
+#define USART_STAT_CTS_MASK (0x10U)
+#define USART_STAT_CTS_SHIFT (4U)
+/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the
+ * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode
+ * is enabled.
+ */
+#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
+#define USART_STAT_DELTACTS_MASK (0x20U)
+#define USART_STAT_DELTACTS_SHIFT (5U)
+/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
+ */
+#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
+#define USART_STAT_TXDISSTAT_MASK (0x40U)
+#define USART_STAT_TXDISSTAT_SHIFT (6U)
+/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART
+ * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
+ */
+#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
+#define USART_STAT_RXBRK_MASK (0x400U)
+#define USART_STAT_RXBRK_SHIFT (10U)
+/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection
+ * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also
+ * be set when this condition occurs because the stop bit(s) for the character would be missing.
+ * RXBRK is cleared when the Un_RXD pin goes high.
+ */
+#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
+#define USART_STAT_DELTARXBRK_MASK (0x800U)
+#define USART_STAT_DELTARXBRK_SHIFT (11U)
+/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
+ */
+#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
+#define USART_STAT_START_MASK (0x1000U)
+#define USART_STAT_START_SHIFT (12U)
+/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily
+ * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected.
+ * Cleared by software.
+ */
+#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
+#define USART_STAT_FRAMERRINT_MASK (0x2000U)
+#define USART_STAT_FRAMERRINT_SHIFT (13U)
+/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a
+ * missing stop bit at the expected location. This could be an indication of a baud rate or
+ * configuration mismatch with the transmitting source.
+ */
+#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
+#define USART_STAT_PARITYERRINT_MASK (0x4000U)
+#define USART_STAT_PARITYERRINT_SHIFT (14U)
+/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
+ */
+#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
+#define USART_STAT_RXNOISEINT_MASK (0x8000U)
+#define USART_STAT_RXNOISEINT_SHIFT (15U)
+/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to
+ * determine the value of each received data bit, except in synchronous mode. This acts as a
+ * noise filter if one sample disagrees. This flag is set when a received data bit contains one
+ * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or
+ * loss of synchronization during data reception.
+ */
+#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
+#define USART_STAT_ABERR_MASK (0x10000U)
+#define USART_STAT_ABERR_SHIFT (16U)
+/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the
+ * end of the start bit that is being measured, essentially an auto baud time-out.
+ */
+#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+/*! @{ */
+#define USART_INTENSET_TXIDLEEN_MASK (0x8U)
+#define USART_INTENSET_TXIDLEEN_SHIFT (3U)
+/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
+ */
+#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
+#define USART_INTENSET_DELTACTSEN_MASK (0x20U)
+#define USART_INTENSET_DELTACTSEN_SHIFT (5U)
+/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input.
+ */
+#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
+#define USART_INTENSET_TXDISEN_MASK (0x40U)
+#define USART_INTENSET_TXDISEN_SHIFT (6U)
+/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by
+ * the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
+ */
+#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
+#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)
+#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)
+/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection
+ * of a received break condition (break condition asserted or deasserted).
+ */
+#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
+#define USART_INTENSET_STARTEN_MASK (0x1000U)
+#define USART_INTENSET_STARTEN_SHIFT (12U)
+/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected.
+ */
+#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
+#define USART_INTENSET_FRAMERREN_MASK (0x2000U)
+#define USART_INTENSET_FRAMERREN_SHIFT (13U)
+/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected.
+ */
+#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
+#define USART_INTENSET_PARITYERREN_MASK (0x4000U)
+#define USART_INTENSET_PARITYERREN_SHIFT (14U)
+/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected.
+ */
+#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
+#define USART_INTENSET_RXNOISEEN_MASK (0x8000U)
+#define USART_INTENSET_RXNOISEEN_SHIFT (15U)
+/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354.
+ */
+#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
+#define USART_INTENSET_ABERREN_MASK (0x10000U)
+#define USART_INTENSET_ABERREN_SHIFT (16U)
+/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs.
+ */
+#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
+/*! @{ */
+#define USART_INTENCLR_TXIDLECLR_MASK (0x8U)
+#define USART_INTENCLR_TXIDLECLR_SHIFT (3U)
+/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
+#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)
+#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)
+/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
+#define USART_INTENCLR_TXDISCLR_MASK (0x40U)
+#define USART_INTENCLR_TXDISCLR_SHIFT (6U)
+/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
+#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)
+/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
+#define USART_INTENCLR_STARTCLR_MASK (0x1000U)
+#define USART_INTENCLR_STARTCLR_SHIFT (12U)
+/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
+#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)
+#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)
+/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
+#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)
+#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)
+/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
+#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)
+#define USART_INTENCLR_RXNOISECLR_SHIFT (15U)
+/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
+#define USART_INTENCLR_ABERRCLR_MASK (0x10000U)
+#define USART_INTENCLR_ABERRCLR_SHIFT (16U)
+/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
+ */
+#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
+/*! @} */
+
+/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
+/*! @{ */
+#define USART_BRG_BRGVAL_MASK (0xFFFFU)
+#define USART_BRG_BRGVAL_SHIFT (0U)
+/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on
+ * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is
+ * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART
+ * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
+ */
+#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
+/*! @{ */
+#define USART_INTSTAT_TXIDLE_MASK (0x8U)
+#define USART_INTSTAT_TXIDLE_SHIFT (3U)
+/*! TXIDLE - Transmitter Idle status.
+ */
+#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
+#define USART_INTSTAT_DELTACTS_MASK (0x20U)
+#define USART_INTSTAT_DELTACTS_SHIFT (5U)
+/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected.
+ */
+#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
+#define USART_INTSTAT_TXDISINT_MASK (0x40U)
+#define USART_INTSTAT_TXDISINT_SHIFT (6U)
+/*! TXDISINT - Transmitter Disabled Interrupt flag.
+ */
+#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
+#define USART_INTSTAT_DELTARXBRK_MASK (0x800U)
+#define USART_INTSTAT_DELTARXBRK_SHIFT (11U)
+/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs.
+ */
+#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
+#define USART_INTSTAT_START_MASK (0x1000U)
+#define USART_INTSTAT_START_SHIFT (12U)
+/*! START - This bit is set when a start is detected on the receiver input.
+ */
+#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
+#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)
+#define USART_INTSTAT_FRAMERRINT_SHIFT (13U)
+/*! FRAMERRINT - Framing Error interrupt flag.
+ */
+#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
+#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)
+#define USART_INTSTAT_PARITYERRINT_SHIFT (14U)
+/*! PARITYERRINT - Parity Error interrupt flag.
+ */
+#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
+#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)
+#define USART_INTSTAT_RXNOISEINT_SHIFT (15U)
+/*! RXNOISEINT - Received Noise interrupt flag.
+ */
+#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
+#define USART_INTSTAT_ABERRINT_MASK (0x10000U)
+#define USART_INTSTAT_ABERRINT_SHIFT (16U)
+/*! ABERRINT - Auto baud Error Interrupt flag.
+ */
+#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
+/*! @} */
+
+/*! @name OSR - Oversample selection register for asynchronous communication. */
+/*! @{ */
+#define USART_OSR_OSRVAL_MASK (0xFU)
+#define USART_OSR_OSRVAL_SHIFT (0U)
+/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to
+ * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive
+ * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.
+ */
+#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
+/*! @} */
+
+/*! @name ADDR - Address register for automatic address matching. */
+/*! @{ */
+#define USART_ADDR_ADDRESS_MASK (0xFFU)
+#define USART_ADDR_ADDRESS_SHIFT (0U)
+/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is
+ * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
+ */
+#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+/*! @{ */
+#define USART_FIFOCFG_ENABLETX_MASK (0x1U)
+#define USART_FIFOCFG_ENABLETX_SHIFT (0U)
+/*! ENABLETX - Enable the transmit FIFO.
+ * 0b0..The transmit FIFO is not enabled.
+ * 0b1..The transmit FIFO is enabled.
+ */
+#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
+#define USART_FIFOCFG_ENABLERX_MASK (0x2U)
+#define USART_FIFOCFG_ENABLERX_SHIFT (1U)
+/*! ENABLERX - Enable the receive FIFO.
+ * 0b0..The receive FIFO is not enabled.
+ * 0b1..The receive FIFO is enabled.
+ */
+#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
+#define USART_FIFOCFG_SIZE_MASK (0x30U)
+#define USART_FIFOCFG_SIZE_SHIFT (4U)
+/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
+ * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
+ */
+#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
+#define USART_FIFOCFG_DMATX_MASK (0x1000U)
+#define USART_FIFOCFG_DMATX_SHIFT (12U)
+/*! DMATX - DMA configuration for transmit.
+ * 0b0..DMA is not used for the transmit function.
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
+#define USART_FIFOCFG_DMARX_MASK (0x2000U)
+#define USART_FIFOCFG_DMARX_SHIFT (13U)
+/*! DMARX - DMA configuration for receive.
+ * 0b0..DMA is not used for the receive function.
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
+#define USART_FIFOCFG_WAKETX_MASK (0x4000U)
+#define USART_FIFOCFG_WAKETX_SHIFT (14U)
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ * Wake-up control register.
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
+ * FIFOTRIG, even when the TXLVL interrupt is not enabled.
+ */
+#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
+#define USART_FIFOCFG_WAKERX_MASK (0x8000U)
+#define USART_FIFOCFG_WAKERX_SHIFT (15U)
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
+ * Wake-up control register.
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
+ * FIFOTRIG, even when the RXLVL interrupt is not enabled.
+ */
+#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
+#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define USART_FIFOCFG_EMPTYTX_SHIFT (16U)
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
+ */
+#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
+#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define USART_FIFOCFG_EMPTYRX_SHIFT (17U)
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
+ */
+#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO status register. */
+/*! @{ */
+#define USART_FIFOSTAT_TXERR_MASK (0x1U)
+#define USART_FIFOSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
+ * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
+ * needed. Cleared by writing a 1 to this bit.
+ */
+#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
+#define USART_FIFOSTAT_RXERR_MASK (0x2U)
+#define USART_FIFOSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
+ * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
+ */
+#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
+#define USART_FIFOSTAT_PERINT_MASK (0x8U)
+#define USART_FIFOSTAT_PERINT_SHIFT (3U)
+/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
+ * an interrupt. The details can be found by reading the peripheral's STAT register.
+ */
+#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
+#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
+ */
+#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
+#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
+ * written. When 0, the transmit FIFO is full and another write would cause it to overflow.
+ */
+#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
+ */
+#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
+#define USART_FIFOSTAT_RXFULL_MASK (0x80U)
+#define USART_FIFOSTAT_RXFULL_SHIFT (7U)
+/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
+ * prevent the peripheral from causing an overflow.
+ */
+#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
+#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define USART_FIFOSTAT_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
+ * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
+ * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
+ * 0.
+ */
+#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
+#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define USART_FIFOSTAT_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
+ * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
+ * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
+ * 1.
+ */
+#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+/*! @{ */
+#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
+ * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
+ */
+#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
+#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
+ * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
+ */
+#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
+#define USART_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define USART_FIFOTRIG_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
+ * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
+ * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
+ * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
+ * FIFO level decreases to 15 entries (is no longer full).
+ */
+#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
+#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define USART_FIFOTRIG_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
+ * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
+ * can wake up the device just enough to perform DMA, then return to the reduced power mode. See
+ * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
+ * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
+ * FIFO has received 16 entries (has become full).
+ */
+#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+/*! @{ */
+#define USART_FIFOINTENSET_TXERR_MASK (0x1U)
+#define USART_FIFOINTENSET_TXERR_SHIFT (0U)
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a transmit error.
+ * 0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
+#define USART_FIFOINTENSET_RXERR_MASK (0x2U)
+#define USART_FIFOINTENSET_RXERR_SHIFT (1U)
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a receive error.
+ * 0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
+#define USART_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define USART_FIFOINTENSET_TXLVL_SHIFT (2U)
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
+ * specified by the TXLVL field in the FIFOTRIG register.
+ * 0b0..No interrupt will be generated based on the TX FIFO level.
+ * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
+ * to the level specified by TXLVL in the FIFOTRIG register.
+ */
+#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
+#define USART_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define USART_FIFOINTENSET_RXLVL_SHIFT (3U)
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
+ * specified by the TXLVL field in the FIFOTRIG register.
+ * 0b0..No interrupt will be generated based on the RX FIFO level.
+ * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
+ * increases to the level specified by RXLVL in the FIFOTRIG register.
+ */
+#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+/*! @{ */
+#define USART_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define USART_FIFOINTENCLR_TXERR_SHIFT (0U)
+/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
+#define USART_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define USART_FIFOINTENCLR_RXERR_SHIFT (1U)
+/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
+#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)
+/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
+#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)
+/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
+ */
+#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+/*! @{ */
+#define USART_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define USART_FIFOINTSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO error.
+ */
+#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
+#define USART_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define USART_FIFOINTSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO error.
+ */
+#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
+#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit FIFO level interrupt.
+ */
+#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
+#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive FIFO level interrupt.
+ */
+#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
+#define USART_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define USART_FIFOINTSTAT_PERINT_SHIFT (4U)
+/*! PERINT - Peripheral interrupt.
+ */
+#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO write data. */
+/*! @{ */
+#define USART_FIFOWR_TXDATA_MASK (0x1FFU)
+#define USART_FIFOWR_TXDATA_SHIFT (0U)
+/*! TXDATA - Transmit data to the FIFO.
+ */
+#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO read data. */
+/*! @{ */
+#define USART_FIFORD_RXDATA_MASK (0x1FFU)
+#define USART_FIFORD_RXDATA_SHIFT (0U)
+/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
+ */
+#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
+#define USART_FIFORD_FRAMERR_MASK (0x2000U)
+#define USART_FIFORD_FRAMERR_SHIFT (13U)
+/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along
+ * with from the FIFO, and indicates that the character was received with a missing stop bit at
+ * the expected location. This could be an indication of a baud rate or configuration mismatch
+ * with the transmitting source.
+ */
+#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
+#define USART_FIFORD_PARITYERR_MASK (0x4000U)
+#define USART_FIFORD_PARITYERR_SHIFT (14U)
+/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along
+ * with from the FIFO. This bit will be set when a parity error is detected in a received
+ * character.
+ */
+#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
+#define USART_FIFORD_RXNOISE_MASK (0x8000U)
+#define USART_FIFORD_RXNOISE_SHIFT (15U)
+/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.
+ */
+#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+/*! @{ */
+#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)
+#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)
+/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
+ */
+#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
+#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)
+/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along
+ * with from the FIFO, and indicates that the character was received with a missing stop bit at
+ * the expected location. This could be an indication of a baud rate or configuration mismatch
+ * with the transmitting source.
+ */
+#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
+#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)
+/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along
+ * with from the FIFO. This bit will be set when a parity error is detected in a received
+ * character.
+ */
+#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
+#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)
+/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.
+ */
+#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral identification register. */
+/*! @{ */
+#define USART_ID_APERTURE_MASK (0xFFU)
+#define USART_ID_APERTURE_SHIFT (0U)
+/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
+ */
+#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
+#define USART_ID_MINOR_REV_MASK (0xF00U)
+#define USART_ID_MINOR_REV_SHIFT (8U)
+/*! MINOR_REV - Minor revision of module implementation.
+ */
+#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
+#define USART_ID_MAJOR_REV_MASK (0xF000U)
+#define USART_ID_MAJOR_REV_SHIFT (12U)
+/*! MAJOR_REV - Major revision of module implementation.
+ */
+#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
+#define USART_ID_ID_MASK (0xFFFF0000U)
+#define USART_ID_ID_SHIFT (16U)
+/*! ID - Module identifier for the selected function.
+ */
+#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USART_Register_Masks */
+
+
+/* USART - Peripheral instance base addresses */
+/** Peripheral USART0 base address */
+#define USART0_BASE (0x40086000u)
+/** Peripheral USART0 base pointer */
+#define USART0 ((USART_Type *)USART0_BASE)
+/** Peripheral USART1 base address */
+#define USART1_BASE (0x40087000u)
+/** Peripheral USART1 base pointer */
+#define USART1 ((USART_Type *)USART1_BASE)
+/** Peripheral USART2 base address */
+#define USART2_BASE (0x40088000u)
+/** Peripheral USART2 base pointer */
+#define USART2 ((USART_Type *)USART2_BASE)
+/** Peripheral USART3 base address */
+#define USART3_BASE (0x40089000u)
+/** Peripheral USART3 base pointer */
+#define USART3 ((USART_Type *)USART3_BASE)
+/** Peripheral USART4 base address */
+#define USART4_BASE (0x4008A000u)
+/** Peripheral USART4 base pointer */
+#define USART4 ((USART_Type *)USART4_BASE)
+/** Peripheral USART5 base address */
+#define USART5_BASE (0x40096000u)
+/** Peripheral USART5 base pointer */
+#define USART5 ((USART_Type *)USART5_BASE)
+/** Peripheral USART6 base address */
+#define USART6_BASE (0x40097000u)
+/** Peripheral USART6 base pointer */
+#define USART6 ((USART_Type *)USART6_BASE)
+/** Peripheral USART7 base address */
+#define USART7_BASE (0x40098000u)
+/** Peripheral USART7 base pointer */
+#define USART7 ((USART_Type *)USART7_BASE)
+/** Peripheral USART8 base address */
+#define USART8_BASE (0x40099000u)
+/** Peripheral USART8 base pointer */
+#define USART8 ((USART_Type *)USART8_BASE)
+/** Peripheral USART9 base address */
+#define USART9_BASE (0x4009A000u)
+/** Peripheral USART9 base pointer */
+#define USART9 ((USART_Type *)USART9_BASE)
+/** Array initializer of USART peripheral base addresses */
+#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE }
+/** Array initializer of USART peripheral base pointers */
+#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 }
+/** Interrupt vectors for the USART peripheral type */
+#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
+ __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
+ __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
+ __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
+ __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+ __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
+ __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
+ __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+/*! @{ */
+#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
+#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
+/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit
+ * is set, the device will respond on packets for function address DEV_ADDR. When receiving a
+ * SetAddress Control Request from the USB host, software must program the new address before
+ * completing the status phase of the SetAddress Control Request.
+ */
+#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U)
+#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U)
+/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR.
+ */
+#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
+#define USB_DEVCMDSTAT_SETUP_MASK (0x100U)
+#define USB_DEVCMDSTAT_SETUP_SHIFT (8U)
+/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this
+ * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW
+ * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the
+ * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW.
+ */
+#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
+/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:
+ * 0b0..USB_NEEDCLK has normal function.
+ * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend.
+ */
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
+#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
+/*! LPM_SUP - LPM Supported:
+ * 0b0..LPM not supported.
+ * 0b1..LPM supported.
+ */
+#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
+#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
+/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP
+ * 0b0..Only acknowledged packets generate an interrupt
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
+#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
+/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP
+ * 0b0..Only acknowledged packets generate an interrupt
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
+#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
+/*! INTONNAK_CO - Interrupt on NAK for control OUT EP
+ * 0b0..Only acknowledged packets generate an interrupt
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
+#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
+/*! INTONNAK_CI - Interrupt on NAK for control IN EP
+ * 0b0..Only acknowledged packets generate an interrupt
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USB_DEVCMDSTAT_DCON_MASK (0x10000U)
+#define USB_DEVCMDSTAT_DCON_SHIFT (16U)
+/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device
+ * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and
+ * the VBUSDEBOUNCED bit is one.
+ */
+#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
+#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U)
+#define USB_DEVCMDSTAT_DSUS_SHIFT (17U)
+/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set
+ * to 1 when the device hasn't seen any activity on its upstream port for more than 3
+ * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and
+ * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen
+ * when the device is connected (Connect bit = 1). When the device is not connected or not
+ * suspended, a writing a 0 has no effect. Writing a 1 never has an effect.
+ */
+#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
+#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
+#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
+/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is
+ * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the
+ * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend
+ * bit = 1) and the software writes a zero to this bit, the device will generate a remote
+ * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this
+ * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the
+ * LPM_SUPP bit is equal to one.
+ */
+#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
+#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
+#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
+/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake
+ * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the
+ * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset
+ * is received. Software can use this bit to check if the remote wake-up feature is enabled by the
+ * host for the LPM transaction.
+ */
+#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
+#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
+#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U)
+/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up
+ * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it.
+ */
+#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
+#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
+#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U)
+/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit
+ * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The
+ * device is disconnected - The device receives resume signaling on its upstream port. The bit is
+ * reset by writing a one to it.
+ */
+#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
+#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
+#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U)
+/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On
+ * a bus reset the device will automatically go to the default state (unconfigured and responding
+ * to address 0). The bit is reset by writing a one to it.
+ */
+#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)
+/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when
+ * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and
+ * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect.
+ */
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
+/*! @} */
+
+/*! @name INFO - USB Info register */
+/*! @{ */
+#define USB_INFO_FRAME_NR_MASK (0x7FFU)
+#define USB_INFO_FRAME_NR_SHIFT (0U)
+/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF.
+ * In case no SOF was received by the device at the beginning of a frame, the frame number
+ * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC
+ * error, the frame number returned will be the corrupted frame number as received by the device.
+ */
+#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
+#define USB_INFO_ERR_CODE_MASK (0x7800U)
+#define USB_INFO_ERR_CODE_SHIFT (11U)
+/*! ERR_CODE - The error code which last occurred:
+ * 0b0000..No error
+ * 0b0001..PID encoding error
+ * 0b0010..PID unknown
+ * 0b0011..Packet unexpected
+ * 0b0100..Token CRC error
+ * 0b0101..Data CRC error
+ * 0b0110..Time out
+ * 0b0111..Babble
+ * 0b1000..Truncated EOP
+ * 0b1001..Sent/Received NAK
+ * 0b1010..Sent Stall
+ * 0b1011..Overrun
+ * 0b1100..Sent empty packet
+ * 0b1101..Bitstuff error
+ * 0b1110..Sync error
+ * 0b1111..Wrong data toggle
+ */
+#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
+#define USB_INFO_MINREV_MASK (0xFF0000U)
+#define USB_INFO_MINREV_SHIFT (16U)
+/*! MINREV - Minor Revision.
+ */
+#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
+#define USB_INFO_MAJREV_MASK (0xFF000000U)
+#define USB_INFO_MAJREV_SHIFT (24U)
+/*! MAJREV - Major Revision.
+ */
+#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
+/*! @} */
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+/*! @{ */
+#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)
+#define USB_EPLISTSTART_EP_LIST_SHIFT (8U)
+/*! EP_LIST - Start address of the USB EP Command/Status List.
+ */
+#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
+/*! @} */
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+/*! @{ */
+#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)
+#define USB_DATABUFSTART_DA_BUF_SHIFT (22U)
+/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located.
+ */
+#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
+/*! @} */
+
+/*! @name LPM - USB Link Power Management register */
+/*! @{ */
+#define USB_LPM_HIRD_HW_MASK (0xFU)
+#define USB_LPM_HIRD_HW_SHIFT (0U)
+/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token
+ */
+#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
+#define USB_LPM_HIRD_SW_MASK (0xF0U)
+#define USB_LPM_HIRD_SW_SHIFT (4U)
+/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB
+ * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume.
+ */
+#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
+#define USB_LPM_DATA_PENDING_MASK (0x100U)
+#define USB_LPM_DATA_PENDING_SHIFT (8U)
+/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will
+ * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and
+ * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has
+ * still data pending and LPM is supported, it must set this bit to 1.
+ */
+#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
+/*! @} */
+
+/*! @name EPSKIP - USB Endpoint skip */
+/*! @{ */
+#define USB_EPSKIP_SKIP_MASK (0x3FFU)
+#define USB_EPSKIP_SKIP_SHIFT (0U)
+/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must
+ * deactivate the buffer assigned to this endpoint and return control back to software. When HW has
+ * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An
+ * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering,
+ * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit.
+ */
+#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
+/*! @} */
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+/*! @{ */
+#define USB_EPINUSE_BUF_MASK (0x3FCU)
+#define USB_EPINUSE_BUF_SHIFT (2U)
+/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer
+ * 0. 1: HW is accessing buffer 1.
+ */
+#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
+/*! @} */
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+/*! @{ */
+#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU)
+#define USB_EPBUFCFG_BUF_SB_SHIFT (2U)
+/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1:
+ * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding
+ * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle
+ * the EPINUSE bit when it clears the Active bit for the buffer.
+ */
+#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
+/*! @} */
+
+/*! @name INTSTAT - USB interrupt status register */
+/*! @{ */
+#define USB_INTSTAT_EP0OUT_MASK (0x1U)
+#define USB_INTSTAT_EP0OUT_SHIFT (0U)
+/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set
+ * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is
+ * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a
+ * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a
+ * one to it.
+ */
+#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
+#define USB_INTSTAT_EP0IN_MASK (0x2U)
+#define USB_INTSTAT_EP0IN_SHIFT (1U)
+/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if
+ * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this
+ * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can
+ * clear this bit by writing a one to it.
+ */
+#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
+#define USB_INTSTAT_EP1OUT_MASK (0x4U)
+#define USB_INTSTAT_EP1OUT_SHIFT (2U)
+/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
+ * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
+ * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by
+ * writing a one to it.
+ */
+#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
+#define USB_INTSTAT_EP1IN_MASK (0x8U)
+#define USB_INTSTAT_EP1IN_SHIFT (3U)
+/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
+ * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
+ * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing
+ * a one to it.
+ */
+#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
+#define USB_INTSTAT_EP2OUT_MASK (0x10U)
+#define USB_INTSTAT_EP2OUT_SHIFT (4U)
+/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
+ * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
+ * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by
+ * writing a one to it.
+ */
+#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
+#define USB_INTSTAT_EP2IN_MASK (0x20U)
+#define USB_INTSTAT_EP2IN_SHIFT (5U)
+/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
+ * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
+ * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing
+ * a one to it.
+ */
+#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
+#define USB_INTSTAT_EP3OUT_MASK (0x40U)
+#define USB_INTSTAT_EP3OUT_SHIFT (6U)
+/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
+ * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
+ * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by
+ * writing a one to it.
+ */
+#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
+#define USB_INTSTAT_EP3IN_MASK (0x80U)
+#define USB_INTSTAT_EP3IN_SHIFT (7U)
+/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
+ * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
+ * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing
+ * a one to it.
+ */
+#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
+#define USB_INTSTAT_EP4OUT_MASK (0x100U)
+#define USB_INTSTAT_EP4OUT_SHIFT (8U)
+/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
+ * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
+ * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by
+ * writing a one to it.
+ */
+#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
+#define USB_INTSTAT_EP4IN_MASK (0x200U)
+#define USB_INTSTAT_EP4IN_SHIFT (9U)
+/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
+ * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
+ * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing
+ * a one to it.
+ */
+#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
+#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U)
+#define USB_INTSTAT_FRAME_INT_SHIFT (30U)
+/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit
+ * and the DCON bit are set. This bit can be used by software when handling isochronous
+ * endpoints. Software can clear this bit by writing a one to it.
+ */
+#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
+#define USB_INTSTAT_DEV_INT_MASK (0x80000000U)
+#define USB_INTSTAT_DEV_INT_SHIFT (31U)
+/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device
+ * Status Change register are set. Software can clear this bit by writing a one to it.
+ */
+#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
+/*! @} */
+
+/*! @name INTEN - USB interrupt enable register */
+/*! @{ */
+#define USB_INTEN_EP_INT_EN_MASK (0x3FFU)
+#define USB_INTEN_EP_INT_EN_SHIFT (0U)
+/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing
+ * bit.
+ */
+#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
+#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U)
+#define USB_INTEN_FRAME_INT_EN_SHIFT (30U)
+/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt
+ * routing bit.
+ */
+#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
+#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U)
+#define USB_INTEN_DEV_INT_EN_SHIFT (31U)
+/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing
+ * bit.
+ */
+#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
+/*! @} */
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+/*! @{ */
+#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU)
+#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U)
+/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
+ * status bit is set. When this register is read, the same value as the USB interrupt status register
+ * is returned.
+ */
+#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
+#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
+#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
+/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
+ * status bit is set. When this register is read, the same value as the USB interrupt status
+ * register is returned.
+ */
+#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
+#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
+/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
+ * status bit is set. When this register is read, the same value as the USB interrupt status
+ * register is returned.
+ */
+#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
+/*! @} */
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+/*! @{ */
+#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU)
+#define USB_EPTOGGLE_TOGGLE_SHIFT (0U)
+/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
+ */
+#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40084000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBFSH Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBFSH - Register Layout Typedef */
+typedef struct {
+ __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */
+ __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */
+ __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */
+ __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */
+ __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */
+ __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */
+ __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */
+ __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */
+ __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */
+ __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */
+ __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */
+ __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */
+ __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */
+ __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */
+ __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
+ __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */
+ __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */
+ __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
+ __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */
+ __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */
+ __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */
+ __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
+} USBFSH_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBFSH Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBFSH_Register_Masks USBFSH Register Masks
+ * @{
+ */
+
+/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */
+/*! @{ */
+#define USBFSH_HCREVISION_REV_MASK (0xFFU)
+#define USBFSH_HCREVISION_REV_SHIFT (0U)
+/*! REV - Revision.
+ */
+#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
+/*! @} */
+
+/*! @name HCCONTROL - Defines the operating modes of the HC */
+/*! @{ */
+#define USBFSH_HCCONTROL_CBSR_MASK (0x3U)
+#define USBFSH_HCCONTROL_CBSR_SHIFT (0U)
+/*! CBSR - ControlBulkServiceRatio.
+ */
+#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
+#define USBFSH_HCCONTROL_PLE_MASK (0x4U)
+#define USBFSH_HCCONTROL_PLE_SHIFT (2U)
+/*! PLE - PeriodicListEnable.
+ */
+#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
+#define USBFSH_HCCONTROL_IE_MASK (0x8U)
+#define USBFSH_HCCONTROL_IE_SHIFT (3U)
+/*! IE - IsochronousEnable.
+ */
+#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
+#define USBFSH_HCCONTROL_CLE_MASK (0x10U)
+#define USBFSH_HCCONTROL_CLE_SHIFT (4U)
+/*! CLE - ControlListEnable.
+ */
+#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
+#define USBFSH_HCCONTROL_BLE_MASK (0x20U)
+#define USBFSH_HCCONTROL_BLE_SHIFT (5U)
+/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame.
+ */
+#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
+#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U)
+#define USBFSH_HCCONTROL_HCFS_SHIFT (6U)
+/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL
+ * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin
+ * 1 ms later.
+ */
+#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
+#define USBFSH_HCCONTROL_IR_MASK (0x100U)
+#define USBFSH_HCCONTROL_IR_SHIFT (8U)
+/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus.
+ */
+#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
+#define USBFSH_HCCONTROL_RWC_MASK (0x200U)
+#define USBFSH_HCCONTROL_RWC_SHIFT (9U)
+/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling.
+ */
+#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
+#define USBFSH_HCCONTROL_RWE_MASK (0x400U)
+#define USBFSH_HCCONTROL_RWE_SHIFT (10U)
+/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature
+ * upon the detection of upstream resume signaling.
+ */
+#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
+/*! @} */
+
+/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */
+/*! @{ */
+#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U)
+#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U)
+/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC.
+ */
+#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
+#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U)
+#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U)
+/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list.
+ */
+#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
+#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U)
+#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U)
+/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list.
+ */
+#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
+#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U)
+#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U)
+/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC.
+ */
+#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
+#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U)
+#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U)
+/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error.
+ */
+#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
+/*! @} */
+
+/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */
+/*! @{ */
+#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U)
+#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U)
+/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and
+ * after the update of HccaFrameNumber.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U)
+/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U)
+#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U)
+/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U)
+#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U)
+/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U)
+#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U)
+/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U)
+/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value,
+ * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U)
+/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any
+ * of HcRhPortStatus[NumberofDownstreamPort] has changed.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U)
+#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U)
+/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus.
+ */
+#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
+/*! @} */
+
+/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */
+/*! @{ */
+#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U)
+#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U)
+/*! SO - Scheduling Overrun interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
+#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U)
+#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U)
+/*! WDH - HcDoneHead Writeback interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
+#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U)
+#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U)
+/*! SF - Start of Frame interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
+#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U)
+#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U)
+/*! RD - Resume Detect interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
+#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U)
+#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U)
+/*! UE - Unrecoverable Error interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
+#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U)
+#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U)
+/*! FNO - Frame Number Overflow interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U)
+/*! RHSC - Root Hub Status Change interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
+#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U)
+#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U)
+/*! OC - Ownership Change interrupt.
+ */
+#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
+#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U)
+#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U)
+/*! MIE - Master Interrupt Enable.
+ */
+#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
+/*! @} */
+
+/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */
+/*! @{ */
+#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U)
+#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U)
+/*! SO - Scheduling Overrun interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U)
+/*! WDH - HcDoneHead Writeback interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U)
+#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U)
+/*! SF - Start of Frame interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U)
+#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U)
+/*! RD - Resume Detect interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U)
+#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U)
+/*! UE - Unrecoverable Error interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U)
+/*! FNO - Frame Number Overflow interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U)
+/*! RHSC - Root Hub Status Change interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U)
+#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U)
+/*! OC - Ownership Change interrupt.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U)
+/*! MIE - A 0 written to this field is ignored by HC.
+ */
+#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
+/*! @} */
+
+/*! @name HCHCCA - Contains the physical address of the host controller communication area */
+/*! @{ */
+#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U)
+#define USBFSH_HCHCCA_HCCA_SHIFT (8U)
+/*! HCCA - Base address of the Host Controller Communication Area.
+ */
+#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
+/*! @} */
+
+/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */
+/*! @{ */
+#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U)
+/*! PCED - The content of this register is updated by HC after a periodic ED is processed.
+ */
+#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
+/*! @} */
+
+/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */
+/*! @{ */
+#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U)
+/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer.
+ */
+#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
+/*! @} */
+
+/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */
+/*! @{ */
+#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U)
+/*! CCED - ControlCurrentED.
+ */
+#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
+/*! @} */
+
+/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */
+/*! @{ */
+#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U)
+/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer.
+ */
+#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
+/*! @} */
+
+/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */
+/*! @{ */
+#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U)
+/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one.
+ */
+#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
+/*! @} */
+
+/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */
+/*! @{ */
+#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U)
+#define USBFSH_HCDONEHEAD_DH_SHIFT (4U)
+/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD.
+ */
+#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
+/*! @} */
+
+/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */
+/*! @{ */
+#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU)
+#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U)
+/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times.
+ */
+#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
+#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U)
+#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U)
+/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data
+ * Packet Counter at the beginning of each frame.
+ */
+#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
+#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U)
+#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U)
+/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval.
+ */
+#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
+/*! @} */
+
+/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */
+/*! @{ */
+#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU)
+#define USBFSH_HCFMREMAINING_FR_SHIFT (0U)
+/*! FR - FrameRemaining This counter is decremented at each bit time.
+ */
+#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
+#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U)
+#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U)
+/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval
+ * whenever FrameRemaining reaches 0.
+ */
+#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
+/*! @} */
+
+/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */
+/*! @{ */
+#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU)
+#define USBFSH_HCFMNUMBER_FN_SHIFT (0U)
+/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded.
+ */
+#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
+/*! @} */
+
+/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */
+/*! @{ */
+#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU)
+#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U)
+/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization.
+ */
+#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
+/*! @} */
+
+/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */
+/*! @{ */
+#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU)
+#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U)
+/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field
+ * prior to initiating a Low Speed transaction.
+ */
+#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
+/*! @} */
+
+/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */
+/*! @{ */
+#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU)
+#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U)
+/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub.
+ */
+#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
+#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U)
+#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U)
+/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled.
+ */
+#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
+#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U)
+#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U)
+/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered.
+ */
+#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
+#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U)
+#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U)
+/*! DT - DeviceType This bit specifies that the root hub is not a compound device.
+ */
+#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U)
+/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported.
+ */
+#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U)
+/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported.
+ */
+#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U)
+/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before
+ * accessing a powered-on port of the root hub.
+ */
+#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
+/*! @} */
+
+/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */
+/*! @{ */
+#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU)
+#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U)
+/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub.
+ */
+#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U)
+/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control
+ * command when PowerSwitchingMode is set.
+ */
+#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
+/*! @} */
+
+/*! @name HCRHSTATUS - This register is divided into two parts */
+/*! @{ */
+#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U)
+#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U)
+/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature;
+ * thus, this bit is always read as 0.
+ */
+#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
+#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U)
+#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U)
+/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented.
+ */
+#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
+#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U)
+#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U)
+/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume
+ * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected
+ * interrupt.
+ */
+#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
+#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U)
+#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U)
+/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature.
+ */
+#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
+#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U)
+#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U)
+/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register.
+ */
+#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
+#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U)
+#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U)
+/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable.
+ */
+#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
+/*! @} */
+
+/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */
+/*! @{ */
+#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U)
+#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U)
+/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port.
+ */
+#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
+#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U)
+#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U)
+/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled.
+ */
+#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
+#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U)
+#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U)
+/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence.
+ */
+#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
+#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U)
+#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U)
+/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in
+ * such a way that overcurrent conditions are reported on a per-port basis.
+ */
+#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U)
+#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U)
+/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted.
+ */
+#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
+#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U)
+#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U)
+/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type
+ * of power switching implemented.
+ */
+#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
+#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U)
+#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U)
+/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port.
+ */
+#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
+#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U)
+#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U)
+/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs.
+ */
+#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U)
+#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U)
+/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared.
+ */
+#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U)
+#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U)
+/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed.
+ */
+#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U)
+#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U)
+/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis.
+ */
+#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U)
+#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U)
+/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal.
+ */
+#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
+/*! @} */
+
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
+/*! @{ */
+#define USBFSH_PORTMODE_ID_MASK (0x1U)
+#define USBFSH_PORTMODE_ID_SHIFT (0U)
+/*! ID - Port ID pin value.
+ */
+#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
+#define USBFSH_PORTMODE_ID_EN_MASK (0x100U)
+#define USBFSH_PORTMODE_ID_EN_SHIFT (8U)
+/*! ID_EN - Port ID pin pull-up enable.
+ */
+#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
+#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
+#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
+/*! DEV_ENABLE - 1: device 0: host.
+ */
+#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBFSH_Register_Masks */
+
+
+/* USBFSH - Peripheral instance base addresses */
+/** Peripheral USBFSH base address */
+#define USBFSH_BASE (0x400A2000u)
+/** Peripheral USBFSH base pointer */
+#define USBFSH ((USBFSH_Type *)USBFSH_BASE)
+/** Array initializer of USBFSH peripheral base addresses */
+#define USBFSH_BASE_ADDRS { USBFSH_BASE }
+/** Array initializer of USBFSH peripheral base pointers */
+#define USBFSH_BASE_PTRS { USBFSH }
+/** Interrupt vectors for the USBFSH peripheral type */
+#define USBFSH_IRQS { USB0_IRQn }
+#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBFSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBHSD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
+ __I uint32_t INFO; /**< USB Info register, offset: 0x4 */
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
+ __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
+ __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
+ __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+ __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
+ __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
+ __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
+ uint8_t RESERVED_0[8];
+ __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
+} USBHSD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBHSD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Register_Masks USBHSD Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+/*! @{ */
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
+/*! DEV_ADDR - USB device address.
+ */
+#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U)
+#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U)
+/*! DEV_EN - USB device enable.
+ */
+#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
+#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U)
+#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U)
+/*! SETUP - SETUP token received.
+ */
+#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
+/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:.
+ */
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U)
+/*! FORCE_VBUS - If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled.
+ */
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
+/*! LPM_SUP - LPM Supported:.
+ */
+#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
+/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
+/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
+/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
+/*! INTONNAK_CI - Interrupt on NAK for control IN EP:.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U)
+#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U)
+/*! DCON - Device status - connect.
+ */
+#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U)
+#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U)
+/*! DSUS - Device status - suspend.
+ */
+#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
+/*! LPM_SUS - Device status - LPM Suspend.
+ */
+#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
+/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host.
+ */
+#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
+#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U)
+#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U)
+/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b:
+ * full-speed 10b: high-speed 11b: super-speed (reserved for future use).
+ */
+#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
+#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U)
+/*! DCON_C - Device status - connect change.
+ */
+#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
+#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U)
+/*! DSUS_C - Device status - suspend change.
+ */
+#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
+#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
+#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U)
+/*! DRES_C - Device status - reset change.
+ */
+#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U)
+/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not.
+ */
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U)
+/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.
+ */
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
+/*! @} */
+
+/*! @name INFO - USB Info register */
+/*! @{ */
+#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU)
+#define USBHSD_INFO_FRAME_NR_SHIFT (0U)
+/*! FRAME_NR - Frame number.
+ */
+#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
+#define USBHSD_INFO_ERR_CODE_MASK (0x7800U)
+#define USBHSD_INFO_ERR_CODE_SHIFT (11U)
+/*! ERR_CODE - The error code which last occurred:.
+ */
+#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
+#define USBHSD_INFO_Minrev_MASK (0xFF0000U)
+#define USBHSD_INFO_Minrev_SHIFT (16U)
+/*! Minrev - Minor revision.
+ */
+#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)
+#define USBHSD_INFO_Majrev_MASK (0xFF000000U)
+#define USBHSD_INFO_Majrev_SHIFT (24U)
+/*! Majrev - Major revision.
+ */
+#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)
+/*! @} */
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+/*! @{ */
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U)
+/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address.
+ */
+#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U)
+/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address.
+ */
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
+/*! @} */
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+/*! @{ */
+#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFC0000U)
+#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (18U)
+/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located.
+ */
+#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
+/*! @} */
+
+/*! @name LPM - USB Link Power Management register */
+/*! @{ */
+#define USBHSD_LPM_HIRD_HW_MASK (0xFU)
+#define USBHSD_LPM_HIRD_HW_SHIFT (0U)
+/*! HIRD_HW - Host Initiated Resume Duration - HW.
+ */
+#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
+#define USBHSD_LPM_HIRD_SW_MASK (0xF0U)
+#define USBHSD_LPM_HIRD_SW_SHIFT (4U)
+/*! HIRD_SW - Host Initiated Resume Duration - SW.
+ */
+#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
+#define USBHSD_LPM_DATA_PENDING_MASK (0x100U)
+#define USBHSD_LPM_DATA_PENDING_SHIFT (8U)
+/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will
+ * return a NYET handshake on every LPM token it receives.
+ */
+#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
+/*! @} */
+
+/*! @name EPSKIP - USB Endpoint skip */
+/*! @{ */
+#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU)
+#define USBHSD_EPSKIP_SKIP_SHIFT (0U)
+/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must
+ * deactivate the buffer assigned to this endpoint and return control back to software.
+ */
+#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
+/*! @} */
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+/*! @{ */
+#define USBHSD_EPINUSE_BUF_MASK (0xFFCU)
+#define USBHSD_EPINUSE_BUF_SHIFT (2U)
+/*! BUF - Buffer in use: This register has one bit per physical endpoint.
+ */
+#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
+/*! @} */
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+/*! @{ */
+#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU)
+#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U)
+/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint.
+ */
+#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
+/*! @} */
+
+/*! @name INTSTAT - USB interrupt status register */
+/*! @{ */
+#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U)
+#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U)
+/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
+#define USBHSD_INTSTAT_EP0IN_MASK (0x2U)
+#define USBHSD_INTSTAT_EP0IN_SHIFT (1U)
+/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction.
+ */
+#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
+#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U)
+#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U)
+/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
+#define USBHSD_INTSTAT_EP1IN_MASK (0x8U)
+#define USBHSD_INTSTAT_EP1IN_SHIFT (3U)
+/*! EP1IN - Interrupt status register bit for the EP1 IN direction.
+ */
+#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
+#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U)
+#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U)
+/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
+#define USBHSD_INTSTAT_EP2IN_MASK (0x20U)
+#define USBHSD_INTSTAT_EP2IN_SHIFT (5U)
+/*! EP2IN - Interrupt status register bit for the EP2 IN direction.
+ */
+#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
+#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U)
+#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U)
+/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
+#define USBHSD_INTSTAT_EP3IN_MASK (0x80U)
+#define USBHSD_INTSTAT_EP3IN_SHIFT (7U)
+/*! EP3IN - Interrupt status register bit for the EP3 IN direction.
+ */
+#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
+#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U)
+#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U)
+/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
+#define USBHSD_INTSTAT_EP4IN_MASK (0x200U)
+#define USBHSD_INTSTAT_EP4IN_SHIFT (9U)
+/*! EP4IN - Interrupt status register bit for the EP4 IN direction.
+ */
+#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
+#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U)
+#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U)
+/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
+#define USBHSD_INTSTAT_EP5IN_MASK (0x800U)
+#define USBHSD_INTSTAT_EP5IN_SHIFT (11U)
+/*! EP5IN - Interrupt status register bit for the EP5 IN direction.
+ */
+#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
+#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U)
+#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U)
+/*! FRAME_INT - Frame interrupt.
+ */
+#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
+#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U)
+#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U)
+/*! DEV_INT - Device status interrupt.
+ */
+#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
+/*! @} */
+
+/*! @name INTEN - USB interrupt enable register */
+/*! @{ */
+#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU)
+#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U)
+/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ * interrupt is generated on the interrupt line.
+ */
+#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
+#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U)
+#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U)
+/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ * interrupt is generated on the interrupt line.
+ */
+#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
+#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U)
+#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U)
+/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
+ * interrupt is generated on the interrupt line.
+ */
+#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
+/*! @} */
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+/*! @{ */
+#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU)
+#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U)
+/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
+ */
+#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
+/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
+ */
+#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
+/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
+ */
+#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
+/*! @} */
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+/*! @{ */
+#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU)
+#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U)
+/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
+ */
+#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Register_Masks */
+
+
+/* USBHSD - Peripheral instance base addresses */
+/** Peripheral USBHSD base address */
+#define USBHSD_BASE (0x40094000u)
+/** Peripheral USBHSD base pointer */
+#define USBHSD ((USBHSD_Type *)USBHSD_BASE)
+/** Array initializer of USBHSD peripheral base addresses */
+#define USBHSD_BASE_ADDRS { USBHSD_BASE }
+/** Array initializer of USBHSD peripheral base pointers */
+#define USBHSD_BASE_PTRS { USBHSD }
+/** Interrupt vectors for the USBHSD peripheral type */
+#define USBHSD_IRQS { USB1_IRQn }
+#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBHSH Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSH - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */
+ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */
+ __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */
+ __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */
+ __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
+ __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
+ __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
+ __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
+ __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */
+ __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */
+ __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */
+ __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */
+ __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */
+ __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */
+ __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */
+ __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */
+ __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */
+ __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */
+ __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
+} USBHSH_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBHSH Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Register_Masks USBHSH Register Masks
+ * @{
+ */
+
+/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */
+/*! @{ */
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U)
+/*! CAPLENGTH - Capability Length: This is used as an offset.
+ */
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U)
+/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major
+ * revision [23:16] = Minor revision Major revisions used: 0x01: USB2.
+ */
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
+/*! @} */
+
+/*! @name HCSPARAMS - Host Controller Structural Parameters */
+/*! @{ */
+#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU)
+#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U)
+/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller.
+ */
+#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
+#define USBHSH_HCSPARAMS_PPC_MASK (0x10U)
+#define USBHSH_HCSPARAMS_PPC_SHIFT (4U)
+/*! PPC - This field indicates whether the host controller implementation includes port power control.
+ */
+#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
+#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U)
+#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U)
+/*! P_INDICATOR - This bit indicates whether the ports support port indicator control.
+ */
+#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
+/*! @} */
+
+/*! @name HCCPARAMS - Host Controller Capability Parameters */
+/*! @{ */
+#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U)
+#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U)
+/*! LPMC - Link Power Management Capability.
+ */
+#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)
+/*! @} */
+
+/*! @name FLADJ_FRINDEX - Frame Length Adjustment */
+/*! @{ */
+#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU)
+#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U)
+/*! FLADJ - Frame Length Timing Value.
+ */
+#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U)
+/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet.
+ */
+#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
+/*! @} */
+
+/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */
+/*! @{ */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U)
+/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list.
+ */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U)
+/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list.
+ */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)
+/*! @} */
+
+/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */
+/*! @{ */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)
+/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list.
+ */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U)
+/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list.
+ */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)
+/*! @} */
+
+/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */
+/*! @{ */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)
+/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list.
+ */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U)
+/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list.
+ */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)
+/*! @} */
+
+/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */
+/*! @{ */
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)
+/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section.
+ */
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)
+/*! @} */
+
+/*! @name USBCMD - USB Command register */
+/*! @{ */
+#define USBHSH_USBCMD_RS_MASK (0x1U)
+#define USBHSH_USBCMD_RS_SHIFT (0U)
+/*! RS - Run/Stop: 1b = Run.
+ */
+#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
+#define USBHSH_USBCMD_HCRESET_MASK (0x2U)
+#define USBHSH_USBCMD_HCRESET_SHIFT (1U)
+/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller.
+ */
+#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
+#define USBHSH_USBCMD_FLS_MASK (0xCU)
+#define USBHSH_USBCMD_FLS_SHIFT (2U)
+/*! FLS - Frame List Size: This field specifies the size of the frame list.
+ */
+#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
+#define USBHSH_USBCMD_LHCR_MASK (0x80U)
+#define USBHSH_USBCMD_LHCR_SHIFT (7U)
+/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host
+ * controller without affecting the state of the ports.
+ */
+#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
+#define USBHSH_USBCMD_ATL_EN_MASK (0x100U)
+#define USBHSH_USBCMD_ATL_EN_SHIFT (8U)
+/*! ATL_EN - ATL List enabled.
+ */
+#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
+#define USBHSH_USBCMD_ISO_EN_MASK (0x200U)
+#define USBHSH_USBCMD_ISO_EN_SHIFT (9U)
+/*! ISO_EN - ISO List enabled.
+ */
+#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
+#define USBHSH_USBCMD_INT_EN_MASK (0x400U)
+#define USBHSH_USBCMD_INT_EN_SHIFT (10U)
+/*! INT_EN - INT List enabled.
+ */
+#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
+#define USBHSH_USBCMD_HIRD_MASK (0xF000000U)
+#define USBHSH_USBCMD_HIRD_SHIFT (24U)
+/*! HIRD - Host-Initiated Resume Duration.
+ */
+#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)
+/*! @} */
+
+/*! @name USBSTS - USB Interrupt Status register */
+/*! @{ */
+#define USBHSH_USBSTS_PCD_MASK (0x4U)
+#define USBHSH_USBSTS_PCD_SHIFT (2U)
+/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a
+ * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a
+ * result of a J-K transition detected on a suspended port.
+ */
+#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
+#define USBHSH_USBSTS_FLR_MASK (0x8U)
+#define USBHSH_USBSTS_FLR_SHIFT (3U)
+/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list
+ * index rolls over its maximum value to 0.
+ */
+#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
+#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U)
+#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U)
+/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed.
+ */
+#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
+#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U)
+#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U)
+/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed.
+ */
+#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
+#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U)
+#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U)
+/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed.
+ */
+#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
+#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U)
+#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U)
+/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set.
+ */
+#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
+/*! @} */
+
+/*! @name USBINTR - USB Interrupt Enable register */
+/*! @{ */
+#define USBHSH_USBINTR_PCDE_MASK (0x4U)
+#define USBHSH_USBINTR_PCDE_SHIFT (2U)
+/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
+#define USBHSH_USBINTR_FLRE_MASK (0x8U)
+#define USBHSH_USBINTR_FLRE_SHIFT (3U)
+/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
+#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U)
+#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U)
+/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
+#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U)
+#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U)
+/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
+#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U)
+#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U)
+/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
+#define USBHSH_USBINTR_SOF_E_MASK (0x80000U)
+#define USBHSH_USBINTR_SOF_E_SHIFT (19U)
+/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable.
+ */
+#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
+/*! @} */
+
+/*! @name PORTSC1 - Port Status and Control register */
+/*! @{ */
+#define USBHSH_PORTSC1_CCS_MASK (0x1U)
+#define USBHSH_PORTSC1_CCS_SHIFT (0U)
+/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port.
+ */
+#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
+#define USBHSH_PORTSC1_CSC_MASK (0x2U)
+#define USBHSH_PORTSC1_CSC_SHIFT (1U)
+/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed.
+ */
+#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
+#define USBHSH_PORTSC1_PED_MASK (0x4U)
+#define USBHSH_PORTSC1_PED_SHIFT (2U)
+/*! PED - Port Enabled/Disabled.
+ */
+#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
+#define USBHSH_PORTSC1_PEDC_MASK (0x8U)
+#define USBHSH_PORTSC1_PEDC_SHIFT (3U)
+/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed.
+ */
+#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
+#define USBHSH_PORTSC1_OCA_MASK (0x10U)
+#define USBHSH_PORTSC1_OCA_SHIFT (4U)
+/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition.
+ */
+#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
+#define USBHSH_PORTSC1_OCC_MASK (0x20U)
+#define USBHSH_PORTSC1_OCC_SHIFT (5U)
+/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed.
+ */
+#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
+#define USBHSH_PORTSC1_FPR_MASK (0x40U)
+#define USBHSH_PORTSC1_FPR_SHIFT (6U)
+/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port.
+ */
+#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
+#define USBHSH_PORTSC1_SUSP_MASK (0x80U)
+#define USBHSH_PORTSC1_SUSP_SHIFT (7U)
+/*! SUSP - Suspend: Logic 1 means port is in the suspend state.
+ */
+#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
+#define USBHSH_PORTSC1_PR_MASK (0x100U)
+#define USBHSH_PORTSC1_PR_SHIFT (8U)
+/*! PR - Port Reset: Logic 1 means the port is in the reset state.
+ */
+#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
+#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U)
+#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U)
+/*! SUS_L1 - Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a
+ * 1 and a non-zero value is specified in the Device Address field, the host controller will
+ * generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as
+ * well as L1 exit timing during any device or host-initiated resume.
+ */
+#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)
+#define USBHSH_PORTSC1_LS_MASK (0xC00U)
+#define USBHSH_PORTSC1_LS_SHIFT (10U)
+/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines.
+ */
+#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
+#define USBHSH_PORTSC1_PP_MASK (0x1000U)
+#define USBHSH_PORTSC1_PP_SHIFT (12U)
+/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register.
+ */
+#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
+#define USBHSH_PORTSC1_PIC_MASK (0xC000U)
+#define USBHSH_PORTSC1_PIC_SHIFT (14U)
+/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the
+ * HCSPARAMS register is logic 0.
+ */
+#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
+#define USBHSH_PORTSC1_PTC_MASK (0xF0000U)
+#define USBHSH_PORTSC1_PTC_SHIFT (16U)
+/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value.
+ */
+#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
+#define USBHSH_PORTSC1_PSPD_MASK (0x300000U)
+#define USBHSH_PORTSC1_PSPD_SHIFT (20U)
+/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved.
+ */
+#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
+#define USBHSH_PORTSC1_WOO_MASK (0x400000U)
+#define USBHSH_PORTSC1_WOO_SHIFT (22U)
+/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to
+ * overcurrent conditions as wake-up events.
+ */
+#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
+#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U)
+#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U)
+/*! SUS_STAT - These two bits are used by software to determine whether the most recent L1 suspend
+ * request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet -
+ * Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not
+ * support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred.
+ */
+#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)
+#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U)
+#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U)
+/*! DEV_ADD - Device Address for LPM tokens.
+ */
+#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)
+/*! @} */
+
+/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */
+/*! @{ */
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U)
+/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
+ */
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)
+/*! @} */
+
+/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */
+/*! @{ */
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U)
+/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be
+ * skipped, independent of the V bit setting.
+ */
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)
+/*! @} */
+
+/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */
+/*! @{ */
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U)
+/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
+ */
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)
+/*! @} */
+
+/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */
+/*! @{ */
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U)
+/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
+ */
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)
+/*! @} */
+
+/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */
+/*! @{ */
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U)
+/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
+ */
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)
+/*! @} */
+
+/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */
+/*! @{ */
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U)
+/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be
+ * skipped, independent of the V bit setting.
+ */
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)
+/*! @} */
+
+/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */
+/*! @{ */
+#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU)
+#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U)
+/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed.
+ */
+#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK)
+#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U)
+#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U)
+/*! ISO_LAST - This indicates the last PTD in the ISO list.
+ */
+#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK)
+#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U)
+#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U)
+/*! INT_LAST - This indicates the last PTD in the INT list.
+ */
+#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK)
+/*! @} */
+
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
+/*! @{ */
+#define USBHSH_PORTMODE_ID0_MASK (0x1U)
+#define USBHSH_PORTMODE_ID0_SHIFT (0U)
+/*! ID0 - Port 0 ID pin value.
+ */
+#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)
+#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U)
+#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U)
+/*! ID0_EN - Port 0 ID pin pull-up enable.
+ */
+#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)
+#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
+#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
+/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device.
+ */
+#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U)
+/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware.
+ */
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
+#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U)
+#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U)
+/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b.
+ */
+#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Register_Masks */
+
+
+/* USBHSH - Peripheral instance base addresses */
+/** Peripheral USBHSH base address */
+#define USBHSH_BASE (0x400A3000u)
+/** Peripheral USBHSH base pointer */
+#define USBHSH ((USBHSH_Type *)USBHSH_BASE)
+/** Array initializer of USBHSH peripheral base addresses */
+#define USBHSH_BASE_ADDRS { USBHSH_BASE }
+/** Array initializer of USBHSH peripheral base pointers */
+#define USBHSH_BASE_PTRS { USBHSH }
+/** Interrupt vectors for the USBHSH peripheral type */
+#define USBHSH_IRQS { USB1_IRQn }
+#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UTICK Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
+ * @{
+ */
+
+/** UTICK - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control register., offset: 0x0 */
+ __IO uint32_t STAT; /**< Status register., offset: 0x4 */
+ __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */
+ __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */
+ __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */
+} UTICK_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UTICK Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register. */
+/*! @{ */
+#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)
+#define UTICK_CTRL_DELAYVAL_SHIFT (0U)
+/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer
+ * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer.
+ */
+#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
+#define UTICK_CTRL_REPEAT_MASK (0x80000000U)
+#define UTICK_CTRL_REPEAT_SHIFT (31U)
+/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously.
+ */
+#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
+/*! @} */
+
+/*! @name STAT - Status register. */
+/*! @{ */
+#define UTICK_STAT_INTR_MASK (0x1U)
+#define UTICK_STAT_INTR_SHIFT (0U)
+/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any
+ * value to this register clears this flag.
+ */
+#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
+#define UTICK_STAT_ACTIVE_MASK (0x2U)
+#define UTICK_STAT_ACTIVE_SHIFT (1U)
+/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active.
+ */
+#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
+/*! @} */
+
+/*! @name CFG - Capture configuration register. */
+/*! @{ */
+#define UTICK_CFG_CAPEN0_MASK (0x1U)
+#define UTICK_CFG_CAPEN0_SHIFT (0U)
+/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled.
+ */
+#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
+#define UTICK_CFG_CAPEN1_MASK (0x2U)
+#define UTICK_CFG_CAPEN1_SHIFT (1U)
+/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled.
+ */
+#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
+#define UTICK_CFG_CAPEN2_MASK (0x4U)
+#define UTICK_CFG_CAPEN2_SHIFT (2U)
+/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled.
+ */
+#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
+#define UTICK_CFG_CAPEN3_MASK (0x8U)
+#define UTICK_CFG_CAPEN3_SHIFT (3U)
+/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled.
+ */
+#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
+#define UTICK_CFG_CAPPOL0_MASK (0x100U)
+#define UTICK_CFG_CAPPOL0_SHIFT (8U)
+/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture.
+ */
+#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
+#define UTICK_CFG_CAPPOL1_MASK (0x200U)
+#define UTICK_CFG_CAPPOL1_SHIFT (9U)
+/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture.
+ */
+#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
+#define UTICK_CFG_CAPPOL2_MASK (0x400U)
+#define UTICK_CFG_CAPPOL2_SHIFT (10U)
+/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture.
+ */
+#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
+#define UTICK_CFG_CAPPOL3_MASK (0x800U)
+#define UTICK_CFG_CAPPOL3_SHIFT (11U)
+/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture.
+ */
+#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
+/*! @} */
+
+/*! @name CAPCLR - Capture clear register. */
+/*! @{ */
+#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)
+#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)
+/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value.
+ */
+#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
+#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)
+#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)
+/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value.
+ */
+#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
+#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)
+#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)
+/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value.
+ */
+#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
+#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)
+#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)
+/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value.
+ */
+#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
+/*! @} */
+
+/*! @name CAP - Capture register . */
+/*! @{ */
+#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)
+#define UTICK_CAP_CAP_VALUE_SHIFT (0U)
+/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower
+ * than the actual value of the Micro-tick Timer at the moment of the capture event.
+ */
+#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
+#define UTICK_CAP_VALID_MASK (0x80000000U)
+#define UTICK_CAP_VALID_SHIFT (31U)
+/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related
+ * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.
+ */
+#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
+/*! @} */
+
+/* The count of UTICK_CAP */
+#define UTICK_CAP_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group UTICK_Register_Masks */
+
+
+/* UTICK - Peripheral instance base addresses */
+/** Peripheral UTICK0 base address */
+#define UTICK0_BASE (0x4000E000u)
+/** Peripheral UTICK0 base pointer */
+#define UTICK0 ((UTICK_Type *)UTICK0_BASE)
+/** Array initializer of UTICK peripheral base addresses */
+#define UTICK_BASE_ADDRS { UTICK0_BASE }
+/** Array initializer of UTICK peripheral base pointers */
+#define UTICK_BASE_PTRS { UTICK0 }
+/** Interrupt vectors for the UTICK peripheral type */
+#define UTICK_IRQS { UTICK0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UTICK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WWDT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
+ * @{
+ */
+
+/** WWDT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
+ __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
+ __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
+ __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
+ __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */
+} WWDT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- WWDT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks
+ * @{
+ */
+
+/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+/*! @{ */
+#define WWDT_MOD_WDEN_MASK (0x1U)
+#define WWDT_MOD_WDEN_SHIFT (0U)
+/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the
+ * watchdog timer will run permanently.
+ * 0b0..Stop. The watchdog timer is stopped.
+ * 0b1..Run. The watchdog timer is running.
+ */
+#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
+#define WWDT_MOD_WDRESET_MASK (0x2U)
+#define WWDT_MOD_WDRESET_SHIFT (1U)
+/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
+ * 0b0..Interrupt. A watchdog time-out will not cause a chip reset.
+ * 0b1..Reset. A watchdog time-out will cause a chip reset.
+ */
+#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
+#define WWDT_MOD_WDTOF_MASK (0x4U)
+#define WWDT_MOD_WDTOF_SHIFT (2U)
+/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by
+ * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a
+ * chip reset if WDRESET = 1.
+ */
+#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
+#define WWDT_MOD_WDINT_MASK (0x8U)
+#define WWDT_MOD_WDINT_SHIFT (3U)
+/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT.
+ * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the
+ * WARNINT value is equal to the value of the TV register. This can occur if the value of
+ * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.
+ */
+#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
+#define WWDT_MOD_WDPROTECT_MASK (0x10U)
+#define WWDT_MOD_WDPROTECT_SHIFT (4U)
+/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
+ * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time.
+ * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.
+ */
+#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
+#define WWDT_MOD_LOCK_MASK (0x20U)
+#define WWDT_MOD_LOCK_SHIFT (5U)
+/*! LOCK - Once this bit is set to one and a watchdog feed is performed, disabling or powering down
+ * the watchdog oscillator is prevented by hardware. This bit can be set once by software and is
+ * only cleared by any reset.
+ */
+#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
+/*! @} */
+
+/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
+/*! @{ */
+#define WWDT_TC_COUNT_MASK (0xFFFFFFU)
+#define WWDT_TC_COUNT_SHIFT (0U)
+/*! COUNT - Watchdog time-out value.
+ */
+#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
+/*! @} */
+
+/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
+/*! @{ */
+#define WWDT_FEED_FEED_MASK (0xFFU)
+#define WWDT_FEED_FEED_SHIFT (0U)
+/*! FEED - Feed value should be 0xAA followed by 0x55.
+ */
+#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
+/*! @} */
+
+/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
+/*! @{ */
+#define WWDT_TV_COUNT_MASK (0xFFFFFFU)
+#define WWDT_TV_COUNT_SHIFT (0U)
+/*! COUNT - Counter timer value.
+ */
+#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
+/*! @} */
+
+/*! @name WARNINT - Watchdog Warning Interrupt compare value. */
+/*! @{ */
+#define WWDT_WARNINT_WARNINT_MASK (0x3FFU)
+#define WWDT_WARNINT_WARNINT_SHIFT (0U)
+/*! WARNINT - Watchdog warning interrupt compare value.
+ */
+#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
+/*! @} */
+
+/*! @name WINDOW - Watchdog Window compare value. */
+/*! @{ */
+#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)
+#define WWDT_WINDOW_WINDOW_SHIFT (0U)
+/*! WINDOW - Watchdog window value.
+ */
+#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WWDT_Register_Masks */
+
+
+/* WWDT - Peripheral instance base addresses */
+/** Peripheral WWDT base address */
+#define WWDT_BASE (0x4000C000u)
+/** Peripheral WWDT base pointer */
+#define WWDT ((WWDT_Type *)WWDT_BASE)
+/** Array initializer of WWDT peripheral base addresses */
+#define WWDT_BASE_ADDRS { WWDT_BASE }
+/** Array initializer of WWDT peripheral base pointers */
+#define WWDT_BASE_PTRS { WWDT }
+/** Interrupt vectors for the WWDT peripheral type */
+#define WWDT_IRQS { WDT_BOD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WWDT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+ #else
+ #pragma pop
+ #endif
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header
+ #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+/** EMC CS base address */
+#define EMC_CS0_BASE (0x80000000u)
+#define EMC_CS1_BASE (0x88000000u)
+#define EMC_CS2_BASE (0x90000000u)
+#define EMC_CS3_BASE (0x98000000u)
+#define EMC_DYCS0_BASE (0xA0000000u)
+#define EMC_DYCS1_BASE (0xA8000000u)
+#define EMC_DYCS2_BASE (0xB0000000u)
+#define EMC_DYCS3_BASE (0xB8000000u)
+#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}
+#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}
+
+/** OTP API */
+typedef struct {
+ uint32_t (*otpInit)(void); /** Initializes OTP controller */
+ uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */
+ uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */
+ uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
+ uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */
+ uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
+ uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */
+ uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */
+ uint32_t RESERVED_0[5];
+ uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */
+ uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */
+} OTP_API_Type;
+
+/** ROM API */
+typedef struct {
+ __I uint32_t usbdApiBase; /** USB API Base */
+ uint32_t RESERVED_0[13];
+ __I OTP_API_Type *otpApiBase; /** OTP API Base */
+ __I uint32_t aesApiBase; /** AES API Base */
+ __I uint32_t secureApiBase; /** Secure API Base */
+} ROM_API_Type;
+
+/** ROM API base address */
+#define ROM_API_BASE (0x03000200u)
+/** ROM API base pointer */
+#define ROM_API (*(ROM_API_Type**) ROM_API_BASE)
+/** OTP API base pointer */
+#define OTP_API (ROM_API->otpApiBase)
+
+/** Used for selecting the address of FROHF setting API in ROM */
+#define FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION 1U
+#define FSL_ROM_VERSION_0A 0U
+#define FSL_ROM_VERSION_1B 1U
+#define FSL_ROM_VERSION_0A_FRO_SETTING_ADDR 0x03007933U
+#define FSL_ROM_VERSION_1B_FRO_SETTING_ADDR 0x03008D9BU
+
+/*!
+ * @brief Get the chip value.
+ *
+ * @return chip version, 0x0: 0A version chip, 0x1: 1B version chip, 0xFF: invalid version.
+ */
+static inline uint32_t Chip_GetVersion(void)
+{
+ uint8_t romVersion = 0U;
+ uint32_t command[5] = {0U}, result[4] = {0U};
+ uint32_t syscon_iap_entry_location = 0x03000205;
+
+ command[0] = 55U;
+ result[0] = 0;
+ result[1] = 0;
+ ((void (*)(uint32_t cmd[5], uint32_t stat[4]))syscon_iap_entry_location)(command, result);
+
+ romVersion = (uint8_t)(result[1]);
+
+ if (0U == result[0])
+ {
+ if (romVersion == FSL_ROM_VERSION_1B)
+ {
+ return FSL_ROM_VERSION_1B;
+ }
+ else if (romVersion == FSL_ROM_VERSION_0A)
+ {
+ return FSL_ROM_VERSION_0A;
+ }
+ else
+ {
+ return 0xFF;
+ }
+ }
+ else
+ {
+ return 0xFF;
+ }
+}
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif /* _LPC54018_H_ */
+
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/LPC54018_features.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/LPC54018_features.h new file mode 100644 index 000000000..f470552bc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/LPC54018_features.h @@ -0,0 +1,348 @@ +/*
+** ###################################################################
+** Version: rev. 1.2, 2017-06-08
+** Build: b191115
+**
+** Abstract:
+** Chip specific module features.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2016-08-12)
+** Initial version.
+** - rev. 1.1 (2016-11-25)
+** Update CANFD and Classic CAN register.
+** Add MAC TIMERSTAMP registers.
+** - rev. 1.2 (2017-06-08)
+** Remove RTC_CTRL_RTC_OSC_BYPASS.
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+#ifndef _LPC54018_FEATURES_H_
+#define _LPC54018_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief ASYNC_SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
+/* @brief CAN availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_CAN_COUNT (2)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief EMC availability on the SoC. */
+#define FSL_FEATURE_SOC_EMC_COUNT (1)
+/* @brief ENET availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_ENET_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (11)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (2)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (10)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (2)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief LCD availability on the SoC. */
+#define FSL_FEATURE_SOC_LCD_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief RIT availability on the SoC. */
+#define FSL_FEATURE_SOC_RIT_COUNT (1)
+/* @brief RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SDIF availability on the SoC. */
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)
+/* @brief SHA availability on the SoC. */
+#define FSL_FEATURE_SOC_SHA_COUNT (1)
+/* @brief SMARTCARD availability on the SoC. */
+#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (11)
+/* @brief SPIFI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (10)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBFSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
+/* @brief USBHSD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
+/* @brief USBHSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+
+/* ADC module features */
+
+/* @brief Do not has input select (register INSEL). */
+#define FSL_FEATURE_ADC_HAS_NO_INSEL (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
+/* @brief Has startup register. */
+#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1)
+/* @brief Has ADTrim register */
+#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
+/* @brief Has Calibration register. */
+#define FSL_FEATURE_ADC_HAS_CALIB_REG (1)
+
+/* CAN module features */
+
+/* @brief Support CANFD or not */
+#define FSL_FEATURE_CAN_SUPPORT_CANFD (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
+/* @brief Align size of DMA descriptor */
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
+/* @brief DMA head link descriptor table align size */
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
+
+/* FLEXCOMM module features */
+
+/* @brief FLEXCOMM0 USART INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
+/* @brief FLEXCOMM0 SPI INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
+/* @brief FLEXCOMM0 I2C INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
+/* @brief FLEXCOMM1 USART INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
+/* @brief FLEXCOMM1 SPI INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
+/* @brief FLEXCOMM1 I2C INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
+/* @brief FLEXCOMM2 USART INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
+/* @brief FLEXCOMM2 SPI INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
+/* @brief FLEXCOMM2 I2C INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
+/* @brief FLEXCOMM3 USART INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
+/* @brief FLEXCOMM3 SPI INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
+/* @brief FLEXCOMM3 I2C INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
+/* @brief FLEXCOMM4 USART INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
+/* @brief FLEXCOMM4 SPI INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
+/* @brief FLEXCOMM4 I2C INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
+/* @brief FLEXCOMM5 USART INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
+/* @brief FLEXCOMM5 SPI INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
+/* @brief FLEXCOMM5 I2C INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
+/* @brief FLEXCOMM6 USART INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
+/* @brief FLEXCOMM6 SPI INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
+/* @brief FLEXCOMM6 I2C INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
+/* @brief FLEXCOMM7 I2S INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0)
+/* @brief FLEXCOMM7 USART INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
+/* @brief FLEXCOMM7 SPI INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
+/* @brief FLEXCOMM7 I2C INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
+/* @brief FLEXCOMM7 I2S INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1)
+/* @brief FLEXCOMM4 USART INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_USART_INDEX (8)
+/* @brief FLEXCOMM4 SPI INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
+/* @brief FLEXCOMM4 I2C INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_I2C_INDEX (8)
+/* @brief FLEXCOMM5 USART INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_USART_INDEX (9)
+/* @brief FLEXCOMM5 SPI INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_SPI_INDEX (9)
+/* @brief FLEXCOMM5 I2C INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_I2C_INDEX (9)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \
+ (((x) == FLEXCOMM0) ? (0) : \
+ (((x) == FLEXCOMM1) ? (0) : \
+ (((x) == FLEXCOMM2) ? (0) : \
+ (((x) == FLEXCOMM3) ? (0) : \
+ (((x) == FLEXCOMM4) ? (0) : \
+ (((x) == FLEXCOMM5) ? (0) : \
+ (((x) == FLEXCOMM6) ? (0) : \
+ (((x) == FLEXCOMM7) ? (1) : \
+ (((x) == FLEXCOMM8) ? (0) : \
+ (((x) == FLEXCOMM9) ? (0) : \
+ (((x) == FLEXCOMM10) ? (0) : (-1))))))))))))
+
+/* I2S module features */
+
+/* @brief I2S support dual channel transfer */
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1)
+
+/* IOCON module features */
+
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
+
+/* MRT module features */
+
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+
+/* RIT module features */
+
+/* @brief RIT has no reset control */
+#define FSL_FEATURE_RIT_HAS_NO_RESET (1)
+
+/* RTC module features */
+
+/* @brief RTC has no reset control */
+#define FSL_FEATURE_RTC_HAS_NO_RESET (1)
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
+
+/* SDIF module features */
+
+/* @brief FIFO depth, every location is a WORD */
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
+/* @brief Max DMA buffer size */
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
+/* @brief Max source clock in HZ */
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
+
+/* SPIFI module features */
+
+/* @brief SPIFI start address */
+#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
+/* @brief SPIFI end address */
+#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
+
+/* SYSCON module features */
+
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+
+/* USB module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USB version */
+#define FSL_FEATURE_USB_VERSION (200)
+/* @brief Number of the endpoint in USB FS */
+#define FSL_FEATURE_USB_EP_NUM (5)
+
+/* USBFSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBFSH version */
+#define FSL_FEATURE_USBFSH_VERSION (200)
+
+/* USBHSD module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBHSD_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBHSD_EP_NUM (6)
+/* @brief Resetting interrupt endpoint resets DATAx sequence to DATA.1 */
+#define FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK (1)
+
+/* USBHSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSH version */
+#define FSL_FEATURE_USBHSH_VERSION (300)
+
+#endif /* _LPC54018_FEATURES_H_ */
+
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/fsl_device_registers.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/fsl_device_registers.h new file mode 100644 index 000000000..7b00306e9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/fsl_device_registers.h @@ -0,0 +1,34 @@ +/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_LPC54018JBD208) || defined(CPU_LPC54018JET180))
+
+#define LPC54018_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC54018.h"
+/* CPU specific feature definitions */
+#include "LPC54018_features.h"
+
+#else
+ #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/system_LPC54018.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/system_LPC54018.c new file mode 100644 index 000000000..d658dd374 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/system_LPC54018.c @@ -0,0 +1,368 @@ +/*
+** ###################################################################
+** Processors: LPC54018JBD208
+** LPC54018JET180
+**
+** Compilers: GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** Keil ARM C/C++ Compiler
+** MCUXpresso Compiler
+**
+** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+** Version: rev. 1.2, 2017-06-08
+** Build: b191014
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2016-08-12)
+** Initial version.
+** - rev. 1.1 (2016-11-25)
+** Update CANFD and Classic CAN register.
+** Add MAC TIMERSTAMP registers.
+** - rev. 1.2 (2017-06-08)
+** Remove RTC_CTRL_RTC_OSC_BYPASS.
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54018
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief Device specific configuration file for LPC54018 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#define NVALMAX (0x100)
+#define PVALMAX (0x20)
+#define MVALMAX (0x8000)
+#define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
+#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
+
+extern void *__Vectors;
+
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
+ 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/* Get WATCH DOG Clk */
+static uint32_t getWdtOscFreq(void)
+{
+ uint8_t freq_sel, div_sel;
+ if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+ {
+ return 0U;
+ }
+ else
+ {
+ div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
+ freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+ return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
+ }
+}
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+ uint32_t n, x, i;
+
+ /* Find NDec */
+ switch (NDEC)
+ {
+ case 0x3FF:
+ n = 0UL;
+ break;
+ case 0x302:
+ n = 1UL;
+ break;
+ case 0x202:
+ n = 2UL;
+ break;
+ default:
+ x = 0x080UL;
+ n = 0xFFFFFFFFUL;
+ for (i = NVALMAX; i >= 3UL; i--)
+ {
+ x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
+ if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+ {
+ /* Decoded value of NDEC */
+ n = i;
+ }
+ if (n != 0xFFFFFFFFUL)
+ {
+ break;
+ }
+ }
+ break;
+ }
+ return n;
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+ uint32_t p, x, i;
+ /* Find PDec */
+ switch (PDEC)
+ {
+ case 0x7F:
+ p = 0UL;
+ break;
+ case 0x62:
+ p = 1UL;
+ break;
+ case 0x42:
+ p = 2UL;
+ break;
+ default:
+ x = 0x10UL;
+ p = 0xFFFFFFFFUL;
+ for (i = PVALMAX; i >= 3UL; i--)
+ {
+ x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
+ if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+ {
+ /* Decoded value of PDEC */
+ p = i;
+ }
+ if (p != 0xFFFFFFFFUL)
+ {
+ break;
+ }
+ }
+ break;
+ }
+ return p;
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+ uint32_t m, i, x;
+
+ /* Find MDec */
+ switch (MDEC)
+ {
+ case 0x1FFFF:
+ m = 0UL;
+ break;
+ case 0x18003:
+ m = 1UL;
+ break;
+ case 0x10003:
+ m = 2UL;
+ break;
+ default:
+ x = 0x04000UL;
+ m = 0xFFFFFFFFUL;
+ for (i = MVALMAX; i >= 3UL; i--)
+ {
+ x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
+ if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
+ {
+ /* Decoded value of MDEC */
+ m = i;
+ }
+ if (m != 0xFFFFFFFFUL)
+ {
+ break;
+ }
+ }
+ break;
+ }
+ return m;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+ uint32_t preDiv = 1;
+
+ /* Direct input is not used? */
+ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)
+ {
+ /* Decode NDEC value to get (N) pre divider */
+ preDiv = pllDecodeN(nDecReg & 0x3FFUL);
+ if (preDiv == 0UL)
+ {
+ preDiv = 1;
+ }
+ }
+ /* Adjusted by 1, directi is used to bypass */
+ return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+ uint32_t postDiv = 1;
+
+ /* Direct input is not used? */
+ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)
+ {
+ /* Decode PDEC value to get (P) post divider */
+ postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);
+ if (postDiv == 0UL)
+ {
+ postDiv = 2;
+ }
+ }
+ /* Adjusted by 1, directo is used to bypass */
+ return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+ uint32_t mMult = 1;
+
+ /* Decode MDEC value to get (M) multiplier */
+ mMult = pllDecodeM(mDecReg & 0x1FFFFUL);
+ if (mMult == 0UL)
+ {
+ mMult = 1;
+ }
+ return mMult;
+}
+
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if defined(__MCUXPRESSO)
+ extern void(*const g_pfnVectors[]) (void);
+ SCB->VTOR = (uint32_t) &g_pfnVectors;
+#else
+ extern void *__Vectors;
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+ SYSCON->ARMTRACECLKDIV = 0;
+/* Optionally enable RAM banks that may be off by default at reset */
+#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
+ SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
+
+#endif
+ SYSCON->MAINCLKSELA = 0U;
+ SYSCON->MAINCLKSELB = 0U;
+ SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+uint32_t clkRate = 0;
+ uint32_t prediv, postdiv;
+ uint64_t workRate;
+
+ switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
+ {
+ case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
+ switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
+ {
+ case 0x00: /* FRO 12 MHz (fro_12m) */
+ clkRate = CLK_FRO_12MHZ;
+ break;
+ case 0x01: /* CLKIN Source (clk_in) */
+ clkRate = CLK_CLK_IN;
+ break;
+ case 0x02: /* Watchdog oscillator (wdt_clk) */
+ clkRate = getWdtOscFreq();
+ break;
+ default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
+ if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
+ {
+ clkRate = CLK_FRO_96MHZ;
+ }
+ else
+ {
+ clkRate = CLK_FRO_48MHZ;
+ }
+ break;
+ }
+ break;
+ case 0x02: /* System PLL clock (pll_clk)*/
+ switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+ {
+ case 0x00: /* FRO 12 MHz (fro_12m) */
+ clkRate = CLK_FRO_12MHZ;
+ break;
+ case 0x01: /* CLKIN Source (clk_in) */
+ clkRate = CLK_CLK_IN;
+ break;
+ case 0x02: /* Watchdog oscillator (wdt_clk) */
+ clkRate = getWdtOscFreq();
+ break;
+ case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+ clkRate = CLK_RTC_32K_CLK;
+ break;
+ default:
+ break;
+ }
+ if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0UL)
+ {
+ /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
+ prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
+ postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
+ /* Adjust input clock */
+ clkRate = clkRate / prediv;
+
+ /* MDEC used for rate */
+ workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
+ clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
+ clkRate = clkRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */
+ }
+ break;
+ case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+ clkRate = CLK_RTC_32K_CLK;
+ break;
+ default:
+ break;
+ }
+ SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemInitHook()
+ ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+ /* Void implementation of the weak function. */
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/system_LPC54018.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/system_LPC54018.h new file mode 100644 index 000000000..d392e1d4f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/system_LPC54018.h @@ -0,0 +1,116 @@ +/*
+** ###################################################################
+** Processors: LPC54018JBD208
+** LPC54018JET180
+**
+** Compilers: GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** Keil ARM C/C++ Compiler
+** MCUXpresso Compiler
+**
+** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+** Version: rev. 1.2, 2017-06-08
+** Build: b191014
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2016-08-12)
+** Initial version.
+** - rev. 1.1 (2016-11-25)
+** Update CANFD and Classic CAN register.
+** Add MAC TIMERSTAMP registers.
+** - rev. 1.2 (2017-06-08)
+** Remove RTC_CTRL_RTC_OSC_BYPASS.
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54018
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief Device specific configuration file for LPC54018 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_LPC54018_H_
+#define _SYSTEM_LPC54018_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
+#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_LPC54018_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_clock.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_clock.c new file mode 100644 index 000000000..98cf2bcee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_clock.c @@ -0,0 +1,2827 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2019 , NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_clock.h"
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.clock"
+#endif
+#define NVALMAX (0x100U)
+#define PVALMAX (0x20U)
+#define MVALMAX (0x8000U)
+
+#define USB_NVALMAX (0x4U)
+#define USB_PVALMAX (0x8U)
+#define USB_MVALMAX (0x100U)
+
+#define PLL_MAX_N_DIV 0x100U
+#define USB_PLL_MAX_N_DIV 0x100U
+
+#define PLL_MDEC_VAL_P (0U) /*!< MDEC is in bits 16 downto 0 */
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P) /*!< NDEC is in bits 9 downto 0 */
+#define PLL_NDEC_VAL_P (0U) /*!< NDEC is in bits 9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
+
+#define PLL_MIN_CCO_FREQ_MHZ (275000000U)
+#define PLL_MAX_CCO_FREQ_MHZ (550000000U)
+#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */
+#define PLL_MIN_IN_SSMODE (2000000U)
+#define PLL_MAX_IN_SSMODE (4000000U)
+
+/*!< Middle of the range values for spread-spectrum */
+#define PLL_SSCG_MF_FREQ_VALUE 4U
+#define PLL_SSCG_MC_COMP_VALUE 2U
+#define PLL_SSCG_MR_DEPTH_VALUE 4U
+#define PLL_SSCG_DITHER_VALUE 0U
+
+/*!< USB PLL CCO MAX AND MIN FREQ */
+#define USB_PLL_MIN_CCO_FREQ_MHZ (156000000U)
+#define USB_PLL_MAX_CCO_FREQ_MHZ (320000000U)
+#define USB_PLL_LOWER_IN_LIMIT (1000000U) /*!< Minimum PLL input rate */
+
+#define USB_PLL_MSEL_VAL_P (0U) /*!< MSEL is in bits 7 downto 0 */
+#define USB_PLL_MSEL_VAL_M (0xFFU)
+#define USB_PLL_PSEL_VAL_P (8U) /*!< PDEC is in bits 9:8 */
+#define USB_PLL_PSEL_VAL_M (0x3U)
+#define USB_PLL_NSEL_VAL_P (10U) /*!< NDEC is in bits 11:10 */
+#define USB_PLL_NSEL_VAL_M (0x3U)
+
+/*!< SWITCH USB POSTDIVIDER FOR REGITSER WRITING */
+#define SWITCH_USB_PSEL(x) \
+ (((x) == 0x0U) ? 0x1U : ((x) == 0x1U) ? 0x02U : ((x) == 0x2U) ? 0x4U : ((x) == 3U) ? 0x8U : 0U)
+
+/*!< SYS PLL NDEC reg */
+#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)
+/*!< SYS PLL PDEC reg */
+#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)
+/*!< SYS PLL MDEC reg */
+#define PLL_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_MDEC_VAL_P) & PLL_MDEC_VAL_M)
+
+/*!< SYS PLL NSEL reg */
+#define USB_PLL_NSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_NSEL_VAL_M) << USB_PLL_NSEL_VAL_P)
+/*!< SYS PLL PSEL reg */
+#define USB_PLL_PSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_PSEL_VAL_M) << USB_PLL_PSEL_VAL_P)
+/*!< SYS PLL MSEL reg */
+#define USB_PLL_MSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_MSEL_VAL_M) << USB_PLL_MSEL_VAL_P)
+
+/*!< FRAC control */
+#define AUDIO_PLL_FRACT_MD_P (0U)
+#define AUDIO_PLL_FRACT_MD_INT_P (15U)
+#define AUDIO_PLL_FRACT_MD_M (0x7FFFUL << AUDIO_PLL_FRACT_MD_P)
+#define AUDIO_PLL_FRACT_MD_INT_M (0x7FUL << AUDIO_PLL_FRACT_MD_INT_P)
+
+#define AUDIO_PLL_MD_FRACT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_P) & PLL_FRAC_MD_FRACT_M)
+#define AUDIO_PLL_MD_INT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_INT_P) & AUDIO_PLL_FRACT_MD_INT_M)
+
+/* Saved value of PLL output rate, computed whenever needed to save run-time
+ computation on each call to retrive the PLL rate. */
+static uint32_t s_Pll_Freq;
+static uint32_t s_Usb_Pll_Freq;
+static uint32_t s_Audio_Pll_Freq;
+
+/** External clock rate on the CLKIN pin in Hz. If not used,
+ set this to 0. Otherwise, set it to the exact rate in Hz this pin is
+ being driven at. */
+static const uint32_t g_I2S_Mclk_Freq = 0U;
+static const uint32_t g_Ext_Clk_Freq = 12000000U;
+static const uint32_t g_Lcd_Clk_In_Freq = 0U;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */
+static uint32_t pllEncodeN(uint32_t N);
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC);
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */
+static uint32_t pllEncodeP(uint32_t P);
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC);
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */
+static uint32_t pllEncodeM(uint32_t M);
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC);
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR);
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg);
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg);
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg);
+/* Convert the binary to fractional part */
+static double Binary2Fractional(uint32_t binaryPart);
+/* Calculate the powerTimes' power of 2 */
+static uint32_t power2Cal(uint32_t powerTimes);
+/* Get the greatest common divisor */
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);
+/* Set PLL output based on desired output rate */
+static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup);
+
+/* Update local PLL rate variable */
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup);
+static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup);
+
+/*!
+ * @brief Set fro clock frequency.
+ * Due to LPC540xx 0A silicon and LPC540xx 1B silicon have different ROM addresses for set fro
+ * frequency api, so add this api to get rom version.
+ * @param base romVersion pointer to recieve rom version.
+ */
+#if defined(FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION) && \
+ (FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION)
+static uint32_t CLOCK_GetRomVersion(uint8_t *romVersion);
+#endif
+
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41,
+ 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION) && \
+ (FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION)
+static uint32_t CLOCK_GetRomVersion(uint8_t *romVersion)
+{
+ uint32_t command[5] = {0U}, result[4] = {0U};
+
+ command[0] = 55U;
+ result[0] = 0;
+ result[1] = 0;
+ ((void (*)(uint32_t cmd[5], uint32_t stat[4]))FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(command, result);
+
+ *romVersion = (uint8_t)(result[1]);
+
+ return result[0];
+}
+#endif
+
+/**
+ * brief
+ * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed
+ * output is enabled.
+ * Usage: CLOCK_SetupFROClocking(frequency), (frequency must be one of 12, 48 or 96 MHz)
+ * Note: Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is
+ * implemented in ROM code and the FROHF TRIM value is stored in OTP
+ *
+ * param froFreq target fro frequency.
+ * return Nothing
+ */
+
+void CLOCK_SetupFROClocking(uint32_t froFreq)
+{
+ uint32_t froRomAddr = 0U;
+#if defined(FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION) && \
+ (FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION)
+ uint8_t romVersion = 0U;
+
+ if (CLOCK_GetRomVersion(&romVersion) == (uint32_t)kStatus_Success)
+ {
+ if (romVersion == FSL_ROM_VERSION_1B)
+ {
+ froRomAddr = FSL_ROM_VERSION_1B_FRO_SETTING_ADDR;
+ }
+ else
+ {
+ froRomAddr = FSL_ROM_VERSION_0A_FRO_SETTING_ADDR;
+ }
+
+ (*((void (*)(uint32_t funcname))(froRomAddr)))(froFreq);
+ }
+#else
+ froRomAddr = FSL_ROM_VERSION_0A_FRO_SETTING_ADDR;
+
+ (*((void (*)(uint32_t))(froRomAddr)))(froFreq);
+#endif
+}
+
+/* Clock Selection for IP */
+/**
+ * brief Configure the clock selection muxes.
+ * param connection : Clock to be configured.
+ * return Nothing
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection)
+{
+ uint8_t mux;
+ uint8_t sel;
+ uint16_t item;
+ uint32_t tmp32 = (uint32_t)connection;
+ uint32_t i;
+ volatile uint32_t *pClkSel;
+
+ pClkSel = &(SYSCON->STICKCLKSEL);
+
+ if (kNONE_to_NONE != connection)
+ {
+ for (i = 0U; i < 2U; i++)
+ {
+ if (tmp32 == 0U)
+ {
+ break;
+ }
+ item = (uint16_t)GET_ID_ITEM(tmp32);
+ if (item != 0UL)
+ {
+ mux = GET_ID_ITEM_MUX(item);
+ sel = GET_ID_ITEM_SEL(item);
+ if (mux == CM_ASYNCAPB)
+ {
+ SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
+ ASYNC_SYSCON->ASYNCAPBCLKSELA = sel;
+ }
+ else
+ {
+ ((volatile uint32_t *)pClkSel)[mux] = sel;
+ }
+ }
+ tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */
+ }
+ }
+}
+
+/* Return the actual clock attach id */
+/**
+ * brief Get the actual clock attach id.
+ * This fuction uses the offset in input attach id, then it reads the actual source value in
+ * the register and combine the offset to obtain an actual attach id.
+ * param attachId : Clock attach id to get.
+ * return Clock source value.
+ */
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId)
+{
+ uint8_t mux;
+ uint8_t actualSel;
+ uint32_t tmp32 = (uint32_t)attachId;
+ uint32_t i;
+ uint32_t actualAttachId = 0U;
+ uint32_t selector = GET_ID_SELECTOR(tmp32);
+ volatile uint32_t *pClkSel;
+
+ pClkSel = &(SYSCON->STICKCLKSEL);
+
+ if (kNONE_to_NONE == attachId)
+ {
+ return kNONE_to_NONE;
+ }
+
+ for (i = 0U; i < 2U; i++)
+ {
+ mux = GET_ID_ITEM_MUX(tmp32);
+ if (tmp32 != 0UL)
+ {
+ if (mux == CM_ASYNCAPB)
+ {
+ actualSel = (uint8_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA);
+ }
+ else
+ {
+ actualSel = (uint8_t)(((volatile uint32_t *)pClkSel)[mux]);
+ }
+
+ /* Consider the combination of two registers */
+ actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i);
+ }
+ tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */
+ }
+
+ actualAttachId |= selector;
+
+ return (clock_attach_id_t)actualAttachId;
+}
+
+/* Set IP Clock Divider */
+/**
+ * brief Setup peripheral clock dividers.
+ * param div_name : Clock divider name
+ * param divided_by_value: Value to be divided
+ * param reset : Whether to reset the divider counter.
+ * return Nothing
+ */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
+{
+ volatile uint32_t *pClkDiv;
+
+ pClkDiv = &(SYSCON->SYSTICKCLKDIV);
+ if (reset)
+ {
+ ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 29U;
+ }
+ if (divided_by_value == 0U) /*!< halt */
+ {
+ ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 30U;
+ }
+ else
+ {
+ ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = (divided_by_value - 1U);
+ }
+}
+
+/* Get CLOCK OUT Clk */
+/*! brief Return Frequency of ClockOut
+ * return Frequency of ClockOut
+ */
+uint32_t CLOCK_GetClockOutClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->CLKOUTSELA)
+ {
+ case 0U:
+ freq = CLOCK_GetCoreSysClkFreq();
+ break;
+
+ case 1U:
+ freq = CLOCK_GetExtClkFreq();
+ break;
+
+ case 2U:
+ freq = CLOCK_GetWdtOscFreq();
+ break;
+
+ case 3U:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+
+ case 4U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+
+ case 5U:
+ freq = CLOCK_GetUsbPllOutFreq();
+ break;
+
+ case 6U:
+ freq = CLOCK_GetAudioPllOutFreq();
+ break;
+
+ case 7U:
+ freq = CLOCK_GetOsc32KFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+ return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U);
+}
+
+/* Get SPIFI Clk */
+/*! brief Return Frequency of Spifi Clock
+ * return Frequency of Spifi.
+ */
+uint32_t CLOCK_GetSpifiClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->SPIFICLKSEL)
+ {
+ case 0U:
+ freq = CLOCK_GetCoreSysClkFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+ case 2U:
+ freq = CLOCK_GetUsbPllOutFreq();
+ break;
+ case 3U:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+ case 4U:
+ freq = CLOCK_GetAudioPllOutFreq();
+ break;
+ case 7U:
+ freq = 0U;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((SYSCON->SPIFICLKDIV & 0xffU) + 1U);
+}
+
+/* Get ADC Clk */
+/*! brief Return Frequency of Adc Clock
+ * return Frequency of Adc Clock.
+ */
+uint32_t CLOCK_GetAdcClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->ADCCLKSEL)
+ {
+ case 0U:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+ case 2U:
+ freq = CLOCK_GetUsbPllOutFreq();
+ break;
+ case 3U:
+ freq = CLOCK_GetAudioPllOutFreq();
+ break;
+ case 7U:
+ freq = 0U;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((SYSCON->ADCCLKDIV & 0xffU) + 1U);
+}
+
+/* Get USB0 Clk */
+/*! brief Return Frequency of Usb0 Clock
+ * return Frequency of Usb0 Clock.
+ */
+uint32_t CLOCK_GetUsb0ClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->USB0CLKSEL)
+ {
+ case 0U:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+ case 2U:
+ freq = CLOCK_GetUsbPllOutFreq();
+ break;
+ case 7U:
+ freq = 0U;
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U);
+}
+
+/* Get USB1 Clk */
+/*! brief Return Frequency of Usb1 Clock
+ * return Frequency of Usb1 Clock.
+ */
+uint32_t CLOCK_GetUsb1ClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->USB1CLKSEL)
+ {
+ case 0U:
+ freq = CLOCK_GetCoreSysClkFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+ case 2U:
+ freq = CLOCK_GetUsbPllOutFreq();
+ break;
+ case 7U:
+ freq = 0U;
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((SYSCON->USB1CLKDIV & 0xffU) + 1U);
+}
+
+/* Get MCLK Clk */
+/*! brief Return Frequency of MClk Clock
+ * return Frequency of MClk Clock.
+ */
+uint32_t CLOCK_GetMclkClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->MCLKCLKSEL)
+ {
+ case 0U:
+ freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffu) + 1U);
+ break;
+ case 1U:
+ freq = CLOCK_GetAudioPllOutFreq();
+ break;
+ case 7U:
+ freq = 0U;
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U);
+}
+
+/* Get SCTIMER Clk */
+/*! brief Return Frequency of SCTimer Clock
+ * return Frequency of SCTimer Clock.
+ */
+uint32_t CLOCK_GetSctClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->SCTCLKSEL)
+ {
+ case 0U:
+ freq = CLOCK_GetCoreSysClkFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+ case 2U:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+ case 3U:
+ freq = CLOCK_GetAudioPllOutFreq();
+ break;
+ case 7U:
+ freq = 0U;
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U);
+}
+
+/* Get SDIO Clk */
+/*! brief Return Frequency of SDIO Clock
+ * return Frequency of SDIO Clock.
+ */
+uint32_t CLOCK_GetSdioClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->SDIOCLKSEL)
+ {
+ case 0U:
+ freq = CLOCK_GetCoreSysClkFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+ case 2U:
+ freq = CLOCK_GetUsbPllOutFreq();
+ break;
+ case 3U:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+ case 4U:
+ freq = CLOCK_GetAudioPllOutFreq();
+ break;
+ case 7U:
+ freq = 0U;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U);
+}
+
+/* Get LCD Clk */
+/*! brief Return Frequency of LCD Clock
+ * return Frequency of LCD Clock.
+ */
+uint32_t CLOCK_GetLcdClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->LCDCLKSEL)
+ {
+ case 0U:
+ freq = CLOCK_GetCoreSysClkFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetLcdClkIn();
+ break;
+ case 2U:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+ case 3U:
+ freq = 0U;
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((SYSCON->LCDCLKDIV & 0xffU) + 1U);
+}
+
+/* Get LCD CLK IN Clk */
+/*! brief Return Frequency of LCD CLKIN Clock
+ * return Frequency of LCD CLKIN Clock.
+ */
+uint32_t CLOCK_GetLcdClkIn(void)
+{
+ return g_Lcd_Clk_In_Freq;
+}
+
+/* Get FRO 12M Clk */
+/*! brief Return Frequency of FRO 12MHz
+ * return Frequency of FRO 12MHz
+ */
+uint32_t CLOCK_GetFro12MFreq(void)
+{
+ return ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) != 0UL) ? 0U : 12000000U;
+}
+
+/* Get EXT OSC Clk */
+/*! brief Return Frequency of External Clock
+ * return Frequency of External Clock. If no external clock is used returns 0.
+ */
+uint32_t CLOCK_GetExtClkFreq(void)
+{
+ return g_Ext_Clk_Freq;
+}
+
+/* Get WATCH DOG Clk */
+/*! brief Return Frequency of Watchdog Oscillator
+ * return Frequency of Watchdog Oscillator
+ */
+uint32_t CLOCK_GetWdtOscFreq(void)
+{
+ uint8_t freq_sel, div_sel;
+ if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) != 0UL)
+ {
+ return 0U;
+ }
+ else
+ {
+ div_sel = (uint8_t)(((SYSCON->WDTOSCCTRL & 0x1fU) + 1U) << 1U);
+ freq_sel =
+ wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+ return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel);
+ }
+}
+
+/* Get HF FRO Clk */
+/*! brief Return Frequency of High-Freq output of FRO
+ * return Frequency of High-Freq output of FRO
+ */
+uint32_t CLOCK_GetFroHfFreq(void)
+{
+ if (((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) != 0UL) ||
+ (0UL == (SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK)))
+ {
+ return 0U;
+ }
+
+ if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) != 0UL)
+ {
+ return 96000000U;
+ }
+ else
+ {
+ return 48000000U;
+ }
+}
+
+/* Get SYSTEM PLL Clk */
+/*! brief Return Frequency of PLL
+ * return Frequency of PLL
+ */
+uint32_t CLOCK_GetPllOutFreq(void)
+{
+ return s_Pll_Freq;
+}
+
+/* Get AUDIO PLL Clk */
+/*! brief Return Frequency of AUDIO PLL
+ * return Frequency of PLL
+ */
+uint32_t CLOCK_GetAudioPllOutFreq(void)
+{
+ return s_Audio_Pll_Freq;
+}
+
+/* Get USB PLL Clk */
+/*! brief Return Frequency of USB PLL
+ * return Frequency of PLL
+ */
+uint32_t CLOCK_GetUsbPllOutFreq(void)
+{
+ return s_Usb_Pll_Freq;
+}
+
+/* Get RTC OSC Clk */
+/*! brief Return Frequency of 32kHz osc
+ * return Frequency of 32kHz osc
+ */
+uint32_t CLOCK_GetOsc32KFreq(void)
+{
+ return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */
+}
+
+/* Get MAIN Clk */
+/*! brief Return Frequency of Core System
+ * return Frequency of Core System
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->MAINCLKSELB)
+ {
+ case 0U:
+ if (SYSCON->MAINCLKSELA == 0U)
+ {
+ freq = CLOCK_GetFro12MFreq();
+ }
+ else if (SYSCON->MAINCLKSELA == 1U)
+ {
+ freq = CLOCK_GetExtClkFreq();
+ }
+ else if (SYSCON->MAINCLKSELA == 2U)
+ {
+ freq = CLOCK_GetWdtOscFreq();
+ }
+ else if (SYSCON->MAINCLKSELA == 3U)
+ {
+ freq = CLOCK_GetFroHfFreq();
+ }
+ else
+ {
+ /* Add comment to prevent the case of rule 15.7. */
+ }
+ break;
+ case 2U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+
+ case 3U:
+ freq = CLOCK_GetOsc32KFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/* Get I2S MCLK Clk */
+/*! brief Return Frequency of I2S MCLK Clock
+ * return Frequency of I2S MCLK Clock
+ */
+uint32_t CLOCK_GetI2SMClkFreq(void)
+{
+ return g_I2S_Mclk_Freq;
+}
+
+/* Get ASYNC APB Clk */
+/*! brief Return Frequency of Asynchronous APB Clock
+ * return Frequency of Asynchronous APB Clock Clock
+ */
+uint32_t CLOCK_GetAsyncApbClkFreq(void)
+{
+ async_clock_src_t clkSrc;
+ uint32_t clkRate;
+
+ clkSrc = CLOCK_GetAsyncApbClkSrc();
+
+ switch (clkSrc)
+ {
+ case kCLOCK_AsyncMainClk:
+ clkRate = CLOCK_GetCoreSysClkFreq();
+ break;
+ case kCLOCK_AsyncFro12Mhz:
+ clkRate = CLK_FRO_12MHZ;
+ break;
+ default:
+ clkRate = 0U;
+ break;
+ }
+
+ return clkRate;
+}
+
+/* Get MCAN Clk */
+/*! brief Return Frequency of MCAN Clock
+ * param MCanSel : 0U: MCAN0; 1U: MCAN1
+ * return Frequency of MCAN Clock
+ */
+uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel)
+{
+ uint32_t freq = 0U;
+ switch (MCanSel)
+ {
+ case 0U:
+ freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN0CLKDIV & 0xffU) + 1U);
+ break;
+ case 1U:
+ freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN1CLKDIV & 0xffU) + 1U);
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/* Get FLEXCOMM Clk */
+/*! brief Return Frequency of Flexcomm functional Clock
+ * return Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
+{
+ uint32_t freq = 0U;
+
+ if (id != 10U)
+ {
+ switch (SYSCON->FCLKSEL[id])
+ {
+ case 0U:
+ freq = CLOCK_GetFro12MFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffu) + 1U);
+ break;
+ case 2U:
+ freq = CLOCK_GetAudioPllOutFreq();
+ break;
+ case 3U:
+ freq = CLOCK_GetI2SMClkFreq();
+ break;
+ case 4U:
+ freq = CLOCK_GetFrgClkFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+ }
+ else
+ {
+ switch (SYSCON->FCLKSEL10)
+ {
+ case 0U:
+ freq = CLOCK_GetCoreSysClkFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+ case 2U:
+ freq = CLOCK_GetUsbPllOutFreq();
+ break;
+ case 3U:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+ case 4U:
+ freq = CLOCK_GetAudioPllOutFreq();
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+ }
+
+ return freq;
+}
+
+/* Get FRG Clk */
+uint32_t CLOCK_GetFRGInputClock(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->FRGCLKSEL)
+ {
+ case 0U:
+ freq = CLOCK_GetCoreSysClkFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+ case 2U:
+ freq = CLOCK_GetFro12MFreq();
+ break;
+ case 3U:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/* Get FRG Clk */
+/*! brief Return Frequency of frg
+ * return Frequency of FRG
+ */
+uint32_t CLOCK_GetFrgClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ if ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK)
+ {
+ freq = (uint32_t)(((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1U)) /
+ ((SYSCON_FRGCTRL_DIV_MASK + 1U) +
+ ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)));
+ }
+ else
+ {
+ freq = 0U;
+ }
+
+ return freq;
+}
+
+/* Get FRG Clk */
+/*! brief Return Frequency of dmic
+ * return Frequency of DMIC
+ */
+uint32_t CLOCK_GetDmicClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (SYSCON->DMICCLKSEL)
+ {
+ case 0U:
+ freq = CLOCK_GetFro12MFreq();
+ break;
+ case 1U:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+ case 2U:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+ case 3U:
+ freq = CLOCK_GetI2SMClkFreq();
+ break;
+ case 4U:
+ freq = CLOCK_GetCoreSysClkFreq();
+ break;
+ case 5U:
+ freq = CLOCK_GetWdtOscFreq();
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);
+ ;
+}
+
+/* Set FRG Clk */
+uint32_t CLOCK_SetFRGClock(uint32_t freq)
+{
+ assert(0UL != freq);
+
+ uint32_t input = CLOCK_GetFRGInputClock();
+ uint32_t mul;
+
+ if ((freq > 48000000U) || (freq > input) || (input / freq >= 2U))
+ {
+ /* FRG output frequency should be less than equal to 48MHz */
+ return 0U;
+ }
+ else
+ {
+ mul = (uint32_t)((((uint64_t)input - freq) * 256U) / ((uint64_t)freq));
+ SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK;
+ return 1U;
+ }
+}
+
+/* Set IP Clk */
+/*! brief Return Frequency of selected clock
+ * return Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+ uint32_t freq;
+ switch (clockName)
+ {
+ case kCLOCK_CoreSysClk:
+ freq = CLOCK_GetCoreSysClkFreq();
+ break;
+ case kCLOCK_BusClk:
+ freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
+ break;
+ case kCLOCK_ClockOut:
+ freq = CLOCK_GetClockOutClkFreq();
+ break;
+ case kCLOCK_Mclk:
+ freq = CLOCK_GetMclkClkFreq();
+ break;
+ case kCLOCK_FroHf:
+ freq = CLOCK_GetFroHfFreq();
+ break;
+ case kCLOCK_Fro12M:
+ freq = CLOCK_GetFro12MFreq();
+ break;
+ case kCLOCK_ExtClk:
+ freq = CLOCK_GetExtClkFreq();
+ break;
+ case kCLOCK_PllOut:
+ freq = CLOCK_GetPllOutFreq();
+ break;
+ case kCLOCK_WdtOsc:
+ freq = CLOCK_GetWdtOscFreq();
+ break;
+ case kCLOCK_Frg:
+ freq = CLOCK_GetFrgClkFreq();
+ break;
+
+ case kCLOCK_AsyncApbClk:
+ freq = CLOCK_GetAsyncApbClkFreq();
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */
+static uint32_t pllEncodeN(uint32_t N)
+{
+ uint32_t x, i;
+
+ /* Find NDec */
+ switch (N)
+ {
+ case 0U:
+ x = 0x3FFU;
+ break;
+
+ case 1U:
+ x = 0x302U;
+ break;
+
+ case 2U:
+ x = 0x202U;
+ break;
+
+ default:
+ x = 0x080U;
+ for (i = N; i <= NVALMAX; i++)
+ {
+ x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
+ }
+ break;
+ }
+
+ return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P);
+}
+
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+ uint32_t n, x, i;
+
+ /* Find NDec */
+ switch (NDEC)
+ {
+ case 0x3FFU:
+ n = 0U;
+ break;
+
+ case 0x302U:
+ n = 1U;
+ break;
+
+ case 0x202U:
+ n = 2U;
+ break;
+
+ default:
+ x = 0x080U;
+ n = 0xFFFFFFFFU;
+ for (i = NVALMAX; i >= 3U; i--)
+ {
+ x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
+ if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+ {
+ /* Decoded value of NDEC */
+ n = i;
+ break;
+ }
+ }
+ break;
+ }
+
+ return n;
+}
+
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */
+static uint32_t pllEncodeP(uint32_t P)
+{
+ uint32_t x, i;
+
+ /* Find PDec */
+ switch (P)
+ {
+ case 0U:
+ x = 0x7FU;
+ break;
+
+ case 1U:
+ x = 0x62U;
+ break;
+
+ case 2U:
+ x = 0x42U;
+ break;
+
+ default:
+ x = 0x10U;
+ for (i = P; i <= PVALMAX; i++)
+ {
+ x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
+ }
+ break;
+ }
+
+ return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+ uint32_t p, x, i;
+
+ /* Find PDec */
+ switch (PDEC)
+ {
+ case 0x7FU:
+ p = 0U;
+ break;
+
+ case 0x62U:
+ p = 1U;
+ break;
+
+ case 0x42U:
+ p = 2U;
+ break;
+
+ default:
+ x = 0x10U;
+ p = 0xFFFFFFFFU;
+ for (i = PVALMAX; i >= 3U; i--)
+ {
+ x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
+ if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+ {
+ /* Decoded value of PDEC */
+ p = i;
+ break;
+ }
+ }
+ break;
+ }
+
+ return p;
+}
+
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */
+static uint32_t pllEncodeM(uint32_t M)
+{
+ uint32_t i, x;
+
+ /* Find MDec */
+ switch (M)
+ {
+ case 0U:
+ x = 0x1FFFFU;
+ break;
+
+ case 1U:
+ x = 0x18003U;
+ break;
+
+ case 2U:
+ x = 0x10003U;
+ break;
+
+ default:
+ x = 0x04000U;
+ for (i = M; i <= MVALMAX; i++)
+ {
+ x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);
+ }
+ break;
+ }
+
+ return x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P);
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+ uint32_t m, i, x;
+
+ /* Find MDec */
+ switch (MDEC)
+ {
+ case 0x1FFFFU:
+ m = 0U;
+ break;
+
+ case 0x18003U:
+ m = 1U;
+ break;
+
+ case 0x10003U:
+ m = 2U;
+ break;
+
+ default:
+ x = 0x04000U;
+ m = 0xFFFFFFFFU;
+ for (i = MVALMAX; i >= 3U; i--)
+ {
+ x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);
+ if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
+ {
+ /* Decoded value of MDEC */
+ m = i;
+ break;
+ }
+ }
+ break;
+ }
+
+ return m;
+}
+
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)
+{
+ /* bandwidth: compute selP from Multiplier */
+ if (M < 60U)
+ {
+ *pSelP = (M >> 1U) + 1U;
+ }
+ else
+ {
+ *pSelP = PVALMAX - 1U;
+ }
+
+ /* bandwidth: compute selI from Multiplier */
+ if (M > 16384U)
+ {
+ *pSelI = 1U;
+ }
+ else if (M > 8192U)
+ {
+ *pSelI = 2U;
+ }
+ else if (M > 2048U)
+ {
+ *pSelI = 4U;
+ }
+ else if (M >= 501U)
+ {
+ *pSelI = 8U;
+ }
+ else if (M >= 60U)
+ {
+ *pSelI = 4U * (1024U / (M + 9U));
+ }
+ else
+ {
+ *pSelI = (M & 0x3CU) + 4U;
+ }
+
+ if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT))
+ {
+ *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT);
+ }
+
+ *pSelR = 0U;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+ uint32_t preDiv = 1;
+
+ /* Direct input is not used? */
+ if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U)
+ {
+ /* Decode NDEC value to get (N) pre divider */
+ preDiv = pllDecodeN(nDecReg & 0x3FFU);
+ if (preDiv == 0U)
+ {
+ preDiv = 1U;
+ }
+ }
+
+ /* Adjusted by 1, directi is used to bypass */
+ return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+ uint32_t postDiv = 1U;
+
+ /* Direct input is not used? */
+ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
+ {
+ /* Decode PDEC value to get (P) post divider */
+ postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
+ if (postDiv == 0U)
+ {
+ postDiv = 2U;
+ }
+ }
+
+ /* Adjusted by 1, directo is used to bypass */
+ return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+ uint32_t mMult = 1U;
+
+ /* Decode MDEC value to get (M) multiplier */
+ mMult = pllDecodeM(mDecReg & 0x1FFFFU);
+
+ if (mMult == 0U)
+ {
+ mMult = 1U;
+ }
+
+ return mMult;
+}
+
+/* Calculate the powerTimes' power of 2 */
+static uint32_t power2Cal(uint32_t powerTimes)
+{
+ uint32_t ret = 1U;
+ uint32_t i;
+ for (i = 0; i < powerTimes; i++)
+ {
+ ret *= 2U;
+ }
+
+ return ret;
+}
+
+/* Convert the binary to fractional part */
+static double Binary2Fractional(uint32_t binaryPart)
+{
+ double fractional = 0.0;
+ for (uint32_t i = 0U; i <= 14U; i++)
+ {
+ fractional += (double)(uint32_t)((binaryPart >> i) & 0x1U) / (double)(uint32_t)power2Cal(15U - i);
+ }
+ return fractional;
+}
+
+/* Find greatest common divisor between m and n */
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
+{
+ uint32_t tmp;
+
+ while (n != 0U)
+ {
+ tmp = n;
+ n = m % n;
+ m = tmp;
+ }
+
+ return m;
+}
+
+/*
+ * Set PLL output based on desired output rate.
+ * In this function, the it calculates the PLL setting for output frequency from input clock
+ * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.
+ * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.
+ */
+static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
+{
+ uint32_t nDivOutHz, fccoHz, multFccoDiv;
+ uint32_t pllPreDivider, pllMultiplier, pllPostDivider;
+ uint32_t pllDirectInput, pllDirectOutput;
+ uint32_t pllSelP, pllSelI, pllSelR, uplimoff;
+
+ /* Baseline parameters (no input or output dividers) */
+ pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */
+ pllPostDivider = 0U; /* 0 implies post-divider will be disabled */
+ pllDirectOutput = 1U;
+ multFccoDiv = 2U;
+
+ /* Verify output rate parameter */
+ if (foutHz > PLL_MAX_CCO_FREQ_MHZ)
+ {
+ /* Maximum PLL output with post divider=1 cannot go above this frequency */
+ return kStatus_PLL_OutputTooHigh;
+ }
+ if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U)))
+ {
+ /* Minmum PLL output with maximum post divider cannot go below this frequency */
+ return kStatus_PLL_OutputTooLow;
+ }
+
+ /* Verify input rate parameter */
+ if (finHz < PLL_LOWER_IN_LIMIT)
+ {
+ /* Input clock into the PLL cannot be lower than this */
+ return kStatus_PLL_InputTooLow;
+ }
+
+ /* Find the optimal CCO frequency for the output and input that
+ will keep it inside the PLL CCO range. This may require
+ tweaking the post-divider for the PLL. */
+ fccoHz = foutHz;
+ while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)
+ {
+ /* CCO output is less than minimum CCO range, so the CCO output
+ needs to be bumped up and the post-divider is used to bring
+ the PLL output back down. */
+ pllPostDivider++;
+ if (pllPostDivider > PVALMAX)
+ {
+ return kStatus_PLL_OutsideIntLimit;
+ }
+
+ /* Target CCO goes up, PLL output goes down */
+ fccoHz = foutHz * (pllPostDivider * 2U);
+ pllDirectOutput = 0U;
+ }
+
+ /* Determine if a pre-divider is needed to get the best frequency */
+ if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz))
+ {
+ uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz));
+
+ if (a > 20000U)
+ {
+ a = (multFccoDiv * finHz) / a;
+ if ((a != 0U) && (a < PLL_MAX_N_DIV))
+ {
+ pllPreDivider = a;
+ }
+ }
+ }
+
+ /* Bypass pre-divider hardware if pre-divider is 1 */
+ if (pllPreDivider > 1U)
+ {
+ pllDirectInput = 0U;
+ }
+ else
+ {
+ pllDirectInput = 1U;
+ }
+
+ /* Determine PLL multipler */
+ nDivOutHz = (finHz / pllPreDivider);
+ pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv;
+
+ /* Find optimal values for filter */
+ /* Will bumping up M by 1 get us closer to the desired CCO frequency? */
+ if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U))
+ {
+ pllMultiplier++;
+ }
+
+ /* Setup filtering */
+ pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR);
+ uplimoff = 0U;
+
+ /* Get encoded value for M (mult) and use manual filter, disable SS mode */
+ pSetup->pllmdec = PLL_MDEC_VAL_SET(pllEncodeM(pllMultiplier));
+
+ /* Get encoded values for N (prediv) and P (postdiv) */
+ pSetup->pllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider));
+ pSetup->pllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider));
+
+ /* PLL control */
+ pSetup->pllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) | /* Filter coefficient */
+ (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) | /* Filter coefficient */
+ (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) | /* Filter coefficient */
+ (0UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) | /* PLL bypass mode disabled */
+ (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) | /* SS/fractional mode disabled */
+ (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */
+ (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */
+
+ return kStatus_PLL_Success;
+}
+
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+/* Alloct the static buffer for cache. */
+static pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];
+static uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
+static uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
+static uint32_t gPllSetupCacheIdx = 0U;
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+/*
+ * Calculate the PLL setting values from input clock freq to output freq.
+ */
+static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
+{
+ pll_error_t retErr;
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+ uint32_t i;
+
+ for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++)
+ {
+ if ((finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]))
+ {
+ /* Hit the target in cache buffer. */
+ pSetup->pllctrl = gPllSetupCacheStruct[i].pllctrl;
+ pSetup->pllndec = gPllSetupCacheStruct[i].pllndec;
+ pSetup->pllpdec = gPllSetupCacheStruct[i].pllpdec;
+ pSetup->pllmdec = gPllSetupCacheStruct[i].pllmdec;
+ retErr = kStatus_PLL_Success;
+ break;
+ }
+ }
+
+ if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+ {
+ return retErr;
+ }
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+ /* No cache or did not hit the cache. */
+ retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup);
+
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+ if (kStatus_PLL_Success == retErr)
+ {
+ /* Cache the most recent calulation result into buffer. */
+ gFinHzCache[gPllSetupCacheIdx] = finHz;
+ gFoutHzCache[gPllSetupCacheIdx] = foutHz;
+
+ gPllSetupCacheStruct[gPllSetupCacheIdx].pllctrl = pSetup->pllctrl;
+ gPllSetupCacheStruct[gPllSetupCacheIdx].pllndec = pSetup->pllndec;
+ gPllSetupCacheStruct[gPllSetupCacheIdx].pllpdec = pSetup->pllpdec;
+ gPllSetupCacheStruct[gPllSetupCacheIdx].pllmdec = pSetup->pllmdec;
+ /* Update the index for next available buffer. */
+ gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT;
+ }
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+ return retErr;
+}
+
+/* Update SYSTEM PLL rate variable */
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)
+{
+ s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup);
+}
+
+/* Update AUDIO PLL rate variable */
+static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup)
+{
+ s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromSetup(pSetup);
+}
+
+/* Update AUDIO Fractional PLL rate variable */
+static void CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pll_setup_t *pSetup)
+{
+ s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromFractSetup(pSetup);
+}
+
+/* Update USB PLL rate variable */
+static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup)
+{
+ s_Usb_Pll_Freq = CLOCK_GetUsbPLLOutFromSetup(pSetup);
+}
+
+/* Return System PLL input clock rate */
+/*! brief Return System PLL input clock rate
+ * return System PLL input clock rate
+ */
+uint32_t CLOCK_GetSystemPLLInClockRate(void)
+{
+ uint32_t clkRate = 0U;
+
+ switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK))
+ {
+ case 0x00U:
+ clkRate = CLK_FRO_12MHZ;
+ break;
+
+ case 0x01U:
+ clkRate = CLOCK_GetExtClkFreq();
+ break;
+
+ case 0x02U:
+ clkRate = CLOCK_GetWdtOscFreq();
+ break;
+
+ case 0x03U:
+ clkRate = CLOCK_GetOsc32KFreq();
+ break;
+
+ default:
+ clkRate = 0U;
+ break;
+ }
+
+ return clkRate;
+}
+
+/* Return Audio PLL input clock rate */
+/*! brief Return Audio PLL input clock rate
+ * return Audio PLL input clock rate
+ */
+uint32_t CLOCK_GetAudioPLLInClockRate(void)
+{
+ uint32_t clkRate = 0U;
+
+ switch ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK))
+ {
+ case 0x00U:
+ clkRate = CLK_FRO_12MHZ;
+ break;
+
+ case 0x01U:
+ clkRate = CLOCK_GetExtClkFreq();
+ break;
+
+ default:
+ clkRate = 0U;
+ break;
+ }
+
+ return clkRate;
+}
+
+/* Return System PLL output clock rate from setup structure */
+/*! brief Return System PLL output clock rate from setup structure
+ * param pSetup : Pointer to a PLL setup structure
+ * return System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup)
+{
+ uint32_t prediv, postdiv, mMult, inPllRate;
+ uint64_t workRate;
+
+ inPllRate = CLOCK_GetSystemPLLInClockRate();
+ /* If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock*/
+ if ((pSetup->pllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U)
+ {
+ /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+ /*
+ * 1. Pre-divider
+ * Pre-divider is only available when the DIRECTI is disabled.
+ */
+ if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK))
+ {
+ prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+ }
+ else
+ {
+ prediv = 1U; /* The pre-divider is bypassed. */
+ }
+ /*
+ * 2. Post-divider
+ * Post-divider is only available when the DIRECTO is disabled.
+ */
+ if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK))
+ {
+ postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+ }
+ else
+ {
+ postdiv = 1U; /* The post-divider is bypassed. */
+ }
+ /* Adjust input clock */
+ inPllRate = inPllRate / prediv;
+
+ /* MDEC used for rate */
+ mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);
+ workRate = (uint64_t)inPllRate * (uint64_t)mMult;
+
+ workRate = workRate / ((uint64_t)postdiv);
+ workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+ }
+ else
+ {
+ /* In bypass mode */
+ workRate = (uint64_t)inPllRate;
+ }
+
+ return (uint32_t)workRate;
+}
+
+/* Return Usb PLL output clock rate from setup structure */
+/*! brief Return System USB PLL output clock rate from setup structure
+ * param pSetup : Pointer to a PLL setup structure
+ * return System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup)
+{
+ uint32_t nsel, psel, msel, inPllRate;
+ uint64_t workRate;
+ inPllRate = CLOCK_GetExtClkFreq();
+ msel = pSetup->msel;
+ psel = pSetup->psel;
+ nsel = pSetup->nsel;
+
+ /* Make sure the PSEL is correct. */
+ if (0U == SWITCH_USB_PSEL(psel))
+ {
+ return 0UL;
+ }
+
+ if (pSetup->fbsel)
+ {
+ /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */
+ workRate = ((uint64_t)inPllRate) * ((uint64_t)msel + 1U) / ((uint64_t)nsel + 1U);
+ }
+ else
+ {
+ /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */
+ workRate = ((uint64_t)inPllRate / ((uint64_t)nsel + 1U)) * (msel + 1U) / (2U * SWITCH_USB_PSEL(psel));
+ }
+
+ return (uint32_t)workRate;
+}
+
+/* Return Audio PLL output clock rate from setup structure */
+/*! brief Return System AUDIO PLL output clock rate from setup structure
+ * param pSetup : Pointer to a PLL setup structure
+ * return System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup)
+{
+ uint32_t prediv, postdiv, mMult, inPllRate;
+ uint64_t workRate;
+
+ inPllRate = CLOCK_GetAudioPLLInClockRate();
+ if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)
+ {
+ /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+ /*
+ * 1. Pre-divider
+ * Pre-divider is only available when the DIRECTI is disabled.
+ */
+ if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK))
+ {
+ prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+ }
+ else
+ {
+ prediv = 1U; /* The pre-divider is bypassed. */
+ }
+ /*
+ * 2. Post-divider
+ * Post-divider is only available when the DIRECTO is disabled.
+ */
+ if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK))
+ {
+ postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+ }
+ else
+ {
+ postdiv = 1U; /* The post-divider is bypassed. */
+ }
+ /* Adjust input clock */
+ inPllRate = inPllRate / prediv;
+
+ /* MDEC used for rate */
+ mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);
+ workRate = (uint64_t)inPllRate * (uint64_t)mMult;
+
+ workRate = workRate / ((uint64_t)postdiv);
+ workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+ }
+ else
+ {
+ /* In bypass mode */
+ workRate = (uint64_t)inPllRate;
+ }
+
+ return (uint32_t)workRate;
+}
+
+/* Return Audio PLL output clock rate from audio fractioanl setup structure */
+/*! brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure
+ * param pSetup : Pointer to a PLL setup structure
+ * return System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup)
+{
+ uint32_t prediv, postdiv, inPllRate;
+ double workRate, mMultFactional;
+
+ inPllRate = CLOCK_GetAudioPLLInClockRate();
+ if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)
+ {
+ /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+ /*
+ * 1. Pre-divider
+ * Pre-divider is only available when the DIRECTI is disabled.
+ */
+ if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK))
+ {
+ prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+ }
+ else
+ {
+ prediv = 1U; /* The pre-divider is bypassed. */
+ }
+ /*
+ * 2. Post-divider
+ * Post-divider is only available when the DIRECTO is disabled.
+ */
+ if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK))
+ {
+ postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+ }
+ else
+ {
+ postdiv = 1U; /* The post-divider is bypassed. */
+ }
+ /* Adjust input clock */
+ inPllRate = inPllRate / prediv;
+
+ mMultFactional = (double)(uint32_t)(pSetup->audpllfrac >> 15) +
+ (double)(uint32_t)Binary2Fractional(pSetup->audpllfrac & 0x7FFFU);
+ workRate = (double)inPllRate * (double)mMultFactional;
+
+ workRate = workRate / ((double)postdiv);
+ workRate = workRate * 2.0; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+ }
+ else
+ {
+ /* In bypass mode */
+ workRate = (double)(uint64_t)inPllRate;
+ }
+
+ return (uint32_t)workRate;
+}
+
+/* Set the current PLL Rate */
+/*! brief Store the current PLL rate
+ * param rate: Current rate of the PLL
+ * return Nothing
+ **/
+void CLOCK_SetStoredPLLClockRate(uint32_t rate)
+{
+ s_Pll_Freq = rate;
+}
+
+/* Set the current Audio PLL Rate */
+/*! brief Store the current AUDIO PLL rate
+ * param rate: Current rate of the PLL
+ * return Nothing
+ **/
+void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate)
+{
+ s_Audio_Pll_Freq = rate;
+}
+
+/* Set the current Usb PLL Rate */
+void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate)
+{
+ s_Usb_Pll_Freq = rate;
+}
+
+/* Return System PLL output clock rate */
+/*! brief Return System PLL output clock rate
+ * param recompute : Forces a PLL rate recomputation if true
+ * return System PLL output clock rate
+ * note The PLL rate is cached in the driver in a variable as
+ * the rate computation function can take some time to perform. It
+ * is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute)
+{
+ pll_setup_t Setup;
+ uint32_t rate;
+
+ if ((recompute) || (s_Pll_Freq == 0U))
+ {
+ Setup.pllctrl = SYSCON->SYSPLLCTRL;
+ Setup.pllndec = SYSCON->SYSPLLNDEC;
+ Setup.pllpdec = SYSCON->SYSPLLPDEC;
+ Setup.pllmdec = SYSCON->SYSPLLMDEC;
+
+ CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup);
+ }
+
+ rate = s_Pll_Freq;
+
+ return rate;
+}
+
+/* Return AUDIO PLL output clock rate */
+/*! brief Return System AUDIO PLL output clock rate
+ * param recompute : Forces a AUDIO PLL rate recomputation if true
+ * return System AUDIO PLL output clock rate
+ * note The AUDIO PLL rate is cached in the driver in a variable as
+ * the rate computation function can take some time to perform. It
+ * is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute)
+{
+ pll_setup_t Setup;
+ uint32_t rate;
+
+ if ((recompute) || (s_Audio_Pll_Freq == 0U))
+ {
+ Setup.pllctrl = SYSCON->AUDPLLCTRL;
+ Setup.pllndec = SYSCON->AUDPLLNDEC;
+ Setup.pllpdec = SYSCON->AUDPLLPDEC;
+ Setup.pllmdec = SYSCON->AUDPLLMDEC;
+
+ CLOCK_GetAudioPLLOutFromSetupUpdate(&Setup);
+ }
+
+ rate = s_Audio_Pll_Freq;
+ return rate;
+}
+
+/* Return USB PLL output clock rate */
+uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute)
+{
+ usb_pll_setup_t Setup;
+ uint32_t rate;
+
+ if ((recompute) || (s_Usb_Pll_Freq == 0U))
+ {
+ Setup.msel = (uint8_t)((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_MSEL_SHIFT) & SYSCON_USBPLLCTRL_MSEL_MASK);
+ Setup.psel = (uint8_t)((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_PSEL_SHIFT) & SYSCON_USBPLLCTRL_PSEL_MASK);
+ Setup.nsel = (uint8_t)((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_NSEL_SHIFT) & SYSCON_USBPLLCTRL_NSEL_MASK);
+ Setup.fbsel = (((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_FBSEL_SHIFT) & SYSCON_USBPLLCTRL_FBSEL_MASK) != 0UL);
+ Setup.bypass =
+ (((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_BYPASS_SHIFT) & SYSCON_USBPLLCTRL_BYPASS_MASK) != 0UL);
+ Setup.direct =
+ (((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_DIRECT_SHIFT) & SYSCON_USBPLLCTRL_DIRECT_MASK) != 0UL);
+ CLOCK_GetUsbPLLOutFromSetupUpdate(&Setup);
+ }
+
+ rate = s_Usb_Pll_Freq;
+ return rate;
+}
+
+/* Set PLL output based on the passed PLL setup data */
+/*! brief Set PLL output based on the passed PLL setup data
+ * param pControl : Pointer to populated PLL control structure to generate setup with
+ * param pSetup : Pointer to PLL setup structure to be filled
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * note Actual frequency for setup may vary from the desired frequency based on the
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
+{
+ uint32_t inRate;
+ pll_error_t pllError;
+
+ /* Determine input rate for the PLL */
+ if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
+ {
+ inRate = pControl->inputRate;
+ }
+ else
+ {
+ inRate = CLOCK_GetSystemPLLInClockRate();
+ }
+
+ /* PLL flag options */
+ pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
+ pSetup->pllRate = pControl->desiredRate;
+ return pllError;
+}
+
+/* Set PLL output from PLL setup structure */
+/*! brief Set PLL output from PLL setup structure (precise frequency)
+ * param pSetup : Pointer to populated PLL setup structure
+ * param flagcfg : Flag configuration for PLL config structure
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+ if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
+ {
+ /* Turn on the ext clock if system pll input select clk_in */
+ CLOCK_Enable_SysOsc(true);
+ }
+ /* Enable power for PLLs */
+ POWER_SetPLL();
+ /* Power off PLL during setup changes */
+ POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+ pSetup->flags = flagcfg;
+
+ /* Write PLL setup data */
+ SYSCON->SYSPLLCTRL = pSetup->pllctrl;
+ SYSCON->SYSPLLNDEC = pSetup->pllndec;
+ SYSCON->SYSPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+ SYSCON->SYSPLLPDEC = pSetup->pllpdec;
+ SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+ SYSCON->SYSPLLMDEC = pSetup->pllmdec;
+ SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+
+ /* Flags for lock or power on */
+ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+ {
+ /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+ uint32_t maxCCO = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+ uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);
+
+ /* Initialize and power up PLL */
+ SYSCON->SYSPLLMDEC = maxCCO;
+ POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+ /* Set mreq to activate */
+ SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);
+
+ /* Delay for 72 uSec @ 12Mhz */
+ SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+ /* clear mreq to prepare for restoring mreq */
+ SYSCON->SYSPLLMDEC = curSSCTRL;
+
+ /* set original value back and activate */
+ SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);
+
+ /* Enable peripheral states by setting low */
+ POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+ }
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+ {
+ while (CLOCK_IsSystemPLLLocked() == false)
+ {
+ }
+ }
+
+ /* Update current programmed PLL rate var */
+ CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup);
+
+ /* System voltage adjustment, occurs prior to setting main system clock */
+ if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U)
+ {
+ POWER_SetVoltageForFreq(s_Pll_Freq);
+ }
+
+ return kStatus_PLL_Success;
+}
+
+/* Set AUDIO PLL output from AUDIO PLL setup structure */
+/*! brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
+ * param pSetup : Pointer to populated PLL setup structure
+ * param flagcfg : Flag configuration for PLL config structure
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+ if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+ {
+ /* Turn on the ext clock if system pll input select clk_in */
+ CLOCK_Enable_SysOsc(true);
+ }
+ /* Enable power VD3 for PLLs */
+ POWER_SetPLL();
+ /* Power off PLL during setup changes */
+ POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+ pSetup->flags = flagcfg;
+
+ /* Write PLL setup data */
+ SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+ SYSCON->AUDPLLNDEC = pSetup->pllndec;
+ SYSCON->AUDPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+ SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */
+
+ /* Flags for lock or power on */
+ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+ {
+ /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+ uint32_t maxCCO = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+ uint32_t curSSCTRL = SYSCON->AUDPLLMDEC & ~(1UL << 17U);
+
+ /* Initialize and power up PLL */
+ SYSCON->AUDPLLMDEC = maxCCO;
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+ /* Set mreq to activate */
+ SYSCON->AUDPLLMDEC = maxCCO | (1UL << 17U);
+
+ /* Delay for 72 uSec @ 12Mhz */
+ SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+ /* clear mreq to prepare for restoring mreq */
+ SYSCON->AUDPLLMDEC = curSSCTRL;
+
+ /* set original value back and activate */
+ SYSCON->AUDPLLMDEC = curSSCTRL | (1UL << 17U);
+
+ /* Enable peripheral states by setting low */
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+ }
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+ {
+ while (CLOCK_IsAudioPLLLocked() == false)
+ {
+ }
+ }
+
+ /* Update current programmed PLL rate var */
+ CLOCK_GetAudioPLLOutFromSetupUpdate(pSetup);
+
+ return kStatus_PLL_Success;
+}
+
+/* Set AUDIO PLL output from AUDIO PLL fractional setup structure */
+/*! brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise
+ * frequency)
+ * param pSetup : Pointer to populated PLL setup structure
+ * param flagcfg : Flag configuration for PLL config structure
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+ if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+ {
+ /* Turn on the ext clock if system pll input select clk_in */
+ CLOCK_Enable_SysOsc(true);
+ }
+ /* Enable power VD3 for PLLs */
+ POWER_SetPLL();
+ /* Power off PLL during setup changes */
+ POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+ pSetup->flags = flagcfg;
+
+ /* Write PLL setup data */
+ SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+ SYSCON->AUDPLLNDEC = pSetup->pllndec;
+ SYSCON->AUDPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+ SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(0); /* enable fractional function */
+ SYSCON->AUDPLLFRAC = pSetup->audpllfrac;
+ SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1UL << SYSCON_AUDPLLFRAC_REQ_SHIFT);
+
+ /* Enable peripheral states by setting low */
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+ {
+ while (CLOCK_IsAudioPLLLocked() == false)
+ {
+ }
+ }
+
+ /* Update current programmed PLL rate var */
+ CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pSetup);
+
+ return kStatus_PLL_Success;
+}
+
+/* Set Audio PLL output based on the passed Audio PLL setup data */
+/*! brief Set AUDIO PLL output based on the passed AUDIO PLL setup data
+ * param pControl : Pointer to populated PLL control structure to generate setup with
+ * param pSetup : Pointer to PLL setup structure to be filled
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * note Actual frequency for setup may vary from the desired frequency based on the
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
+{
+ uint32_t inRate;
+ pll_error_t pllError;
+
+ /* Determine input rate for the PLL */
+ if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
+ {
+ inRate = pControl->inputRate;
+ }
+ else
+ {
+ inRate = CLOCK_GetAudioPLLInClockRate();
+ }
+
+ /* PLL flag options */
+ pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
+ pSetup->pllRate = pControl->desiredRate;
+ return pllError;
+}
+
+/* Setup PLL Frequency from pre-calculated value */
+/**
+ * brief Set PLL output from PLL setup structure (precise frequency)
+ * param pSetup : Pointer to populated PLL setup structure
+ * return kStatus_PLL_Success on success, or PLL setup error code
+ * note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup)
+{
+ if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
+ {
+ /* Turn on the ext clock if system pll input select clk_in */
+ CLOCK_Enable_SysOsc(true);
+ }
+ /* Enable power VD3 for PLLs */
+ POWER_SetPLL();
+ /* Power off PLL during setup changes */
+ POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+ /* Write PLL setup data */
+ SYSCON->SYSPLLCTRL = pSetup->pllctrl;
+ SYSCON->SYSPLLNDEC = pSetup->pllndec;
+ SYSCON->SYSPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+ SYSCON->SYSPLLPDEC = pSetup->pllpdec;
+ SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+ SYSCON->SYSPLLMDEC = pSetup->pllmdec;
+ SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+
+ /* Flags for lock or power on */
+ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+ {
+ /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+ uint32_t maxCCO = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+ uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);
+
+ /* Initialize and power up PLL */
+ SYSCON->SYSPLLMDEC = maxCCO;
+ POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+ /* Set mreq to activate */
+ SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);
+
+ /* Delay for 72 uSec @ 12Mhz */
+ SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+ /* clear mreq to prepare for restoring mreq */
+ SYSCON->SYSPLLMDEC = curSSCTRL;
+
+ /* set original value back and activate */
+ SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);
+
+ /* Enable peripheral states by setting low */
+ POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+ }
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+ {
+ while (CLOCK_IsSystemPLLLocked() == false)
+ {
+ }
+ }
+
+ /* Update current programmed PLL rate var */
+ s_Pll_Freq = pSetup->pllRate;
+
+ return kStatus_PLL_Success;
+}
+
+/* Setup Audio PLL Frequency from pre-calculated value */
+/**
+ * brief Set Audio PLL output from Audio PLL setup structure (precise frequency)
+ * param pSetup : Pointer to populated PLL setup structure
+ * return kStatus_PLL_Success on success, or Audio PLL setup error code
+ * note This function will power off the PLL, setup the Audio PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup)
+{
+ if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+ {
+ /* Turn on the ext clock if system pll input select clk_in */
+ CLOCK_Enable_SysOsc(true);
+ }
+ /* Enable power VD3 for PLLs */
+ POWER_SetPLL();
+ /* Power off Audio PLL during setup changes */
+ POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+ /* Write Audio PLL setup data */
+ SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+ SYSCON->AUDPLLFRAC = pSetup->audpllfrac;
+ SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1UL << SYSCON_AUDPLLFRAC_REQ_SHIFT); /* latch */
+ SYSCON->AUDPLLNDEC = pSetup->pllndec;
+ SYSCON->AUDPLLNDEC = pSetup->pllndec | (1UL << SYSCON_AUDPLLNDEC_NREQ_SHIFT); /* latch */
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_AUDPLLPDEC_PREQ_SHIFT); /* latch */
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_AUDPLLMDEC_MREQ_SHIFT); /* latch */
+ SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */
+
+ /* Flags for lock or power on */
+ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+ {
+ /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+ uint32_t maxCCO = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+ uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);
+
+ /* Initialize and power up PLL */
+ SYSCON->SYSPLLMDEC = maxCCO;
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+ /* Set mreq to activate */
+ SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);
+
+ /* Delay for 72 uSec @ 12Mhz */
+ SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+ /* clear mreq to prepare for restoring mreq */
+ SYSCON->SYSPLLMDEC = curSSCTRL;
+
+ /* set original value back and activate */
+ SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);
+
+ /* Enable peripheral states by setting low */
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+ }
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+ {
+ while (CLOCK_IsAudioPLLLocked() == false)
+ {
+ }
+ }
+
+ /* Update current programmed PLL rate var */
+ s_Audio_Pll_Freq = pSetup->pllRate;
+
+ return kStatus_PLL_Success;
+}
+
+/* Setup USB PLL Frequency from pre-calculated value */
+/**
+ * brief Set USB PLL output from USB PLL setup structure (precise frequency)
+ * param pSetup : Pointer to populated USB PLL setup structure
+ * return kStatus_PLL_Success on success, or USB PLL setup error code
+ * note This function will power off the USB PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
+ * and adjust system voltages to the new USB PLL rate. The function will not
+ * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup)
+{
+ uint32_t usbpllctrl, fccoHz;
+ uint8_t msel, psel, nsel;
+ bool pllDirectInput, pllDirectOutput, pllfbsel;
+
+ msel = pSetup->msel;
+ psel = pSetup->psel;
+ nsel = pSetup->nsel;
+ pllDirectOutput = pSetup->direct;
+ pllDirectInput = pSetup->bypass;
+ pllfbsel = pSetup->fbsel;
+
+ /* Input clock into the PLL cannot be lower than this */
+ if (pSetup->inputRate < USB_PLL_LOWER_IN_LIMIT)
+ {
+ return kStatus_PLL_InputTooLow;
+ }
+
+ if (pllfbsel)
+ {
+ /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */
+ fccoHz = (pSetup->inputRate / ((uint32_t)nsel + 1U)) * 2U * (msel + 1U) * SWITCH_USB_PSEL(psel);
+
+ /* USB PLL CCO out rate cannot be lower than this */
+ if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)
+ {
+ return kStatus_PLL_CCOTooLow;
+ }
+ /* USB PLL CCO out rate cannot be Higher than this */
+ if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)
+ {
+ return kStatus_PLL_CCOTooHigh;
+ }
+ }
+ else
+ {
+ /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */
+ fccoHz = pSetup->inputRate / ((uint32_t)nsel + 1U) * (msel + 1U);
+
+ /* USB PLL CCO out rate cannot be lower than this */
+ if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)
+ {
+ return kStatus_PLL_CCOTooLow;
+ }
+ /* USB PLL CCO out rate cannot be Higher than this */
+ if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)
+ {
+ return kStatus_PLL_CCOTooHigh;
+ }
+ }
+
+ /* If configure the USB HOST clock, VD5 power for USB PHY should be enable
+ before the PLL is working */
+ /* Turn on the ext clock for usb pll input */
+ CLOCK_Enable_SysOsc(true);
+
+ /* Enable power VD3 for PLLs */
+ POWER_SetPLL();
+
+ /* Power on the VD5 for USB PHY */
+ POWER_SetUsbPhy();
+
+ /* Power off USB PLL during setup changes */
+ POWER_EnablePD(kPDRUNCFG_PD_USB_PLL);
+
+ /* Write USB PLL setup data */
+ usbpllctrl = USB_PLL_NSEL_VAL_SET(nsel) | /* NSEL VALUE */
+ USB_PLL_PSEL_VAL_SET(psel) | /* PSEL VALUE */
+ USB_PLL_MSEL_VAL_SET(msel) | /* MSEL VALUE */
+ (uint32_t)pllDirectInput << SYSCON_USBPLLCTRL_BYPASS_SHIFT | /* BYPASS DISABLE */
+ (uint32_t)pllDirectOutput << SYSCON_USBPLLCTRL_DIRECT_SHIFT | /* DIRECTO DISABLE */
+ (uint32_t)pllfbsel << SYSCON_USBPLLCTRL_FBSEL_SHIFT; /* FBSEL SELECT */
+
+ SYSCON->USBPLLCTRL = usbpllctrl;
+
+ POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+
+ /* Delay for 72 uSec @ 12Mhz for the usb pll to lock */
+ SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ if (false == pllDirectInput)
+ {
+ while (CLOCK_IsUsbPLLLocked() == false)
+ {
+ }
+ }
+ CLOCK_GetUsbPLLOutFromSetupUpdate(pSetup);
+ return kStatus_PLL_Success;
+}
+
+/* Set System PLL clock based on the input frequency and multiplier */
+/*! brief Set PLL output based on the multiplier and input frequency
+ * param multiply_by : multiplier
+ * param input_freq : Clock input frequency of the PLL
+ * return Nothing
+ * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
+ * function does not disable or enable PLL power, wait for PLL lock,
+ * or adjust system voltages. These must be done in the application.
+ * The function will not alter any source clocks (ie, main systen clock)
+ * that may use the PLL, so these should be setup prior to and after
+ * exiting the function.
+ */
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq)
+{
+ uint32_t cco_freq = input_freq * multiply_by;
+ uint32_t pdec = 1U;
+ uint32_t selr;
+ uint32_t seli;
+ uint32_t selp;
+ uint32_t mdec, ndec;
+
+ uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1);
+
+ while (cco_freq < 275000000U)
+ {
+ multiply_by <<= 1U; /* double value in each iteration */
+ pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */
+ cco_freq = input_freq * multiply_by;
+ }
+ selr = 0U;
+ if (multiply_by < 60U)
+ {
+ seli = (multiply_by & 0x3cU) + 4U;
+ selp = (multiply_by >> 1U) + 1U;
+ }
+ else
+ {
+ selp = 31U;
+ if (multiply_by > 16384U)
+ {
+ seli = 1U;
+ }
+ else if (multiply_by > 8192U)
+ {
+ seli = 2U;
+ }
+ else if (multiply_by > 2048U)
+ {
+ seli = 4U;
+ }
+ else if (multiply_by >= 501U)
+ {
+ seli = 8U;
+ }
+ else
+ {
+ seli = 4U * (1024U / (multiply_by + 9U));
+ }
+ }
+
+ if (pdec > 1U)
+ {
+ directo = 0U; /* use post divider */
+ pdec = pdec / 2U; /* Account for minus 1 encoding */
+ /* Translate P value */
+ switch (pdec)
+ {
+ case 1U:
+ pdec = 0x62U; /* 1 * 2 */
+ break;
+ case 2U:
+ pdec = 0x42U; /* 2 * 2 */
+ break;
+ case 4U:
+ pdec = 0x02U; /* 4 * 2 */
+ break;
+ case 8U:
+ pdec = 0x0bU; /* 8 * 2 */
+ break;
+ case 16U:
+ pdec = 0x11U; /* 16 * 2 */
+ break;
+ case 32U:
+ pdec = 0x08U; /* 32 * 2 */
+ break;
+ default:
+ pdec = 0x08U;
+ break;
+ }
+ }
+
+ mdec = PLL_MDEC_VAL_SET(pllEncodeM(multiply_by));
+ ndec = 0x302U; /* pre divide by 1 (hardcoded) */
+
+ SYSCON->SYSPLLCTRL = directo | (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) |
+ (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT);
+ SYSCON->SYSPLLPDEC = pdec | (1U << 7U); /* set Pdec value and assert preq */
+ SYSCON->SYSPLLNDEC = ndec | (1UL << 10U); /* set Pdec value and assert preq */
+ SYSCON->SYSPLLMDEC = (1UL << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */
+}
+
+/* Enable USB DEVICE FULL SPEED clock */
+/*! brief Enable USB Device FS clock.
+ * param src : clock source
+ * param freq: clock frequency
+ * Enable USB Device Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq)
+{
+ bool ret = true;
+
+ CLOCK_DisableClock(kCLOCK_Usbd0);
+
+ if (kCLOCK_UsbSrcFro == src)
+ {
+ switch (freq)
+ {
+ case 96000000U:
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */
+ break;
+
+ case 48000000U:
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */
+ break;
+
+ default:
+ ret = false;
+ break;
+ }
+ /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+ SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+ SYSCON_FROCTRL_USBCLKADJ_MASK;
+ /* Select FRO 96 or 48 MHz */
+ CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+ }
+ else
+ {
+ /*Set the USB PLL as the Usb0 CLK*/
+ POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+
+ usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};
+
+ (void)CLOCK_SetUsbPLLFreq(&pll_setup);
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);
+ CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);
+ SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ }
+ CLOCK_EnableClock(kCLOCK_Usbd0);
+ CLOCK_EnableClock(kCLOCK_UsbRam1);
+
+ return ret;
+}
+
+/* Enable USB HOST FULL SPEED clock */
+/*! brief Enable USB HOST FS clock.
+ * param src : clock source
+ * param freq: clock frequency
+ * Enable USB HOST Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq)
+{
+ bool ret = true;
+
+ CLOCK_DisableClock(kCLOCK_Usbhmr0);
+ CLOCK_DisableClock(kCLOCK_Usbhsl0);
+
+ if (kCLOCK_UsbSrcFro == src)
+ {
+ switch (freq)
+ {
+ case 96000000U:
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */
+ break;
+
+ case 48000000U:
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */
+ break;
+
+ default:
+ ret = false;
+ break;
+ }
+ /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+ SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+ SYSCON_FROCTRL_USBCLKADJ_MASK;
+ /* Select FRO 96 or 48 MHz */
+ CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+ }
+ else
+ {
+ /*Set the USB PLL as the Usb0 CLK*/
+ POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+
+ usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};
+
+ (void)CLOCK_SetUsbPLLFreq(&pll_setup);
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);
+ CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);
+ SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ }
+ CLOCK_EnableClock(kCLOCK_Usbhmr0);
+ CLOCK_EnableClock(kCLOCK_Usbhsl0);
+ CLOCK_EnableClock(kCLOCK_UsbRam1);
+
+ return ret;
+}
+
+/* Enable USB DEVICE HIGH SPEED clock */
+/*! brief Enable USB Device HS clock.
+ * param src : clock source
+ * param freq: clock frequency
+ * Enable USB Device High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq)
+{
+ bool ret = true;
+ CLOCK_DisableClock(kCLOCK_Usbd1);
+ /* Power on the VD5 for USB PHY */
+ POWER_SetUsbPhy();
+ if (kCLOCK_UsbSrcFro == src)
+ {
+ switch (freq)
+ {
+ case 96000000U:
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */
+ break;
+
+ case 48000000U:
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */
+ break;
+
+ default:
+ ret = false;
+ break;
+ }
+ /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+ SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+ SYSCON_FROCTRL_USBCLKADJ_MASK;
+ /* Select FRO 96 or 48 MHz */
+ CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);
+ }
+ else
+ {
+ SDK_DelayAtLeastUs(50, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};
+
+ (void)CLOCK_SetUsbPLLFreq(&pll_setup);
+
+ /* Select USB PLL output as USB clock src */
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false);
+ CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);
+ }
+
+ SDK_DelayAtLeastUs(50, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ /* Enable USB1D and USB1RAM */
+ CLOCK_EnableClock(kCLOCK_Usbd1);
+ CLOCK_EnableClock(kCLOCK_UsbRam1);
+ POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */
+ return ret;
+}
+
+/* Enable USB HOST HIGH SPEED clock */
+/*! brief Enable USB HOST HS clock.
+ * param src : clock source
+ * param freq: clock frequency
+ * Enable USB HOST High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq)
+{
+ bool ret = true;
+ CLOCK_DisableClock(kCLOCK_Usbh1);
+ /* Power on the VD5 for USB PHY */
+ POWER_SetUsbPhy();
+ if (kCLOCK_UsbSrcFro == src)
+ {
+ switch (freq)
+ {
+ case 96000000U:
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */
+ break;
+
+ case 48000000U:
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */
+ break;
+
+ default:
+ ret = false;
+ break;
+ }
+ /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+ SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+ SYSCON_FROCTRL_USBCLKADJ_MASK;
+ /* Select FRO 96 or 48 MHz */
+ CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);
+ }
+ else
+ {
+ SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};
+
+ (void)CLOCK_SetUsbPLLFreq(&pll_setup);
+
+ /* Select USB PLL output as USB clock src */
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false);
+ CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);
+ }
+
+ SDK_DelayAtLeastUs(50, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ /* Enable USBh1 and USB1RAM */
+ CLOCK_EnableClock(kCLOCK_Usbh1);
+ CLOCK_EnableClock(kCLOCK_UsbRam1);
+ POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */
+ return ret;
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_clock.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_clock.h new file mode 100644 index 000000000..f14a543dc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_clock.h @@ -0,0 +1,1293 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2019 , NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.3.1. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
+/*@}*/
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could control the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
+#endif
+
+/*!
+ * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
+ *
+ * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
+ * would cache the recent calulation and accelerate the execution to get the
+ * right settings.
+ */
+#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
+#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
+#endif
+
+/* Definition for delay API in clock driver, users can redefine it to the real application. */
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000UL)
+#endif
+
+/*! @brief Clock ip name array for ADC. */
+#define ADC_CLOCKS \
+ { \
+ kCLOCK_Adc0 \
+ }
+/*! @brief Clock ip name array for ROM. */
+#define ROM_CLOCKS \
+ { \
+ kCLOCK_Rom \
+ }
+/*! @brief Clock ip name array for SRAM. */
+#define SRAM_CLOCKS \
+ { \
+ kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
+ }
+/*! @brief Clock ip name array for FLASH. */
+#define FLASH_CLOCKS \
+ { \
+ kCLOCK_Flash \
+ }
+/*! @brief Clock ip name array for FMC. */
+#define FMC_CLOCKS \
+ { \
+ kCLOCK_Fmc \
+ }
+/*! @brief Clock ip name array for EEPROM. */
+#define EEPROM_CLOCKS \
+ { \
+ kCLOCK_Eeprom \
+ }
+/*! @brief Clock ip name array for SPIFI. */
+#define SPIFI_CLOCKS \
+ { \
+ kCLOCK_Spifi \
+ }
+/*! @brief Clock ip name array for INPUTMUX. */
+#define INPUTMUX_CLOCKS \
+ { \
+ kCLOCK_InputMux \
+ }
+/*! @brief Clock ip name array for IOCON. */
+#define IOCON_CLOCKS \
+ { \
+ kCLOCK_Iocon \
+ }
+/*! @brief Clock ip name array for GPIO. */
+#define GPIO_CLOCKS \
+ { \
+ kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
+ }
+/*! @brief Clock ip name array for PINT. */
+#define PINT_CLOCKS \
+ { \
+ kCLOCK_Pint \
+ }
+/*! @brief Clock ip name array for GINT. */
+#define GINT_CLOCKS \
+ { \
+ kCLOCK_Gint, kCLOCK_Gint \
+ }
+/*! @brief Clock ip name array for DMA. */
+#define DMA_CLOCKS \
+ { \
+ kCLOCK_Dma \
+ }
+/*! @brief Clock ip name array for CRC. */
+#define CRC_CLOCKS \
+ { \
+ kCLOCK_Crc \
+ }
+/*! @brief Clock ip name array for WWDT. */
+#define WWDT_CLOCKS \
+ { \
+ kCLOCK_Wwdt \
+ }
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS \
+ { \
+ kCLOCK_Rtc \
+ }
+/*! @brief Clock ip name array for ADC0. */
+#define ADC0_CLOCKS \
+ { \
+ kCLOCK_Adc0 \
+ }
+/*! @brief Clock ip name array for MRT. */
+#define MRT_CLOCKS \
+ { \
+ kCLOCK_Mrt \
+ }
+/*! @brief Clock ip name array for RIT. */
+#define RIT_CLOCKS \
+ { \
+ kCLOCK_Rit \
+ }
+/*! @brief Clock ip name array for SCT0. */
+#define SCT_CLOCKS \
+ { \
+ kCLOCK_Sct0 \
+ }
+/*! @brief Clock ip name array for MCAN. */
+#define MCAN_CLOCKS \
+ { \
+ kCLOCK_Mcan0, kCLOCK_Mcan1 \
+ }
+/*! @brief Clock ip name array for UTICK. */
+#define UTICK_CLOCKS \
+ { \
+ kCLOCK_Utick \
+ }
+/*! @brief Clock ip name array for FLEXCOMM. */
+#define FLEXCOMM_CLOCKS \
+ { \
+ kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
+ kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9, kCLOCK_FlexComm10 \
+ }
+/*! @brief Clock ip name array for LPUART. */
+#define LPUART_CLOCKS \
+ { \
+ kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
+ kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9 \
+ }
+
+/*! @brief Clock ip name array for BI2C. */
+#define BI2C_CLOCKS \
+ { \
+ kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \
+ kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9 \
+ }
+/*! @brief Clock ip name array for LSPI. */
+#define LPSI_CLOCKS \
+ { \
+ kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \
+ kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9 \
+ }
+/*! @brief Clock ip name array for FLEXI2S. */
+#define FLEXI2S_CLOCKS \
+ { \
+ kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
+ kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \
+ }
+/*! @brief Clock ip name array for DMIC. */
+#define DMIC_CLOCKS \
+ { \
+ kCLOCK_DMic \
+ }
+/*! @brief Clock ip name array for CT32B. */
+#define CTIMER_CLOCKS \
+ { \
+ kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
+ }
+/*! @brief Clock ip name array for LCD. */
+#define LCD_CLOCKS \
+ { \
+ kCLOCK_Lcd \
+ }
+/*! @brief Clock ip name array for SDIO. */
+#define SDIO_CLOCKS \
+ { \
+ kCLOCK_Sdio \
+ }
+/*! @brief Clock ip name array for USBRAM. */
+#define USBRAM_CLOCKS \
+ { \
+ kCLOCK_UsbRam1 \
+ }
+/*! @brief Clock ip name array for EMC. */
+#define EMC_CLOCKS \
+ { \
+ kCLOCK_Emc \
+ }
+/*! @brief Clock ip name array for ETH. */
+#define ETH_CLOCKS \
+ { \
+ kCLOCK_Eth \
+ }
+/*! @brief Clock ip name array for AES. */
+#define AES_CLOCKS \
+ { \
+ kCLOCK_Aes \
+ }
+/*! @brief Clock ip name array for OTP. */
+#define OTP_CLOCKS \
+ { \
+ kCLOCK_Otp \
+ }
+/*! @brief Clock ip name array for RNG. */
+#define RNG_CLOCKS \
+ { \
+ kCLOCK_Rng \
+ }
+/*! @brief Clock ip name array for USBHMR0. */
+#define USBHMR0_CLOCKS \
+ { \
+ kCLOCK_Usbhmr0 \
+ }
+/*! @brief Clock ip name array for USBHSL0. */
+#define USBHSL0_CLOCKS \
+ { \
+ kCLOCK_Usbhsl0 \
+ }
+/*! @brief Clock ip name array for SHA0. */
+#define SHA0_CLOCKS \
+ { \
+ kCLOCK_Sha0 \
+ }
+/*! @brief Clock ip name array for SMARTCARD. */
+#define SMARTCARD_CLOCKS \
+ { \
+ kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
+ }
+/*! @brief Clock ip name array for USBD. */
+#define USBD_CLOCKS \
+ { \
+ kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
+ }
+/*! @brief Clock ip name array for USBH. */
+#define USBH_CLOCKS \
+ { \
+ kCLOCK_Usbh1 \
+ }
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+/*------------------------------------------------------------------------------
+ clock_ip_name_t definition:
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 8U
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
+ ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+ (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+#define AHB_CLK_CTRL0 0
+#define AHB_CLK_CTRL1 1
+#define AHB_CLK_CTRL2 2
+#define ASYNC_CLK_CTRL0 3
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+typedef enum _clock_ip_name
+{
+ kCLOCK_IpInvalid = 0U,
+ kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
+ kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
+ kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
+ kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
+ kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),
+ kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
+ kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
+ kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
+ kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
+ kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
+ kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
+ kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
+ kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
+ kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
+ kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
+ kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
+ kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
+ kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
+ kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
+ kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
+ kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
+ kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
+ kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),
+ kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
+ kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+ kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+ kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+ kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+ kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+ kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+ kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+ kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+ kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+ kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+ kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+ kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+ kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+ kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+ kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+ kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+ kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+ kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+ kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+ kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+ kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+ kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+ kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+ kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+ kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+ kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+ kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+ kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+ kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+ kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+ kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+ kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+ kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+ kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+ kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+ kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+ kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+ kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+ kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+ kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+ kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
+ kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
+ kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
+ kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
+ kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
+ kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
+ kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
+ kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
+ kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
+ kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
+ kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
+ kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
+ kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
+ kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
+ kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
+ kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
+ kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
+ kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
+ kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
+ kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+ kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+ kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+ kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+ kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+ kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+ kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+ kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+ kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+ kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+ kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
+ kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
+ kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
+ kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
+ kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
+ kCLOCK_FlexComm10 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
+
+ kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
+ kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
+} clock_ip_name_t;
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+ kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
+ kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
+ kCLOCK_ClockOut, /*!< CLOCKOUT */
+ kCLOCK_FroHf, /*!< FRO48/96 */
+ kCLOCK_UsbPll, /*!< USB1 PLL */
+ kCLOCK_Mclk, /*!< MCLK */
+ kCLOCK_Fro12M, /*!< FRO12M */
+ kCLOCK_ExtClk, /*!< External Clock */
+ kCLOCK_PllOut, /*!< PLL Output */
+ kCLOCK_UsbClk, /*!< USB input */
+ kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
+ kCLOCK_Frg, /*!< Frg Clock */
+ kCLOCK_AsyncApbClk, /*!< Async APB clock */
+} clock_name_t;
+
+/**
+ * Clock source selections for the asynchronous APB clock
+ */
+typedef enum _async_clock_src
+{
+ kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
+ kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
+ kCLOCK_AsyncAudioPllClk,
+ kCLOCK_AsyncI2cClkFc6,
+
+} async_clock_src_t;
+
+/*! @brief Clock Mux Switches
+ * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
+ * starting from LSB upwards
+ *
+ * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
+ *
+ */
+
+#define CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))
+#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
+#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
+
+#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
+#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
+#define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))
+#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((connection)&0xF00U) >> 8U) - 1U))
+#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
+
+#define CM_STICKCLKSEL 0
+#define CM_MAINCLKSELA 1
+#define CM_MAINCLKSELB 2
+#define CM_CLKOUTCLKSELA 3
+#define CM_SYSPLLCLKSEL 5
+#define CM_AUDPLLCLKSEL 7
+#define CM_SPIFICLKSEL 9
+#define CM_ADCASYNCCLKSEL 10
+#define CM_USB0CLKSEL 11
+#define CM_USB1CLKSEL 12
+#define CM_FXCOMCLKSEL0 13
+#define CM_FXCOMCLKSEL1 14
+#define CM_FXCOMCLKSEL2 15
+#define CM_FXCOMCLKSEL3 16
+#define CM_FXCOMCLKSEL4 17
+#define CM_FXCOMCLKSEL5 18
+#define CM_FXCOMCLKSEL6 19
+#define CM_FXCOMCLKSEL7 20
+#define CM_FXCOMCLKSEL8 21
+#define CM_FXCOMCLKSEL9 22
+#define CM_FXCOMCLKSEL10 23
+#define CM_MCLKCLKSEL 25
+#define CM_FRGCLKSEL 27
+#define CM_DMICCLKSEL 28
+#define CM_SCTCLKSEL 29
+#define CM_LCDCLKSEL 30
+#define CM_SDIOCLKSEL 31
+
+#define CM_ASYNCAPB 32U
+
+typedef enum _clock_attach_id
+{
+
+ kSYSTICK_DIV_CLK_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 0),
+ kWDT_OSC_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 1),
+ kOSC32K_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 2),
+ kFRO12M_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 3),
+ kNONE_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 7),
+
+ kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
+ kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
+ kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
+ kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
+ kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
+ kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
+
+ kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
+ kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
+ kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
+ kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
+ kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
+ kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
+ kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
+ kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
+
+ kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
+ kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
+ kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
+ kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
+ kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
+
+ kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0),
+ kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),
+ kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7),
+
+ kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
+ kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
+ kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2),
+ kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
+ kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),
+ kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
+
+ kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
+ kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
+ kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
+ kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),
+ kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
+
+ kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
+ kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
+ kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),
+ kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
+
+ kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0),
+ kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),
+ kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),
+ kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7),
+
+ kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
+ kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
+ kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
+ kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
+ kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
+ kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
+
+ kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
+ kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
+ kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
+ kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
+ kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
+ kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
+
+ kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
+ kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
+ kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
+ kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
+ kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
+ kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
+
+ kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
+ kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
+ kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
+ kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
+ kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
+ kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
+
+ kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
+ kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
+ kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
+ kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
+ kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
+ kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
+
+ kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
+ kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
+ kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
+ kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
+ kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
+ kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
+
+ kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
+ kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
+ kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
+ kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
+ kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
+ kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
+
+ kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
+ kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
+ kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
+ kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
+ kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
+ kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
+
+ kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0),
+ kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1),
+ kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),
+ kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3),
+ kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4),
+ kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7),
+
+ kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0),
+ kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1),
+ kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),
+ kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3),
+ kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4),
+ kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7),
+
+ kMAIN_CLK_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 0),
+ kSYS_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 1),
+ kUSB_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 2),
+ kFRO_HF_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 3),
+ kAUDIO_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 4),
+ kNONE_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 7),
+
+ kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
+ kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
+ kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
+
+ kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
+ kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
+ kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
+ kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
+ kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
+
+ kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
+ kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
+ kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
+ kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
+ kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4),
+ kWDT_OSC_to_DMIC = MUX_A(CM_DMICCLKSEL, 5),
+ kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
+
+ kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
+ kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
+ kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
+ kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
+ kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
+
+ kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
+ kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
+ kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),
+ kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),
+
+ kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
+ kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
+ kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
+ kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
+ kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
+ kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
+
+ kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
+ kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
+ kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
+ kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),
+ kNONE_to_NONE = (int)0x80000000U,
+} clock_attach_id_t;
+
+/* Clock dividers */
+typedef enum _clock_div_name
+{
+ kCLOCK_DivSystickClk = 0,
+ kCLOCK_DivArmTrClkDiv = 1,
+ kCLOCK_DivCan0Clk = 2,
+ kCLOCK_DivCan1Clk = 3,
+ kCLOCK_DivSmartCard0Clk = 4,
+ kCLOCK_DivSmartCard1Clk = 5,
+ kCLOCK_DivAhbClk = 32,
+ kCLOCK_DivClkOut = 33,
+ kCLOCK_DivFrohfClk = 34,
+ kCLOCK_DivSpifiClk = 36,
+ kCLOCK_DivAdcAsyncClk = 37,
+ kCLOCK_DivUsb0Clk = 38,
+ kCLOCK_DivUsb1Clk = 39,
+ kCLOCK_DivFrg = 40,
+ kCLOCK_DivDmicClk = 42,
+ kCLOCK_DivMClk = 43,
+ kCLOCK_DivLcdClk = 44,
+ kCLOCK_DivSctClk = 45,
+ kCLOCK_DivEmcClk = 46,
+ kCLOCK_DivSdioClk = 47
+} clock_div_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+static inline void CLOCK_EnableClock(clock_ip_name_t clk)
+{
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+ if (index < 3UL)
+ {
+ SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ }
+ else
+ {
+ SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
+ ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ }
+}
+
+static inline void CLOCK_DisableClock(clock_ip_name_t clk)
+{
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+ if (index < 3UL)
+ {
+ SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ }
+ else
+ {
+ ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
+ }
+}
+
+/**
+ * @brief
+ * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed
+ * output is enabled.
+ * Usage: CLOCK_SetupFROClocking(frequency), (frequency must be one of 12, 48 or 96 MHz)
+ * Note: Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is
+ * implemented in ROM code and the FROHF TRIM value is stored in OTP
+ *
+ * @param froFreq target fro frequency.
+ * @return Nothing
+ */
+
+void CLOCK_SetupFROClocking(uint32_t froFreq);
+
+/**
+ * @brief Configure the clock selection muxes.
+ * @param connection : Clock to be configured.
+ * @return Nothing
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection);
+/**
+ * @brief Get the actual clock attach id.
+ * This fuction uses the offset in input attach id, then it reads the actual source value in
+ * the register and combine the offset to obtain an actual attach id.
+ * @param attachId : Clock attach id to get.
+ * @return Clock source value.
+ */
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
+/**
+ * @brief Setup peripheral clock dividers.
+ * @param div_name : Clock divider name
+ * @param divided_by_value: Value to be divided
+ * @param reset : Whether to reset the divider counter.
+ * @return Nothing
+ */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
+
+/*! @brief Return Frequency of selected clock
+ * @return Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+/*! @brief Return Frequency of FRO 12MHz
+ * @return Frequency of FRO 12MHz
+ */
+uint32_t CLOCK_GetFro12MFreq(void);
+/*! @brief Return Frequency of ClockOut
+ * @return Frequency of ClockOut
+ */
+uint32_t CLOCK_GetClockOutClkFreq(void);
+/*! @brief Return Frequency of Spifi Clock
+ * @return Frequency of Spifi.
+ */
+uint32_t CLOCK_GetSpifiClkFreq(void);
+/*! @brief Return Frequency of Adc Clock
+ * @return Frequency of Adc Clock.
+ */
+uint32_t CLOCK_GetAdcClkFreq(void);
+/*! brief Return Frequency of MCAN Clock
+ * param MCanSel : 0U: MCAN0; 1U: MCAN1
+ * return Frequency of MCAN Clock
+ */
+uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel);
+/*! @brief Return Frequency of Usb0 Clock
+ * @return Frequency of Usb0 Clock.
+ */
+uint32_t CLOCK_GetUsb0ClkFreq(void);
+/*! @brief Return Frequency of Usb1 Clock
+ * @return Frequency of Usb1 Clock.
+ */
+uint32_t CLOCK_GetUsb1ClkFreq(void);
+/*! @brief Return Frequency of MClk Clock
+ * @return Frequency of MClk Clock.
+ */
+uint32_t CLOCK_GetMclkClkFreq(void);
+/*! @brief Return Frequency of SCTimer Clock
+ * @return Frequency of SCTimer Clock.
+ */
+uint32_t CLOCK_GetSctClkFreq(void);
+/*! @brief Return Frequency of SDIO Clock
+ * @return Frequency of SDIO Clock.
+ */
+uint32_t CLOCK_GetSdioClkFreq(void);
+/*! @brief Return Frequency of LCD Clock
+ * @return Frequency of LCD Clock.
+ */
+uint32_t CLOCK_GetLcdClkFreq(void);
+/*! @brief Return Frequency of LCD CLKIN Clock
+ * @return Frequency of LCD CLKIN Clock.
+ */
+uint32_t CLOCK_GetLcdClkIn(void);
+/*! @brief Return Frequency of External Clock
+ * @return Frequency of External Clock. If no external clock is used returns 0.
+ */
+uint32_t CLOCK_GetExtClkFreq(void);
+/*! @brief Return Frequency of Watchdog Oscillator
+ * @return Frequency of Watchdog Oscillator
+ */
+uint32_t CLOCK_GetWdtOscFreq(void);
+/*! @brief Return Frequency of High-Freq output of FRO
+ * @return Frequency of High-Freq output of FRO
+ */
+uint32_t CLOCK_GetFroHfFreq(void);
+/*! @brief Return Frequency of frg
+ * @return Frequency of FRG
+ */
+uint32_t CLOCK_GetFrgClkFreq(void);
+/*! @brief Return Frequency of dmic
+ * @return Frequency of DMIC
+ */
+uint32_t CLOCK_GetDmicClkFreq(void);
+
+/*!
+ * @brief Set FRG Clk
+ * @return
+ * 1: if set FRG CLK successfully.
+ * 0: if set FRG CLK fail.
+ */
+uint32_t CLOCK_SetFRGClock(uint32_t freq);
+
+/*! @brief Return Frequency of PLL
+ * @return Frequency of PLL
+ */
+uint32_t CLOCK_GetPllOutFreq(void);
+/*! @brief Return Frequency of USB PLL
+ * @return Frequency of PLL
+ */
+uint32_t CLOCK_GetUsbPllOutFreq(void);
+/*! @brief Return Frequency of AUDIO PLL
+ * @return Frequency of PLL
+ */
+uint32_t CLOCK_GetAudioPllOutFreq(void);
+/*! @brief Return Frequency of 32kHz osc
+ * @return Frequency of 32kHz osc
+ */
+uint32_t CLOCK_GetOsc32KFreq(void);
+/*! @brief Return Frequency of Core System
+ * @return Frequency of Core System
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+/*! @brief Return Frequency of I2S MCLK Clock
+ * @return Frequency of I2S MCLK Clock
+ */
+uint32_t CLOCK_GetI2SMClkFreq(void);
+/*! @brief Return Frequency of Flexcomm functional Clock
+ * @return Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
+
+/*! @brief return FRG Clk
+ * @return Frequency of FRG CLK.
+ */
+uint32_t CLOCK_GetFRGInputClock(void);
+/*! @brief Return Asynchronous APB Clock source
+ * @return Asynchronous APB CLock source
+ */
+__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
+{
+ return (async_clock_src_t)(uint32_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3U);
+}
+/*! @brief Return Frequency of Asynchronous APB Clock
+ * @return Frequency of Asynchronous APB Clock Clock
+ */
+uint32_t CLOCK_GetAsyncApbClkFreq(void);
+/*! @brief Return EMC source
+ * @return EMC source
+ */
+__STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq(void)
+{
+ uint32_t freqtmp;
+
+ freqtmp = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
+ return freqtmp / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
+}
+/*! @brief Return Audio PLL input clock rate
+ * @return Audio PLL input clock rate
+ */
+uint32_t CLOCK_GetAudioPLLInClockRate(void);
+/*! @brief Return System PLL input clock rate
+ * @return System PLL input clock rate
+ */
+uint32_t CLOCK_GetSystemPLLInClockRate(void);
+
+/*! @brief Return System PLL output clock rate
+ * @param recompute : Forces a PLL rate recomputation if true
+ * @return System PLL output clock rate
+ * @note The PLL rate is cached in the driver in a variable as
+ * the rate computation function can take some time to perform. It
+ * is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
+
+/*! @brief Return System AUDIO PLL output clock rate
+ * @param recompute : Forces a AUDIO PLL rate recomputation if true
+ * @return System AUDIO PLL output clock rate
+ * @note The AUDIO PLL rate is cached in the driver in a variable as
+ * the rate computation function can take some time to perform. It
+ * is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
+
+/*! @brief Return System USB PLL output clock rate
+ * @param recompute : Forces a USB PLL rate recomputation if true
+ * @return System USB PLL output clock rate
+ * @note The USB PLL rate is cached in the driver in a variable as
+ * the rate computation function can take some time to perform. It
+ * is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute);
+
+/*! @brief Enables and disables PLL bypass mode
+ * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
+ * @return System PLL output clock rate
+ */
+__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
+{
+ if (bypass)
+ {
+ SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
+ }
+ else
+ {
+ SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
+ }
+}
+
+/*! @brief Check if PLL is locked or not
+ * @return true if the PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
+{
+ return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0U);
+}
+
+/*! @brief Check if USB PLL is locked or not
+ * @return true if the USB PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
+{
+ return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0U);
+}
+
+/*! @brief Check if AUDIO PLL is locked or not
+ * @return true if the AUDIO PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
+{
+ return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0U);
+}
+
+/*! @brief Enables and disables SYS OSC
+ * @brief enable : true to enable SYS OSC, false to disable SYS OSC
+ */
+__STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable)
+{
+ if (enable)
+ {
+ SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
+ SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
+ }
+
+ else
+ {
+ SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
+ SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
+ }
+}
+
+/*! @brief Store the current PLL rate
+ * @param rate: Current rate of the PLL
+ * @return Nothing
+ **/
+void CLOCK_SetStoredPLLClockRate(uint32_t rate);
+
+/*! @brief Store the current AUDIO PLL rate
+ * @param rate: Current rate of the PLL
+ * @return Nothing
+ **/
+void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
+
+/*! @brief PLL configuration structure flags for 'flags' field
+ * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
+ *
+ * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
+ * configuration structure must be assigned with the expected PLL frequency. If the
+ * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
+ * function and the driver will determine the PLL rate from the currently selected
+ * PLL source. This flag might be used to configure the PLL input clock more accurately
+ * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
+ *
+ * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
+ * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
+ * are not used.<br>
+ */
+#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
+#define PLL_CONFIGFLAG_FORCENOFRACT \
+ (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \
+ SS hardware */
+
+/*! @brief PLL configuration structure
+ *
+ * This structure can be used to configure the settings for a PLL
+ * setup structure. Fill in the desired configuration for the PLL
+ * and call the PLL setup function to fill in a PLL setup structure.
+ */
+typedef struct _pll_config
+{
+ uint32_t desiredRate; /*!< Desired PLL rate in Hz */
+ uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
+ uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
+} pll_config_t;
+
+/*! @brief PLL setup structure flags for 'flags' field
+ * These flags control how the PLL setup function sets up the PLL
+ */
+#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
+#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
+#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
+
+/*! @brief PLL setup structure
+ * This structure can be used to pre-build a PLL setup configuration
+ * at run-time and quickly set the PLL to the configuration. It can be
+ * populated with the PLL setup function. If powering up or waiting
+ * for PLL lock, the PLL input clock source should be configured prior
+ * to PLL setup.
+ */
+typedef struct _pll_setup
+{
+ uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */
+ uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */
+ uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */
+ uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */
+ uint32_t pllRate; /*!< Acutal PLL rate */
+ uint32_t audpllfrac; /*!< only aduio PLL has this function*/
+ uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
+} pll_setup_t;
+
+/*! @brief PLL status definitions
+ */
+typedef enum _pll_error
+{
+ kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
+ kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
+ kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
+ kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
+ kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
+ kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
+ kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
+ kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
+} pll_error_t;
+
+/*! @brief USB clock source definition. */
+typedef enum _clock_usb_src
+{
+ kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
+ kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
+ kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
+ kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */
+
+ kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(
+ 7U) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */
+} clock_usb_src_t;
+
+/*! @brief USB PDEL Divider. */
+typedef enum _usb_pll_psel
+{
+ pSel_Divide_1 = 0U,
+ pSel_Divide_2,
+ pSel_Divide_4,
+ pSel_Divide_8
+} usb_pll_psel;
+
+/*! @brief PLL setup structure
+ * This structure can be used to pre-build a USB PLL setup configuration
+ * at run-time and quickly set the usb PLL to the configuration. It can be
+ * populated with the USB PLL setup function. If powering up or waiting
+ * for USB PLL lock, the PLL input clock source should be configured prior
+ * to USB PLL setup.
+ */
+typedef struct _usb_pll_setup
+{
+ uint8_t msel; /*!< USB PLL control register msel:1U-256U */
+ uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
+ uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
+ bool direct; /*!< USB PLL CCO output control */
+ bool bypass; /*!< USB PLL inout clock bypass control */
+ bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/
+ uint32_t inputRate; /*!< USB PLL input rate */
+} usb_pll_setup_t;
+
+/*! @brief Return System PLL output clock rate from setup structure
+ * @param pSetup : Pointer to a PLL setup structure
+ * @return System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
+
+/*! @brief Return System AUDIO PLL output clock rate from setup structure
+ * @param pSetup : Pointer to a PLL setup structure
+ * @return System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
+
+/*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure
+ * @param pSetup : Pointer to a PLL setup structure
+ * @return System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);
+
+/*! @brief Return System USB PLL output clock rate from setup structure
+ * @param pSetup : Pointer to a PLL setup structure
+ * @return System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
+
+/*! @brief Set PLL output based on the passed PLL setup data
+ * @param pControl : Pointer to populated PLL control structure to generate setup with
+ * @param pSetup : Pointer to PLL setup structure to be filled
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note Actual frequency for setup may vary from the desired frequency based on the
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
+
+/*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data
+ * @param pControl : Pointer to populated PLL control structure to generate setup with
+ * @param pSetup : Pointer to PLL setup structure to be filled
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note Actual frequency for setup may vary from the desired frequency based on the
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
+
+/*! @brief Set PLL output from PLL setup structure (precise frequency)
+ * @param pSetup : Pointer to populated PLL setup structure
+ * @param flagcfg : Flag configuration for PLL config structure
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
+ * @param pSetup : Pointer to populated PLL setup structure
+ * @param flagcfg : Flag configuration for PLL config structure
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise
+ * frequency)
+ * @param pSetup : Pointer to populated PLL setup structure
+ * @param flagcfg : Flag configuration for PLL config structure
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/**
+ * @brief Set PLL output from PLL setup structure (precise frequency)
+ * @param pSetup : Pointer to populated PLL setup structure
+ * @return kStatus_PLL_Success on success, or PLL setup error code
+ * @note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
+
+/**
+ * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency)
+ * @param pSetup : Pointer to populated PLL setup structure
+ * @return kStatus_PLL_Success on success, or Audio PLL setup error code
+ * @note This function will power off the PLL, setup the Audio PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
+
+/**
+ * @brief Set USB PLL output from USB PLL setup structure (precise frequency)
+ * @param pSetup : Pointer to populated USB PLL setup structure
+ * @return kStatus_PLL_Success on success, or USB PLL setup error code
+ * @note This function will power off the USB PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
+ * and adjust system voltages to the new USB PLL rate. The function will not
+ * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
+
+/*! @brief Set PLL output based on the multiplier and input frequency
+ * @param multiply_by : multiplier
+ * @param input_freq : Clock input frequency of the PLL
+ * @return Nothing
+ * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
+ * function does not disable or enable PLL power, wait for PLL lock,
+ * or adjust system voltages. These must be done in the application.
+ * The function will not alter any source clocks (ie, main systen clock)
+ * that may use the PLL, so these should be setup prior to and after
+ * exiting the function.
+ */
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
+
+/*! @brief Disable USB clock.
+ *
+ * Disable USB clock.
+ */
+static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
+{
+ CLOCK_DisableClock(clk);
+}
+
+/*! @brief Enable USB Device FS clock.
+ * @param src : clock source
+ * @param freq: clock frequency
+ * Enable USB Device Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Enable USB HOST FS clock.
+ * @param src : clock source
+ * @param freq: clock frequency
+ * Enable USB HOST Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Set the current Usb PLL Rate
+ */
+void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate);
+
+/*! @brief Enable USB Device HS clock.
+ * @param src : clock source
+ * @param freq: clock frequency
+ * Enable USB Device High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Enable USB HOST HS clock.
+ * @param src : clock source
+ * @param freq: clock frequency
+ * Enable USB HOST High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_common.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_common.c new file mode 100644 index 000000000..f6284379c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_common.c @@ -0,0 +1,225 @@ +/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#define SDK_MEM_MAGIC_NUMBER 12345U
+
+typedef struct _mem_align_control_block
+{
+ uint16_t identifier; /*!< Identifier for the memory control block. */
+ uint16_t offset; /*!< offset from aligned address to real address */
+} mem_align_cb_t;
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+#ifndef __GIC_PRIO_BITS
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Image$$VECTOR_ROM$$Base[];
+ extern uint32_t Image$$VECTOR_RAM$$Base[];
+ extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+ extern uint32_t __VECTOR_TABLE[];
+ extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+ extern uint32_t __VECTOR_TABLE[];
+ extern uint32_t __VECTOR_RAM[];
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+ uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
+ uint32_t n;
+ uint32_t ret;
+ uint32_t irqMaskValue;
+
+ irqMaskValue = DisableGlobalIRQ();
+ if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+ {
+ /* Copy the vector table from ROM to RAM */
+ for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+ {
+ __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+ }
+ /* Point the VTOR to the position of vector table */
+ SCB->VTOR = (uint32_t)__VECTOR_RAM;
+ }
+
+ ret = __VECTOR_RAM[irq + 16];
+ /* make sure the __VECTOR_RAM is noncachable */
+ __VECTOR_RAM[irq + 16] = irqHandler;
+
+ EnableGlobalIRQ(irqMaskValue);
+
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+
+ return ret;
+}
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#endif /* __GIC_PRIO_BITS. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t intNumber = (uint32_t)interrupt;
+
+ uint32_t index = 0;
+
+ while (intNumber >= 32u)
+ {
+ index++;
+ intNumber -= 32u;
+ }
+
+ SYSCON->STARTERSET[index] = 1u << intNumber;
+ EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t intNumber = (uint32_t)interrupt;
+
+ DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+ uint32_t index = 0;
+
+ while (intNumber >= 32u)
+ {
+ index++;
+ intNumber -= 32u;
+ }
+
+ SYSCON->STARTERCLR[index] = 1u << intNumber;
+}
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+void *SDK_Malloc(size_t size, size_t alignbytes)
+{
+ mem_align_cb_t *p_cb = NULL;
+ uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
+ union
+ {
+ void *pointer_value;
+ uint32_t unsigned_value;
+ } p_align_addr, p_addr;
+
+ p_addr.pointer_value = malloc(alignedsize);
+
+ if (p_addr.pointer_value == NULL)
+ {
+ return NULL;
+ }
+
+ p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
+
+ p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
+ p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
+ p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
+
+ return p_align_addr.pointer_value;
+}
+
+void SDK_Free(void *ptr)
+{
+ union
+ {
+ void *pointer_value;
+ uint32_t unsigned_value;
+ } p_free;
+ p_free.pointer_value = ptr;
+ mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
+
+ if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
+ {
+ return;
+ }
+
+ p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+ free(p_free.pointer_value);
+}
+
+/*!
+ * @brief Delay function bases on while loop, every loop includes three instructions.
+ *
+ * @param count Counts of loop needed for dalay.
+ */
+#ifndef __XCC__
+#if defined(__CC_ARM) /* This macro is arm v5 specific */
+/* clang-format off */
+__ASM static void DelayLoop(uint32_t count)
+{
+loop
+ SUBS R0, R0, #1
+ CMP R0, #0
+ BNE loop
+ BX LR
+}
+/* clang-format on */
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
+ * use SUB and CMP here for compatibility */
+static void DelayLoop(uint32_t count)
+{
+ __ASM volatile(" MOV R0, %0" : : "r"(count));
+ __ASM volatile(
+ "loop: \n"
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+ " SUB R0, R0, #1 \n"
+#else
+ " SUBS R0, R0, #1 \n"
+#endif
+ " CMP R0, #0 \n"
+
+ " BNE loop \n");
+}
+#endif /* defined(__CC_ARM) */
+
+/*!
+ * @brief Delay at least for some time.
+ * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+ * if precise delay count was needed, please implement a new delay function with hardware timer.
+ *
+ * @param delay_us Delay time in unit of microsecond.
+ * @param coreClock_Hz Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz)
+{
+ assert(0U != delay_us);
+ uint64_t count = USEC_TO_COUNT(delay_us, coreClock_Hz);
+ assert(count <= UINT32_MAX);
+
+ /* Divide value may be different in various environment to ensure delay is precise.
+ * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
+ * two instructions in one period, through test here set divide 2. Other M cores use
+ * divide 4. By the way, divide 2 or 4 could let odd count lost precision, but it does
+ * not matter because other instructions outside while loop is enough to fill the time.
+ */
+#if (__CORTEX_M == 7)
+ count = count / 2U;
+#else
+ count = count / 4U;
+#endif
+ DelayLoop((uint32_t)count);
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_common.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_common.h new file mode 100644 index 000000000..b7be9c3f1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_common.h @@ -0,0 +1,648 @@ +/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#if defined(__ICCARM__)
+#include <stddef.h>
+#endif
+
+/*
+ * For CMSIS pack RTE.
+ * CMSIS pack RTE generates "RTC_Components.h" which contains the statements
+ * of the related <RTE_Components_h> element for all selected software components.
+ */
+#ifdef _RTE_
+#include "RTE_Components.h"
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief common driver version 2.2.2. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+/*@}*/
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+ kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
+ kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
+ kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
+ kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
+ kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
+ kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
+ kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
+ kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
+ kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
+ kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
+ kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
+ kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
+ kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
+ kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
+ kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
+ kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
+ kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
+ kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
+ kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
+ kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
+ kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
+ kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
+ kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
+ kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
+ kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
+ kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
+ kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
+ kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
+ kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
+ kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
+ kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
+ kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
+ kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
+ kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
+ kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
+ kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
+ kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
+ kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
+ kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
+ kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
+ kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
+ kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
+ kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
+ kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
+ kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
+ kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
+ kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
+ kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
+ kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
+ kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
+ kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
+ kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
+ kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
+ kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
+ kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
+ kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
+ kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
+ kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
+ kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
+ kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
+ kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
+ kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
+ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
+ kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
+ kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
+ kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
+ kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */
+ kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
+ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
+ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
+ kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
+ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
+ kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
+
+ kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
+ kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
+ kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
+ kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
+ kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
+ kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
+ kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
+ kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
+ kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
+ kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
+ kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
+ kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
+ kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
+ kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
+ kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
+ kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
+ kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
+ kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
+ kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
+ kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
+ kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
+ kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
+ kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */
+ kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */
+};
+
+/*! @brief Generic status return codes. */
+enum
+{
+ kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+ kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+ kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+ kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+ kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+ kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+ kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*
+ * Macro guard for whether to use default weak IRQ implementation in drivers
+ */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*! @name Alignment variable definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http:/ /supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+ _Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
+#endif
+#elif defined(__GNUC__)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
+#endif
+#else
+#error Toolchain not supported
+#define SDK_ALIGN(var, alignbytes) var
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var
+#endif
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var
+#endif
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+ ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
+/* @} */
+
+/*! @name Non-cacheable region definition macros */
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
+ * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
+ * will be initialized to zero in system startup.
+ */
+/* @{ */
+#if (defined(__ICCARM__))
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#endif
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
+#if(defined(__CC_ARM))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
+#endif
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#endif
+#elif(defined(__XCC__))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
+#elif(defined(__GNUC__))
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#endif
+#else
+#error Toolchain not supported.
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
+#endif
+/* @} */
+
+/*! @name Time sensitive region */
+/* @{ */
+#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+#else
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#else
+#error Toolchain not supported.
+#endif
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+/* @} */
+
+/*! @name Ram Function */
+#if (defined(__ICCARM__))
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#elif(defined(__GNUC__))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/* @} */
+
+/*! @name Suppress fallthrough warning macro */
+/* For switch case code block, if case section ends without "break;" statement, there wil be
+ fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ case section which misses "break;"statement.
+ */
+/* @{ */
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough))
+#else
+#define SUPPRESS_FALL_THROUGH_WARNING()
+#endif
+/* @} */
+
+#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+void DefaultISR(void);
+#endif
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+ (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+ extern "C"
+{
+#endif
+
+ /*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt enabled successfully
+ * @retval kStatus_Fail Failed to enable the interrupt
+ */
+ static inline status_t EnableIRQ(IRQn_Type interrupt)
+ {
+ if (NotAvail_IRQn == interrupt)
+ {
+ return kStatus_Fail;
+ }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ {
+ return kStatus_Fail;
+ }
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+ GIC_EnableIRQ(interrupt);
+#else
+ NVIC_EnableIRQ(interrupt);
+#endif
+ return kStatus_Success;
+ }
+
+ /*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt disabled successfully
+ * @retval kStatus_Fail Failed to disable the interrupt
+ */
+ static inline status_t DisableIRQ(IRQn_Type interrupt)
+ {
+ if (NotAvail_IRQn == interrupt)
+ {
+ return kStatus_Fail;
+ }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ {
+ return kStatus_Fail;
+ }
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+ GIC_DisableIRQ(interrupt);
+#else
+ NVIC_DisableIRQ(interrupt);
+#endif
+ return kStatus_Success;
+ }
+
+ /*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+ static inline uint32_t DisableGlobalIRQ(void)
+ {
+#if defined (__XCC__)
+ return 0;
+#else
+#if defined(CPSR_I_Msk)
+ uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+ __disable_irq();
+
+ return cpsr;
+#else
+ uint32_t regPrimask = __get_PRIMASK();
+
+ __disable_irq();
+
+ return regPrimask;
+#endif
+#endif
+ }
+
+ /*!
+ * @brief Enable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+ static inline void EnableGlobalIRQ(uint32_t primask)
+ {
+#if defined (__XCC__)
+#else
+#if defined(CPSR_I_Msk)
+ __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+ __set_PRIMASK(primask);
+#endif
+#endif
+ }
+
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+ /*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+ /*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+ void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+ /*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+ void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+ /*!
+ * @brief Allocate memory with given alignment and aligned size.
+ *
+ * This is provided to support the dynamically allocated memory
+ * used in cache-able region.
+ * @param size The length required to malloc.
+ * @param alignbytes The alignment size.
+ * @retval The allocated memory.
+ */
+ void *SDK_Malloc(size_t size, size_t alignbytes);
+
+ /*!
+ * @brief Free memory.
+ *
+ * @param ptr The memory to be release.
+ */
+ void SDK_Free(void *ptr);
+
+ /*!
+ * @brief Delay at least for some time.
+ * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+ * if precise delay count was needed, please implement a new delay function with hardware timer.
+ *
+ * @param delay_us Delay time in unit of microsecond.
+ * @param coreClock_Hz Core clock frequency with Hz.
+ */
+ void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_emc.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_emc.c new file mode 100644 index 000000000..57e9d4b7c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_emc.c @@ -0,0 +1,445 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_emc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.emc"
+#endif
+
+/*! @brief Define macros for EMC driver. */
+#define EMC_REFRESH_CLOCK_PARAM (16U)
+#define EMC_SDRAM_WAIT_CYCLES (2000U)
+#define EMC_DYNCTL_COLUMNBASE_OFFSET (0U)
+#define EMC_DYNCTL_COLUMNBASE_MASK (0x3U)
+#define EMC_DYNCTL_COLUMNPLUS_OFFSET (3U)
+#define EMC_DYNCTL_COLUMNPLUS_MASK (0x18U)
+#define EMC_DYNCTL_BUSWIDTH_MASK (0x80U)
+#define EMC_DYNCTL_BUSADDRMAP_MASK (0x20U)
+#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1cU)
+#define EMC_SDRAM_BANKCS_BA0_MASK (uint32_t)(0x2000)
+#define EMC_SDRAM_BANKCS_BA1_MASK (uint32_t)(0x4000)
+#define EMC_SDRAM_BANKCS_BA_MASK (EMC_SDRAM_BANKCS_BA0_MASK | EMC_SDRAM_BANKCS_BA1_MASK)
+#define EMC_DIV_ROUND_UP(n, m) (((n) + (m)-1U) / (m))
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for EMC module.
+ *
+ * @param base EMC peripheral base address
+ */
+static uint32_t EMC_GetInstance(EMC_Type *base);
+
+/*!
+ * @brief Get the clock cycles of EMC clock.
+ * The function is used to calculate the multiple of the
+ * 16 EMCCLKs between the timer_Ns period.
+ *
+ * @param base EMC peripheral base address
+ * @param timer_Ns The timer/period in unit of nanosecond
+ * @param plus The plus added to the register settings to reach the calculated cycles.
+ * @return The calculated cycles.
+ */
+static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus);
+
+/*!
+ * @brief Get the shift value to shift the mode register content by.
+ *
+ * @param addrMap EMC address map for the dynamic memory configuration.
+ * It is the bit 14 ~ bit 7 of the EMC_DYNAMICCONFIG.
+ * @return The offset value to shift the mode register content by.
+ */
+static uint32_t EMC_ModeOffset(uint32_t addrMap);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to EMC clocks for each instance. */
+static const clock_ip_name_t s_EMCClock[FSL_FEATURE_SOC_EMC_COUNT] = EMC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_EMC_HAS_NO_RESET) && FSL_FEATURE_EMC_HAS_NO_RESET)
+/*! @brief Pointers to EMC resets for each instance. */
+static const reset_ip_name_t s_emcResets[] = EMC_RSTS;
+#endif
+
+/*! @brief Pointers to EMC bases for each instance. */
+static const EMC_Type *const s_EMCBases[] = EMC_BASE_PTRS;
+
+/*! @brief Define the start address for each chip controlled by EMC. */
+static const uint32_t s_EMCDYCSBases[] = EMC_DYCS_ADDRESS;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t EMC_GetInstance(EMC_Type *base)
+{
+ uint32_t instance;
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < ARRAY_SIZE(s_EMCBases); instance++)
+ {
+ if (s_EMCBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < ARRAY_SIZE(s_EMCBases));
+
+ return instance;
+}
+
+static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus)
+{
+ uint32_t cycles;
+
+ cycles = CLOCK_GetEmcClkFreq() / EMC_HZ_ONEMHZ * timer_Ns;
+ cycles = EMC_DIV_ROUND_UP(cycles, EMC_MILLISECS_ONESEC); /* Round up. */
+
+ /* Decrese according to the plus. */
+ if (cycles >= plus)
+ {
+ cycles = cycles - plus;
+ }
+ else
+ {
+ cycles = 0;
+ }
+
+ return cycles;
+}
+
+static uint32_t EMC_ModeOffset(uint32_t addrMap)
+{
+ uint8_t offset = 0;
+ uint32_t columbase = addrMap & EMC_DYNCTL_COLUMNBASE_MASK;
+
+ /* First calculate the column length. */
+ if (columbase == 2U)
+ {
+ offset = 8;
+ }
+ else
+ {
+ if (0U == columbase)
+ {
+ offset = 9;
+ }
+ else
+ {
+ offset = 8;
+ }
+
+ /* Add column length increase check. */
+ offset += (uint8_t)((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET);
+ }
+
+ /* Add Buswidth/16. */
+ if (0U != (addrMap & EMC_DYNCTL_BUSWIDTH_MASK))
+ {
+ offset += 2U;
+ }
+ else
+ {
+ offset += 1U;
+ }
+
+ /* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */
+ if (0U == (addrMap & EMC_DYNCTL_BUSADDRMAP_MASK))
+ {
+ if (0U == (addrMap & EMC_DYNCTL_DEVBANKS_BITS_MASK))
+ {
+ offset += 1U;
+ }
+ else
+ {
+ offset += 2U;
+ }
+ }
+
+ return offset;
+}
+
+/*!
+ * brief Initializes the basic for EMC.
+ * This function ungates the EMC clock, initializes the emc system configure
+ * and enable the EMC module. This function must be called in the first step to initialize
+ * the external memory.
+ *
+ * param base EMC peripheral base address.
+ * param config The EMC basic configuration.
+ */
+void EMC_Init(EMC_Type *base, emc_basic_config_t *config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Enable the clock. */
+ CLOCK_EnableClock((s_EMCClock[EMC_GetInstance(base)]));
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_EMC_HAS_NO_RESET) && FSL_FEATURE_EMC_HAS_NO_RESET)
+ /* Reset the EMC module */
+ RESET_PeripheralReset(s_emcResets[EMC_GetInstance(base)]);
+#endif
+
+ /* Reset the EMC. */
+ SYSCON->PRESETCTRL[2] |= SYSCON_PRESETCTRL_EMC_RESET_MASK;
+ SYSCON->PRESETCTRL[2] &= ~SYSCON_PRESETCTRL_EMC_RESET_MASK;
+
+ /* Set the EMC sytem configure. */
+ SYSCON->EMCCLKDIV = SYSCON_EMCCLKDIV_DIV(config->emcClkDiv);
+
+ SYSCON->EMCSYSCTRL = SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(config->fbClkSrc);
+
+ /* Set the endian mode. */
+ base->CONFIG = (uint32_t)config->endian;
+ /* Enable the EMC module with normal memory map mode and normal work mode. */
+ base->CONTROL = EMC_CONTROL_E_MASK;
+}
+
+/*!
+ * brief Initializes the dynamic memory controller.
+ * This function initializes the dynamic memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external dynamic memory.
+ *
+ * param base EMC peripheral base address.
+ * param timing The timing and latency for dynamica memory controller setting. It shall
+ * be used for all dynamica memory chips, threfore the worst timing value for all
+ * used chips must be given.
+ * param configure The EMC dynamic memory controller chip independent configuration pointer.
+ * This configuration pointer is actually pointer to a configration array. the array number
+ * depends on the "totalChips".
+ * param totalChips The total dynamic memory chip numbers been used or the length of the
+ * "emc_dynamic_chip_config_t" type memory.
+ */
+void EMC_DynamicMemInit(EMC_Type *base,
+ emc_dynamic_timing_config_t *timing,
+ emc_dynamic_chip_config_t *config,
+ uint32_t totalChips)
+{
+ assert(NULL != config);
+ assert(NULL != timing);
+ assert(totalChips <= EMC_DYNAMIC_MEMDEV_NUM);
+
+ uint32_t count;
+ uint32_t casLatency;
+ uint32_t addr;
+ uint32_t offset;
+ uint32_t data;
+ emc_dynamic_chip_config_t *dynamicConfig = config;
+
+ /* Setting for dynamic memory controller chip independent configuration. */
+ for (count = 0; (count < totalChips); count++)
+ {
+ if (NULL == dynamicConfig)
+ {
+ break;
+ }
+ else
+ {
+ base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG =
+ EMC_DYNAMIC_DYNAMICCONFIG_MD(dynamicConfig->dynamicDevice) | EMC_ADDRMAP(dynamicConfig->devAddrMap);
+ /* Abstract CAS latency from the sdram mode reigster setting values. */
+ casLatency = ((uint32_t)dynamicConfig->sdramModeReg & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT;
+ base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICRASCAS =
+ EMC_DYNAMIC_DYNAMICRASCAS_RAS(dynamicConfig->rAS_Nclk) | EMC_DYNAMIC_DYNAMICRASCAS_CAS(casLatency);
+
+ dynamicConfig++;
+ }
+ }
+
+ /* Configure the Dynamic Memory controller timing/latency for all chips. */
+ base->DYNAMICREADCONFIG = EMC_DYNAMICREADCONFIG_RD(timing->readConfig);
+ base->DYNAMICRP = EMC_CalculateTimerCycles(base, timing->tRp_Ns, 1) & EMC_DYNAMICRP_TRP_MASK;
+ base->DYNAMICRAS = EMC_CalculateTimerCycles(base, timing->tRas_Ns, 1) & EMC_DYNAMICRAS_TRAS_MASK;
+ base->DYNAMICSREX = EMC_CalculateTimerCycles(base, timing->tSrex_Ns, 1) & EMC_DYNAMICSREX_TSREX_MASK;
+ base->DYNAMICAPR = EMC_CalculateTimerCycles(base, timing->tApr_Ns, 1) & EMC_DYNAMICAPR_TAPR_MASK;
+ base->DYNAMICDAL = EMC_CalculateTimerCycles(base, timing->tDal_Ns, 0) & EMC_DYNAMICDAL_TDAL_MASK;
+ base->DYNAMICWR = EMC_CalculateTimerCycles(base, timing->tWr_Ns, 1) & EMC_DYNAMICWR_TWR_MASK;
+ base->DYNAMICRC = EMC_CalculateTimerCycles(base, timing->tRc_Ns, 1) & EMC_DYNAMICRC_TRC_MASK;
+ base->DYNAMICRFC = EMC_CalculateTimerCycles(base, timing->tRfc_Ns, 1) & EMC_DYNAMICRFC_TRFC_MASK;
+ base->DYNAMICXSR = EMC_CalculateTimerCycles(base, timing->tXsr_Ns, 1) & EMC_DYNAMICXSR_TXSR_MASK;
+ base->DYNAMICRRD = EMC_CalculateTimerCycles(base, timing->tRrd_Ns, 1) & EMC_DYNAMICRRD_TRRD_MASK;
+ base->DYNAMICMRD = EMC_DYNAMICMRD_TMRD((timing->tMrd_Nclk > 0U) ? timing->tMrd_Nclk - 1UL : 0UL);
+
+ SDK_DelayAtLeastUs(EMC_SDRAM_NOP_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ /* Step 2. issue nop command. */
+ base->DYNAMICCONTROL = 0x00000183;
+
+ SDK_DelayAtLeastUs(EMC_SDRAM_PRECHARGE_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ /* Step 3. issue precharge all command. */
+ base->DYNAMICCONTROL = 0x00000103;
+
+ /* Step 4. issue two auto-refresh command. */
+ base->DYNAMICREFRESH = 2;
+ SDK_DelayAtLeastUs(EMC_SDRAM_AUTO_REFRESH_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+ base->DYNAMICREFRESH = EMC_CalculateTimerCycles(base, timing->refreshPeriod_Nanosec, 0) / EMC_REFRESH_CLOCK_PARAM;
+
+ /* Step 5. issue a mode command and set the mode value. */
+ base->DYNAMICCONTROL = 0x00000083;
+
+ /* Calculate the mode settings here and to reach the 8 auto-refresh time requirement. */
+ dynamicConfig = config;
+ for (count = 0; (count < totalChips); count++)
+ {
+ if (NULL == dynamicConfig)
+ {
+ break;
+ }
+ else
+ {
+ /* Get the shift value first. */
+ offset = EMC_ModeOffset(dynamicConfig->devAddrMap);
+ addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] |
+ ((uint32_t)(dynamicConfig->sdramModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) << offset));
+ /* Set the right mode setting value. */
+ data = *(volatile uint32_t *)addr;
+ data = data;
+ dynamicConfig++;
+ }
+ }
+
+ if (kEMC_Sdram != config->dynamicDevice)
+ {
+ /* Add extended mode register if the low-power sdram is used. */
+ base->DYNAMICCONTROL = 0x00000083;
+ /* Calculate the mode settings for extended mode register. */
+ dynamicConfig = config;
+ for (count = 0; (count < totalChips); count++)
+ {
+ if (NULL == dynamicConfig)
+ {
+ break;
+ }
+ else
+ {
+ /* Get the shift value first. */
+ offset = EMC_ModeOffset(dynamicConfig->devAddrMap);
+ addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] |
+ (((uint32_t)(dynamicConfig->sdramExtModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) |
+ EMC_SDRAM_BANKCS_BA1_MASK)
+ << offset));
+ /* Set the right mode setting value. */
+ data = *(volatile uint32_t *)addr;
+ data = data;
+ dynamicConfig++;
+ }
+ }
+ }
+
+ /* Step 6. issue normal operation command. */
+ base->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */
+
+ /* The buffer shall be disabled when do the sdram initialization and
+ * enabled after the initialization during normal opeation.
+ */
+ dynamicConfig = config;
+ for (count = 0; (count < totalChips); count++)
+ {
+ if (NULL == dynamicConfig)
+ {
+ break;
+ }
+ else
+ {
+ base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG |= EMC_DYNAMIC_DYNAMICCONFIG_B_MASK;
+ dynamicConfig++;
+ }
+ }
+}
+
+/*!
+ * brief Initializes the static memory controller.
+ * This function initializes the static memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external static memory.
+ *
+ * param base EMC peripheral base address.
+ * param extWait_Ns The extended wait timeout or the read/write transfer time.
+ * This is common for all static memory chips and set with NULL if not required.
+ * param configure The EMC static memory controller chip independent configuration pointer.
+ * This configuration pointer is actually pointer to a configration array. the array number
+ * depends on the "totalChips".
+ * param totalChips The total static memory chip numbers been used or the length of the
+ * "emc_static_chip_config_t" type memory.
+ */
+void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips)
+{
+ assert(NULL != config);
+
+ uint32_t count;
+ emc_static_chip_config_t *staticConfig = config;
+
+ /* Initialize extended wait. */
+ if (NULL != extWait_Ns)
+ {
+ for (count = 0; (count < totalChips) && (staticConfig != NULL); count++)
+ {
+ assert(0U != (staticConfig->specailConfig & (uint32_t)kEMC_AsynchronosPageEnable));
+ }
+
+ base->STATICEXTENDEDWAIT = EMC_CalculateTimerCycles(base, *extWait_Ns, 1);
+ staticConfig++;
+ }
+
+ /* Initialize the static memory chip specific configure. */
+ staticConfig = config;
+ for (count = 0; (count < totalChips); count++)
+ {
+ if (NULL == staticConfig)
+ {
+ break;
+ }
+ else
+ {
+ base->STATIC[staticConfig->chipIndex].STATICCONFIG =
+ (staticConfig->specailConfig | (uint32_t)staticConfig->memWidth);
+ base->STATIC[staticConfig->chipIndex].STATICWAITWEN =
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitWriteEn_Ns, 1);
+ base->STATIC[staticConfig->chipIndex].STATICWAITOEN =
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitOutEn_Ns, 0);
+ base->STATIC[staticConfig->chipIndex].STATICWAITRD =
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitReadNoPage_Ns, 1);
+ base->STATIC[staticConfig->chipIndex].STATICWAITPAGE =
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitReadPage_Ns, 1);
+ base->STATIC[staticConfig->chipIndex].STATICWAITWR =
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitWrite_Ns, 2);
+ base->STATIC[staticConfig->chipIndex].STATICWAITTURN =
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitTurn_Ns, 1);
+
+ staticConfig++;
+ }
+ }
+}
+
+/*!
+ * brief Deinitializes the EMC module and gates the clock.
+ * This function gates the EMC controller clock. As a result, the EMC
+ * module doesn't work after calling this function.
+ *
+ * param base EMC peripheral base address.
+ */
+void EMC_Deinit(EMC_Type *base)
+{
+ /* Deinit the EMC. */
+ base->CONTROL &= ~EMC_CONTROL_E_MASK;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Disable the clock. */
+ CLOCK_DisableClock(s_EMCClock[EMC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_emc.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_emc.h new file mode 100644 index 000000000..082ac508e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_emc.h @@ -0,0 +1,364 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_EMC_H_
+#define _FSL_EMC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup emc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief EMC driver version. */
+#define FSL_EMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
+
+/*! @brief Define the chip numbers for dynamic and static memory devices. */
+#define EMC_STATIC_MEMDEV_NUM (4U)
+#define EMC_DYNAMIC_MEMDEV_NUM (4U)
+#define EMC_ADDRMAP_SHIFT EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT
+#define EMC_ADDRMAP_MASK (EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK | EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_ADDRMAP(x) (((uint32_t)(((uint32_t)(x)) << EMC_ADDRMAP_SHIFT)) & EMC_ADDRMAP_MASK)
+#define EMC_HZ_ONEMHZ (1000000U)
+#define EMC_MILLISECS_ONESEC (1000U)
+#define EMC_SDRAM_MODE_CL_SHIFT (4U)
+#define EMC_SDRAM_MODE_CL_MASK (0x70U)
+/*! @brief EDMA_SDRAM NOP command wait us */
+#ifndef EMC_SDRAM_NOP_DELAY_US
+#define EMC_SDRAM_NOP_DELAY_US (100U)
+#endif
+/*! @brief EDMA_SDRAM precharge command wait us */
+#ifndef EMC_SDRAM_PRECHARGE_DELAY_US
+#define EMC_SDRAM_PRECHARGE_DELAY_US (100U)
+#endif
+/*! @brief EDMA_SDRAM auto refresh wait us */
+#ifndef EMC_SDRAM_AUTO_REFRESH_DELAY_US
+#define EMC_SDRAM_AUTO_REFRESH_DELAY_US (50U)
+#endif
+/*!
+ * @brief Define EMC memory width for static memory device.
+ */
+typedef enum _emc_static_memwidth
+{
+ kEMC_8BitWidth = 0x0U, /*!< 8 bit memory width. */
+ kEMC_16BitWidth, /*!< 16 bit memory width. */
+ kEMC_32BitWidth /*!< 32 bit memory width. */
+} emc_static_memwidth_t;
+
+/*!
+ * @brief Define EMC static configuration.
+ */
+typedef enum _emc_static_special_config
+{
+ kEMC_AsynchronosPageEnable = 0x0008U, /*!< Enable the asynchronous page mode. page length four. */
+ kEMC_ActiveHighChipSelect = 0x0040U, /*!< Chip select active high. */
+ kEMC_ByteLaneStateAllLow = 0x0080U, /*!< Reads/writes the respective valuie bits in BLS3:0 are low. */
+ kEMC_ExtWaitEnable = 0x0100U, /*!< Extended wait enable. */
+ kEMC_BufferEnable = 0x80000U /*!< Buffer enable. */
+} emc_static_special_config_t;
+
+/*! @brief EMC dynamic memory device. */
+typedef enum _emc_dynamic_device
+{
+ kEMC_Sdram = 0x0U, /*!< Dynamic memory device: SDRAM. */
+ kEMC_Lpsdram, /*!< Dynamic memory device: Low-power SDRAM. */
+} emc_dynamic_device_t;
+
+/*! @brief EMC dynamic read strategy. */
+typedef enum _emc_dynamic_read
+{
+ kEMC_NoDelay = 0x0U, /*!< No delay. */
+ kEMC_Cmddelay, /*!< Command delayed strategy, using EMCCLKDELAY. */
+ kEMC_CmdDelayPulseOneclk, /*!< Command delayed strategy pluse one clock cycle using EMCCLKDELAY. */
+ kEMC_CmddelayPulsetwoclk, /*!< Command delayed strategy pulse two clock cycle using EMCCLKDELAY. */
+} emc_dynamic_read_t;
+
+/*! @brief EMC endian mode. */
+typedef enum _emc_endian_mode
+{
+ kEMC_LittleEndian = 0x0U, /*!< Little endian mode. */
+ kEMC_BigEndian, /*!< Big endian mode. */
+} emc_endian_mode_t;
+
+/*! @brief EMC Feedback clock input source select. */
+typedef enum _emc_fbclk_src
+{
+ kEMC_IntloopbackEmcclk = 0U, /*!< Use the internal loop back from EMC_CLK output. */
+ kEMC_EMCFbclkInput /*!< Use the external EMC_FBCLK input. */
+} emc_fbclk_src_t;
+
+/*! @brief EMC dynamic timing/delay configure structure. */
+typedef struct _emc_dynamic_timing_config
+{
+ emc_dynamic_read_t readConfig; /* Dynamic read strategy. */
+ uint32_t refreshPeriod_Nanosec; /*!< The refresh period in unit of nanosecond. */
+ uint32_t tRp_Ns; /*!< Precharge command period in unit of nanosecond. */
+ uint32_t tRas_Ns; /*!< Active to precharge command period in unit of nanosecond. */
+ uint32_t tSrex_Ns; /*!< Self-refresh exit time in unit of nanosecond. */
+ uint32_t tApr_Ns; /*!< Last data out to active command time in unit of nanosecond. */
+ uint32_t tDal_Ns; /*!< Data-in to active command in unit of nanosecond. */
+ uint32_t tWr_Ns; /*!< Write recovery time in unit of nanosecond. */
+ uint32_t tRc_Ns; /*!< Active to active command period in unit of nanosecond. */
+ uint32_t tRfc_Ns; /*!< Auto-refresh period and auto-refresh to active command period in unit of nanosecond. */
+ uint32_t tXsr_Ns; /*!< Exit self-refresh to active command time in unit of nanosecond. */
+ uint32_t tRrd_Ns; /*!< Active bank A to active bank B latency in unit of nanosecond. */
+ uint8_t tMrd_Nclk; /*!< Load mode register to active command time in unit of EMCCLK cycles.*/
+} emc_dynamic_timing_config_t;
+
+/*!
+ * @brief EMC dynamic memory controller independent chip configuration structure.
+ * Please take refer to the address mapping table in the RM in EMC chapter when you
+ * set the "devAddrMap". Choose the right Bit 14 Bit12 ~ Bit 7 group in the table
+ * according to the bus width/banks/row/colum length for you device.
+ * Set devAddrMap with the value make up with the seven bits (bit14 bit12 ~ bit 7)
+ * and inset the bit 13 with 0.
+ * for example, if the bit 14 and bit12 ~ bit7 is 1000001 is choosen according to the
+ * 32bit high-performance bus width with 2 banks, 11 row lwngth, 8 column length.
+ * Set devAddrMap with 0x81.
+ */
+typedef struct _emc_dynamic_chip_config
+{
+ uint8_t chipIndex; /*!< Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1. */
+ emc_dynamic_device_t
+ dynamicDevice; /*!< All chips shall use the same device setting. mixed use are not supported. */
+ uint8_t rAS_Nclk; /*!< Active to read/write delay tRCD. */
+ uint16_t sdramModeReg; /*!< Sdram mode register setting. */
+ uint16_t sdramExtModeReg; /*!< Used for low-power sdram device. The extended mode register. */
+ uint8_t devAddrMap; /*!< dynamic device address mapping, choose the address mapping for your specific device. */
+} emc_dynamic_chip_config_t;
+
+/*!
+ * @brief EMC static memory controller independent chip configuration structure.
+ */
+typedef struct _emc_static_chip_config
+{
+ uint8_t chipIndex;
+ emc_static_memwidth_t memWidth; /*!< Memory width. */
+ uint32_t specailConfig; /*!< Static configuration,a logical OR of "emc_static_special_config_t". */
+ uint32_t tWaitWriteEn_Ns; /*!< The delay form chip select to write enable in unit of nanosecond. */
+ uint32_t tWaitOutEn_Ns; /*!< The delay from chip selcet to output enable in unit of nanosecond. */
+ uint32_t
+ tWaitReadNoPage_Ns; /*!< In No-page mode, the delay from chip select to read access in unit of nanosecond. */
+ uint32_t tWaitReadPage_Ns; /*!< In page mode, the read after the first read wait states in unit of nanosecond. */
+ uint32_t tWaitWrite_Ns; /*!< The delay from chip select to write access in unit of nanosecond. */
+ uint32_t tWaitTurn_Ns; /*!< The Bus turn-around time in unit of nanosecond. */
+} emc_static_chip_config_t;
+
+/*!
+ * @brief EMC module basic configuration structure.
+ *
+ * Defines the static memory controller configure structure and
+ * uses the EMC_Init() function to make necessary initializations.
+ *
+ */
+typedef struct _emc_basic_config
+{
+ emc_endian_mode_t endian; /*!< Endian mode . */
+ emc_fbclk_src_t fbClkSrc; /*!< The feedback clock source. */
+ uint8_t emcClkDiv; /*!< EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */
+} emc_basic_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name EMC Initialize and de-initialize opeartion
+ * @{
+ */
+/*!
+ * @brief Initializes the basic for EMC.
+ * This function ungates the EMC clock, initializes the emc system configure
+ * and enable the EMC module. This function must be called in the first step to initialize
+ * the external memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param config The EMC basic configuration.
+ */
+void EMC_Init(EMC_Type *base, emc_basic_config_t *config);
+
+/*!
+ * @brief Initializes the dynamic memory controller.
+ * This function initializes the dynamic memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external dynamic memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param timing The timing and latency for dynamica memory controller setting. It shall
+ * be used for all dynamica memory chips, threfore the worst timing value for all
+ * used chips must be given.
+ * @param configure The EMC dynamic memory controller chip independent configuration pointer.
+ * This configuration pointer is actually pointer to a configration array. the array number
+ * depends on the "totalChips".
+ * @param totalChips The total dynamic memory chip numbers been used or the length of the
+ * "emc_dynamic_chip_config_t" type memory.
+ */
+void EMC_DynamicMemInit(EMC_Type *base,
+ emc_dynamic_timing_config_t *timing,
+ emc_dynamic_chip_config_t *config,
+ uint32_t totalChips);
+
+/*!
+ * @brief Initializes the static memory controller.
+ * This function initializes the static memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external static memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param extWait_Ns The extended wait timeout or the read/write transfer time.
+ * This is common for all static memory chips and set with NULL if not required.
+ * @param configure The EMC static memory controller chip independent configuration pointer.
+ * This configuration pointer is actually pointer to a configration array. the array number
+ * depends on the "totalChips".
+ * @param totalChips The total static memory chip numbers been used or the length of the
+ * "emc_static_chip_config_t" type memory.
+ */
+void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips);
+
+/*!
+ * @brief Deinitializes the EMC module and gates the clock.
+ * This function gates the EMC controller clock. As a result, the EMC
+ * module doesn't work after calling this function.
+ *
+ * @param base EMC peripheral base address.
+ */
+void EMC_Deinit(EMC_Type *base);
+
+/* @} */
+
+/*!
+ * @name EMC Basic Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the EMC module.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable EMC module, false disable.
+ */
+static inline void EMC_Enable(EMC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CONTROL |= EMC_CONTROL_E_MASK;
+ }
+ else
+ {
+ base->CONTROL &= ~EMC_CONTROL_E_MASK;
+ }
+}
+
+/*!
+ * @brief Enables/disables the EMC Dynaimc memory controller.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable EMC dynamic memory controller, false disable.
+ */
+static inline void EMC_EnableDynamicMemControl(EMC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->DYNAMICCONTROL |= (EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);
+ }
+ else
+ {
+ base->DYNAMICCONTROL &= ~(EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);
+ }
+}
+
+/*!
+ * @brief Enables/disables the EMC address mirror.
+ * Enable the address mirror the EMC_CS1is mirrored to both EMC_CS0
+ * and EMC_DYCS0 memory areas. Disable the address mirror enables
+ * EMC_cS0 and EMC_DYCS0 memory to be accessed.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable the address mirror, false disable the address mirror.
+ */
+static inline void EMC_MirrorChipAddr(EMC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CONTROL |= EMC_CONTROL_M_MASK;
+ }
+ else
+ {
+ base->CONTROL &= ~EMC_CONTROL_M_MASK;
+ }
+}
+
+/*!
+ * @brief Enter the self-refresh mode for dynamic memory controller.
+ * This function provided self-refresh mode enter or exit for application.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enter the self-refresh mode, false to exit self-refresh
+ * and enter the normal mode.
+ */
+static inline void EMC_EnterSelfRefreshCommand(EMC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->DYNAMICCONTROL |= EMC_DYNAMICCONTROL_SR_MASK;
+ }
+ else
+ {
+ base->DYNAMICCONTROL &= ~EMC_DYNAMICCONTROL_SR_MASK;
+ }
+}
+
+/*!
+ * @brief Get the operating mode of the EMC.
+ * This function can be used to get the operating mode of the EMC.
+ *
+ * @param base EMC peripheral base address.
+ * @return The EMC in self-refresh mode if true, else in normal mode.
+ */
+static inline bool EMC_IsInSelfrefreshMode(EMC_Type *base)
+{
+ return (0U != (base->STATUS & EMC_STATUS_SA_MASK));
+}
+
+/*!
+ * @brief Enter/exit the low-power mode.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True Enter the low-power mode, false exit low-power mode
+ * and return to normal mode.
+ */
+static inline void EMC_EnterLowPowerMode(EMC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CONTROL |= EMC_CONTROL_L_MASK;
+ }
+ else
+ {
+ base->CONTROL &= ~EMC_CONTROL_L_MASK;
+ }
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_EMC_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.c new file mode 100644 index 000000000..28cfb38bd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.c @@ -0,0 +1,411 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm"
+#endif
+
+/*!
+ * @brief Used for conversion between `void*` and `uint32_t`.
+ */
+typedef union pvoid_to_u32
+{
+ void *pvoid;
+ uint32_t u32;
+} pvoid_to_u32_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*! @brief Set the FLEXCOMM mode . */
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock);
+
+/*! @brief check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
+static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
+static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
+IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
+
+/*! @brief Array to map FLEXCOMM instance number to base address. */
+static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief IDs of clock for each FLEXCOMM module */
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
+/*! @brief Pointers to FLEXCOMM resets for each instance. */
+static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
+{
+ if (periph == FLEXCOMM_PERIPH_NONE)
+ {
+ return true;
+ }
+ else if (periph <= FLEXCOMM_PERIPH_I2S_TX)
+ {
+ return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false;
+ }
+ else if (periph == FLEXCOMM_PERIPH_I2S_RX)
+ {
+ return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false;
+ }
+ else
+ {
+ return false;
+ }
+}
+
+/* Get the index corresponding to the FLEXCOMM */
+/*! brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base)
+{
+ uint32_t i;
+ pvoid_to_u32_t BaseAddr;
+ BaseAddr.pvoid = base;
+
+ for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
+ {
+ if (BaseAddr.u32 == s_flexcommBaseAddrs[i])
+ {
+ break;
+ }
+ }
+
+ assert(i < FSL_FEATURE_SOC_FLEXCOMM_COUNT);
+ return i;
+}
+
+/* Changes FLEXCOMM mode */
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
+{
+ /* Check whether peripheral type is present */
+ if (!FLEXCOMM_PeripheralIsPresent(base, periph))
+ {
+ return kStatus_OutOfRange;
+ }
+
+ /* Flexcomm is locked to different peripheral type than expected */
+ if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) &&
+ ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph))
+ {
+ return kStatus_Fail;
+ }
+
+ /* Check if we are asked to lock */
+ if (lock != 0)
+ {
+ base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
+ }
+ else
+ {
+ base->PSELID = (uint32_t)periph;
+ }
+
+ return kStatus_Success;
+}
+
+/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
+{
+ uint32_t idx = FLEXCOMM_GetInstance(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Enable the peripheral clock */
+ CLOCK_EnableClock(s_flexcommClocks[idx]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
+ /* Reset the FLEXCOMM module */
+ RESET_PeripheralReset(s_flexcommResets[idx]);
+#endif
+
+ /* Set the FLEXCOMM to given peripheral */
+ return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
+}
+
+/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(base);
+
+ /* Clear handler first to avoid execution of the handler with wrong handle */
+ s_flexcommIrqHandler[instance] = NULL;
+ s_flexcommHandle[instance] = handle;
+ s_flexcommIrqHandler[instance] = handler;
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(FLEXCOMM0)
+void FLEXCOMM0_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[0]);
+ s_flexcommIrqHandler[0]((uint32_t *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM1)
+void FLEXCOMM1_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[1]);
+ s_flexcommIrqHandler[1]((uint32_t *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM2)
+void FLEXCOMM2_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[2]);
+ s_flexcommIrqHandler[2]((uint32_t *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM3)
+void FLEXCOMM3_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[3]);
+ s_flexcommIrqHandler[3]((uint32_t *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM4)
+void FLEXCOMM4_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[4]);
+ s_flexcommIrqHandler[4]((uint32_t *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+#endif
+
+#if defined(FLEXCOMM5)
+void FLEXCOMM5_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[5]);
+ s_flexcommIrqHandler[5]((uint32_t *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM6)
+void FLEXCOMM6_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[6]);
+ s_flexcommIrqHandler[6]((uint32_t *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM7)
+void FLEXCOMM7_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[7]);
+ s_flexcommIrqHandler[7]((uint32_t *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM8)
+void FLEXCOMM8_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[8]);
+ s_flexcommIrqHandler[8]((uint32_t *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM9)
+void FLEXCOMM9_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[9]);
+ s_flexcommIrqHandler[9]((uint32_t *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM10)
+void FLEXCOMM10_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[10]);
+ s_flexcommIrqHandler[10]((uint32_t *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM11)
+void FLEXCOMM11_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[11]);
+ s_flexcommIrqHandler[11]((uint32_t *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM12)
+void FLEXCOMM12_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[12]);
+ s_flexcommIrqHandler[12]((uint32_t *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM13)
+void FLEXCOMM13_DriverIRQHandler(void)
+{
+ assert(s_flexcommIrqHandler[13]);
+ s_flexcommIrqHandler[13]((uint32_t *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM14)
+void FLEXCOMM14_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM14);
+ assert(s_flexcommIrqHandler[instance]);
+ s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM15)
+void FLEXCOMM15_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM15);
+ assert(s_flexcommIrqHandler[instance]);
+ s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM16)
+void FLEXCOMM16_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM16);
+ assert(s_flexcommIrqHandler[instance]);
+ s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.h new file mode 100644 index 000000000..6fa82b415 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.h @@ -0,0 +1,64 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FLEXCOMM_H_
+#define _FSL_FLEXCOMM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexcomm_driver
+ * @{
+ */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexCOMM driver version 2.0.2. */
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*! @brief FLEXCOMM peripheral modes. */
+typedef enum
+{
+ FLEXCOMM_PERIPH_NONE, /*!< No peripheral */
+ FLEXCOMM_PERIPH_USART, /*!< USART peripheral */
+ FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */
+ FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */
+ FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
+ FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
+} FLEXCOMM_PERIPH_T;
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
+
+/*! @brief Array with IRQ number for each FLEXCOMM module. */
+extern IRQn_Type const kFlexcommIrqs[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base);
+
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
+
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_FLEXCOMM_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_gpio.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_gpio.c new file mode 100644 index 000000000..ed74b465e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_gpio.c @@ -0,0 +1,302 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+/*! @brief Pointers to GPIO resets for each instance. */
+static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
+#endif
+/*******************************************************************************
+ * Prototypes
+ ************ ******************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * param base GPIO peripheral base pointer.
+ * param port GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ assert(port < ARRAY_SIZE(s_gpioClockName));
+
+ /* Upgate the GPIO clock */
+ CLOCK_EnableClock(s_gpioClockName[port]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+ /* Reset the GPIO module */
+ RESET_PeripheralReset(s_gpioResets[port]);
+#endif
+}
+
+/*!
+ * brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalInput,
+ * 0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalOutput,
+ * 0,
+ * }
+ * endcode
+ *
+ * param base GPIO peripheral base pointer(Typically GPIO)
+ * param port GPIO port number
+ * param pin GPIO pin number
+ * param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
+{
+ if (config->pinDirection == kGPIO_DigitalInput)
+ {
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+ base->DIRCLR[port] = 1UL << pin;
+#else
+ base->DIR[port] &= ~(1UL << pin);
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
+ }
+ else
+ {
+ /* Set default output value */
+ if (config->outputLogic == 0U)
+ {
+ base->CLR[port] = (1UL << pin);
+ }
+ else
+ {
+ base->SET[port] = (1UL << pin);
+ }
+/* Set pin direction */
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+ base->DIRSET[port] = 1UL << pin;
+#else
+ base->DIR[port] |= 1UL << pin;
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
+ }
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
+/*!
+ * @brief Configures the gpio pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration..
+ */
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config)
+{
+ base->INTEDG[port] = base->INTEDG[port] | ((uint32_t)config->mode << pin);
+
+ base->INTPOL[port] = base->INTPOL[port] | ((uint32_t)config->polarity << pin);
+}
+
+/*!
+ * @brief Enables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTENA[port] = base->INTENA[port] | mask;
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTENB[port] = base->INTENB[port] | mask;
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+
+/*!
+ * @brief Disables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTENA[port] = base->INTENA[port] & ~mask;
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTENB[port] = base->INTENB[port] & ~mask;
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+
+/*!
+ * @brief Clears multiple pins interrupt flag. Status flags are cleared by
+ * writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTSTATA[port] = mask;
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTSTATB[port] = mask;
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+
+/*!
+ * @ Read port interrupt status.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param index GPIO interrupt number.
+ * @retval masked GPIO status value
+ */
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index)
+{
+ uint32_t status = 0U;
+
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ status = base->INTSTATA[port];
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ status = base->INTSTATB[port];
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+ return status;
+}
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTENA[port] = base->INTENA[port] | (1UL << pin);
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTENB[port] = base->INTENB[port] | (1UL << pin);
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTENA[port] = base->INTENA[port] & ~(1UL << pin);
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTENB[port] = base->INTENB[port] & ~(1UL << pin);
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+
+/*!
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by
+ * writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTSTATA[port] = 1UL << pin;
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTSTATB[port] = 1UL << pin;
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_gpio.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_gpio.h new file mode 100644 index 000000000..39dd2f488 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_gpio.h @@ -0,0 +1,364 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _LPC_GPIO_H_
+#define _LPC_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_gpio
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPC GPIO driver version. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
+/*@}*/
+
+/*! @brief LPC GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+ kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
+ kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Every pin can only be configured as either output pin or input pin at a time.
+ * If configured as a input pin, then leave the outputConfig unused.
+ */
+typedef struct _gpio_pin_config
+{
+ gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+ /* Output configurations, please ignore if configured as a input one */
+ uint8_t outputLogic; /*!< Set default output logic, no use in input */
+} gpio_pin_config_t;
+
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
+#define GPIO_PIN_INT_LEVEL 0x00U
+#define GPIO_PIN_INT_EDGE 0x01U
+
+#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U
+#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U
+
+/*! @brief GPIO Pin Interrupt enable mode */
+typedef enum _gpio_pin_enable_mode
+{
+ kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */
+ kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */
+} gpio_pin_enable_mode_t;
+
+/*! @brief GPIO Pin Interrupt enable polarity */
+typedef enum _gpio_pin_enable_polarity
+{
+ kGPIO_PinIntEnableHighOrRise =
+ PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */
+ kGPIO_PinIntEnableLowOrFall =
+ PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */
+} gpio_pin_enable_polarity_t;
+
+/*! @brief LPC GPIO interrupt index definition */
+typedef enum _gpio_interrupt_index
+{
+ kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/
+ kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/
+} gpio_interrupt_index_t;
+
+/*! @brief Configures the interrupt generation condition. */
+typedef struct _gpio_interrupt_config
+{
+ uint8_t mode; /* The trigger mode of GPIO interrupts */
+ uint8_t polarity; /* The polarity of GPIO interrupts */
+} gpio_interrupt_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * @param base GPIO peripheral base pointer.
+ * @param port GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port);
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalInput,
+ * 0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalOutput,
+ * 0,
+ * }
+ * @endcode
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param pin GPIO pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param pin GPIO pin number
+ * @param output GPIO pin output logic level.
+ * - 0: corresponding pin output low-logic level.
+ * - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
+{
+ base->B[port][pin] = output;
+}
+
+/*@}*/
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the GPIO PIN.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param pin GPIO pin number
+ * @retval GPIO port input value
+ * - 0: corresponding pin input low-logic level.
+ * - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)
+{
+ return (uint32_t)base->B[port][pin];
+}
+
+/*@}*/
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->SET[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->CLR[port] = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->NOT[port] = mask;
+}
+
+/*@}*/
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ */
+static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)
+{
+ return (uint32_t)base->PIN[port];
+}
+
+/*@}*/
+/*! @name GPIO Mask Operations */
+/*@{*/
+
+/*!
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->MASK[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param output GPIO port output value.
+ */
+static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)
+{
+ base->MPIN[port] = output;
+}
+
+/*!
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
+ * affected.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @retval masked GPIO port value
+ */
+static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
+{
+ return (uint32_t)base->MPIN[port];
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
+/*!
+ * @brief Configures the gpio pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration..
+ */
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config);
+
+/*!
+ * @brief Enables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @brief Disables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @brief Clears pin interrupt flag. Status flags are cleared by
+ * writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @ Read port interrupt status.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param index GPIO interrupt number.
+ * @retval masked GPIO status value
+ */
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index);
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+/*!
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by
+ * writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _LPC_GPIO_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_iocon.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_iocon.h new file mode 100644 index 000000000..0386ecb4f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_iocon.h @@ -0,0 +1,288 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOCON_H_
+#define _FSL_IOCON_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_iocon
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOCON driver version 2.1.1. */
+#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+/**
+ * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
+ */
+typedef struct _iocon_group
+{
+ uint32_t port : 8; /* Pin port */
+ uint32_t pin : 8; /* Pin number */
+ uint32_t ionumber : 8; /* IO number */
+ uint32_t modefunc : 16; /* Function and mode */
+} iocon_group_t;
+
+/**
+ * @brief IOCON function and mode selection definitions
+ * @note See the User Manual for specific modes and functions supported by the various pins.
+ */
+#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4)
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
+#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */
+#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */
+#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */
+#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */
+#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */
+#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */
+#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */
+#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */
+#if defined(IOCON_PIO_MODE_SHIFT)
+#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
+#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
+#endif
+
+#if defined(IOCON_PIO_I2CSLEW_SHIFT)
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */
+#endif
+
+#if defined(IOCON_PIO_EGP_SHIFT)
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */
+#endif
+
+#if defined(IOCON_PIO_SLEW_SHIFT)
+#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
+#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
+#endif
+
+#if defined(IOCON_PIO_INVERT_SHIFT)
+#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */
+#endif
+
+#if defined(IOCON_PIO_DIGIMODE_SHIFT)
+#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */
+#define IOCON_DIGITAL_EN \
+ (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */
+#endif
+
+#if defined(IOCON_PIO_FILTEROFF_SHIFT)
+#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
+#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */
+#endif
+
+#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
+#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */
+#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
+#endif
+
+#if defined(IOCON_PIO_OD_SHIFT)
+#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */
+#endif
+
+#if defined(IOCON_PIO_I2CFILTER_SHIFT)
+#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */
+#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */
+#endif
+
+#if defined(IOCON_PIO_ASW_SHIFT)
+#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */
+#endif
+
+#if defined(IOCON_PIO_SSEL_SHIFT)
+#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */
+#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */
+#endif
+
+#if defined(IOCON_PIO_ECS_SHIFT)
+#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */
+#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */
+#endif
+
+#if defined(IOCON_PIO_S_MODE_SHIFT)
+#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
+#define IOCON_S_MODE_1CLK \
+ (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
+ */
+#define IOCON_S_MODE_2CLK \
+ (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
+ */
+#define IOCON_S_MODE_3CLK \
+ (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
+ */
+#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
+#endif
+
+#if defined(IOCON_PIO_CLK_DIV_SHIFT)
+#define IOCON_CLKDIV(div) \
+ ((div) \
+ << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+#endif
+
+#else
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
+
+#if defined(IOCON_PIO_MODE_SHIFT)
+#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
+#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
+#endif
+
+#if defined(IOCON_PIO_I2CSLEW_SHIFT)
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */
+#endif
+
+#if defined(IOCON_PIO_EGP_SHIFT)
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */
+#endif
+
+#if defined(IOCON_PIO_INVERT_SHIFT)
+#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */
+#endif
+
+#if defined(IOCON_PIO_DIGIMODE_SHIFT)
+#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */
+#define IOCON_DIGITAL_EN \
+ (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */
+#endif
+
+#if defined(IOCON_PIO_FILTEROFF_SHIFT)
+#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
+#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */
+#endif
+
+#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
+#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */
+#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
+#endif
+
+#if defined(IOCON_PIO_OD_SHIFT)
+#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */
+#endif
+
+#if defined(IOCON_PIO_I2CFILTER_SHIFT)
+#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */
+#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */
+#endif
+
+#if defined(IOCON_PIO_S_MODE_SHIFT)
+#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
+#define IOCON_S_MODE_1CLK \
+ (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
+ */
+#define IOCON_S_MODE_2CLK \
+ (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
+ */
+#define IOCON_S_MODE_3CLK \
+ (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
+ */
+#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
+#endif
+
+#if defined(IOCON_PIO_CLK_DIV_SHIFT)
+#define IOCON_CLKDIV(div) \
+ ((div) \
+ << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+#endif
+
+#endif
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1))
+/**
+ * @brief Sets I/O Control pin mux
+ * @param base : The base of IOCON peripheral on the chip
+ * @param ionumber : GPIO number to mux
+ * @param modefunc : OR'ed values of type IOCON_*
+ * @return Nothing
+ */
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc)
+{
+ base->PIO[ionumber] = modefunc;
+}
+#else
+/**
+ * @brief Sets I/O Control pin mux
+ * @param base : The base of IOCON peripheral on the chip
+ * @param port : GPIO port to mux
+ * @param pin : GPIO pin to mux
+ * @param modefunc : OR'ed values of type IOCON_*
+ * @return Nothing
+ */
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
+{
+ base->PIO[port][pin] = modefunc;
+}
+#endif
+
+/**
+ * @brief Set all I/O Control pin muxing
+ * @param base : The base of IOCON peripheral on the chip
+ * @param pinArray : Pointer to array of pin mux selections
+ * @param arrayLength : Number of entries in pinArray
+ * @return Nothing
+ */
+__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
+{
+ uint32_t i;
+
+ for (i = 0; i < arrayLength; i++)
+ {
+#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1))
+ IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc);
+#else
+ IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
+#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */
+ }
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_IOCON_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_power.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_power.c new file mode 100644 index 000000000..92ca474e9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_power.c @@ -0,0 +1,20 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_common.h"
+#include "fsl_power.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.power"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Empty file since implementation is in header file and power library */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_power.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_power.h new file mode 100644 index 000000000..6e19262a6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_power.h @@ -0,0 +1,225 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_POWER_H_
+#define _FSL_POWER_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup power */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief power driver version 2.0.0. */
+#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
+#define PDRCFG0 0x0U
+#define PDRCFG1 0x1U
+
+typedef enum pd_bits
+{
+ kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U),
+ kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
+ kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U),
+ kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
+ kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
+ kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U),
+ kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
+ kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
+ kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
+ kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
+ kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U),
+ kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
+ kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
+ kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
+ kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
+ kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
+ kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
+ kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
+ kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U),
+ kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U),
+ kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U),
+ kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U),
+ kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U),
+ kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U),
+
+ kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U),
+ kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U),
+ kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U),
+ kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U),
+ kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U),
+ kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U),
+
+ /*
+ This enum member has no practical meaning,it is used to avoid MISRA issue,
+ user should not trying to use it.
+ */
+ kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
+} pd_bit_t;
+
+/* Power mode configuration API parameter */
+typedef enum _power_mode_config
+{
+ kPmu_Sleep = 0U,
+ kPmu_Deep_Sleep = 1U,
+ kPmu_Deep_PowerDown = 2U,
+} power_mode_cfg_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+* @name Power Configuration
+* @{
+*/
+
+/*!
+ * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
+ *
+ * @param en peripheral for which to enable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_EnablePD(pd_bit_t en)
+{
+ /* PDRUNCFGSET */
+ SYSCON->PDRUNCFGSET[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
+}
+
+/*!
+ * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
+ *
+ * @param en peripheral for which to disable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_DisablePD(pd_bit_t en)
+{
+ /* PDRUNCFGCLR */
+ SYSCON->PDRUNCFGCLR[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
+}
+
+/*!
+ * @brief API to enable deep sleep bit in the ARM Core.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_EnableDeepSleep(void)
+{
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief API to disable deep sleep bit in the ARM Core.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_DisableDeepSleep(void)
+{
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief Power Library API to reload OTP.
+ * This API must be called if VD6 is power down
+ * and power back again since FROHF TRIM value
+ * is store in OTP. If not, when calling FROHF settng
+ * API in clock driver then the FROHF clock out put
+ * will be inaccurate.
+ * @return none
+ */
+void POWER_OtpReload(void);
+
+/*!
+ * @brief Power Library API to power the PLLs.
+ *
+ * @param none
+ * @return none
+ */
+void POWER_SetPLL(void);
+
+/*!
+ * @brief Power Library API to power the USB PHY.
+ *
+ * @param none
+ * @return none
+ */
+void POWER_SetUsbPhy(void);
+
+/*!
+ * @brief Power Library API to enter different power mode.
+ *
+ * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
+ * during power mode selected.
+ * @return none
+ */
+void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter sleep mode.
+ *
+ * @return none
+ */
+void POWER_EnterSleep(void);
+
+/*!
+ * @brief Power Library API to enter deep sleep mode.
+ *
+ * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be
+ * powered on during deep sleep
+ * @return none
+ */
+void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter deep power down mode.
+ *
+ * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
+ during deep power
+ * down mode, but this is has no effect as the voltages are cut off.
+
+ * @return none
+ */
+void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
+ *
+ * @param freq - The desired frequency at which the part would like to operate,
+ * note that the voltage and flash wait states should be set before changing frequency
+ * @return none
+ */
+void POWER_SetVoltageForFreq(uint32_t freq);
+
+/*!
+ * @brief Power Library API to return the library version.
+ *
+ * @param none
+ * @return version number of the power library
+ */
+uint32_t POWER_GetLibVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FSL_POWER_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_reset.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_reset.c new file mode 100644 index 000000000..6c000500e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_reset.c @@ -0,0 +1,132 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.reset"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+ (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+
+/*!
+ * brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+ const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+ const uint32_t bitMask = 1UL << bitPos;
+
+ assert(bitPos < 32UL);
+
+ /* ASYNC_SYSCON registers have offset 1024 */
+ if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+ {
+ /* reset register is in ASYNC_SYSCON */
+
+ /* set bit */
+ ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;
+ /* wait until it reads 0b1 */
+ while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+ {
+ }
+ }
+ else
+ {
+ /* reset register is in SYSCON */
+
+ /* set bit */
+ SYSCON->PRESETCTRLSET[regIndex] = bitMask;
+ /* wait until it reads 0b1 */
+ while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+ {
+ }
+ }
+}
+
+/*!
+ * brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+ const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+ const uint32_t bitMask = 1UL << bitPos;
+
+ assert(bitPos < 32UL);
+
+ /* ASYNC_SYSCON registers have offset 1024 */
+ if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+ {
+ /* reset register is in ASYNC_SYSCON */
+
+ /* clear bit */
+ ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;
+ /* wait until it reads 0b0 */
+ while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+ {
+ }
+ }
+ else
+ {
+ /* reset register is in SYSCON */
+
+ /* clear bit */
+ SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
+ /* wait until it reads 0b0 */
+ while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+ {
+ }
+ }
+}
+
+/*!
+ * brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+ RESET_SetPeripheralReset(peripheral);
+ RESET_ClearPeripheralReset(peripheral);
+}
+
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_reset.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_reset.h new file mode 100644 index 000000000..75dc0a582 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_reset.h @@ -0,0 +1,277 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_RESET_H_
+#define _FSL_RESET_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*! @addtogroup reset */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief reset driver version 2.0.1. */
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*!
+ * @brief Enumeration for peripheral reset control bits
+ *
+ * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
+ */
+typedef enum _SYSCON_RSTn
+{
+ kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */
+ kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */
+ kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */
+ kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */
+ kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */
+ kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */
+ kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */
+ kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */
+ kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */
+ kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */
+ kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */
+ kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */
+ kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */
+
+ kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
+ kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */
+ kMCAN0_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN0 reset control */
+ kMCAN1_RST_SHIFT_RSTn = 65536 | 8U, /**< MCAN1 reset control */
+ kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
+ kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
+ kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
+ kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
+ kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
+ kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
+ kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
+ kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
+ kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
+ kDMIC_RST_SHIFT_RSTn = 65536 | 19U, /**< Digital microphone interface reset control */
+ kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */
+ kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0D reset control */
+ kCT32B0_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B0 reset control */
+ kCT32B1_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B1 reset control */
+
+ kLCD_RST_SHIFT_RSTn = 131072 | 2U, /**< LCD reset control */
+ kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */
+ kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USB1H reset control */
+ kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USB1D reset control */
+ kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB1RAM reset control */
+ kEMC_RST_SHIFT_RSTn = 131072 | 7U, /**< EMC reset control */
+ kETH_RST_SHIFT_RSTn = 131072 | 8U, /**< ETH reset control */
+ kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */
+ kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */
+ kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */
+ kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */
+ kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */
+ kFC8_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcomm Interface 8 reset control */
+ kFC9_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcomm Interface 9 reset control */
+ kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */
+ kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */
+ kSHA_RST_SHIFT_RSTn = 131072 | 18U, /**< SHA reset control */
+ kSC0_RST_SHIFT_RSTn = 131072 | 19U, /**< SC0 reset control */
+ kSC1_RST_SHIFT_RSTn = 131072 | 20U, /**< SC1 reset control */
+ kFC10_RST_SHIFT_RSTn = 131072 | 21U, /**< Flexcomm Interface 10 reset control */
+
+ kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */
+ kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */
+} SYSCON_RSTn_t;
+
+/** Array initializers with peripheral reset bits **/
+#define ADC_RSTS \
+ { \
+ kADC0_RST_SHIFT_RSTn \
+ } /* Reset bits for ADC peripheral */
+#define AES_RSTS \
+ { \
+ kAES_RST_SHIFT_RSTn \
+ } /* Reset bits for AES peripheral */
+#define CRC_RSTS \
+ { \
+ kCRC_RST_SHIFT_RSTn \
+ } /* Reset bits for CRC peripheral */
+#define CTIMER_RSTS \
+ { \
+ kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
+ kCT32B4_RST_SHIFT_RSTn \
+ } /* Reset bits for CTIMER peripheral */
+#define DMA_RSTS_N \
+ { \
+ kDMA_RST_SHIFT_RSTn \
+ } /* Reset bits for DMA peripheral */
+#define DMIC_RSTS \
+ { \
+ kDMIC_RST_SHIFT_RSTn \
+ } /* Reset bits for DMIC peripheral */
+#define EMC_RSTS \
+ { \
+ kEMC_RST_SHIFT_RSTn \
+ } /* Reset bits for EMC peripheral */
+#define ETH_RST \
+ { \
+ kETH_RST_SHIFT_RSTn \
+ } /* Reset bits for EMC peripheral */
+#define FLEXCOMM_RSTS \
+ { \
+ kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
+ kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn \
+ } /* Reset bits for FLEXCOMM peripheral */
+#define GINT_RSTS \
+ { \
+ kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
+ } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
+#define GPIO_RSTS_N \
+ { \
+ kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \
+ kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \
+ } /* Reset bits for GPIO peripheral */
+#define INPUTMUX_RSTS \
+ { \
+ kMUX_RST_SHIFT_RSTn \
+ } /* Reset bits for INPUTMUX peripheral */
+#define IOCON_RSTS \
+ { \
+ kIOCON_RST_SHIFT_RSTn \
+ } /* Reset bits for IOCON peripheral */
+#define FLASH_RSTS \
+ { \
+ kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
+ } /* Reset bits for Flash peripheral */
+#define LCD_RSTS \
+ { \
+ kLCD_RST_SHIFT_RSTn \
+ } /* Reset bits for LCD peripheral */
+#define MRT_RSTS \
+ { \
+ kMRT_RST_SHIFT_RSTn \
+ } /* Reset bits for MRT peripheral */
+#define MCAN_RSTS \
+ { \
+ kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \
+ } /* Reset bits for MCAN0&MACN1 peripheral */
+#define OTP_RSTS \
+ { \
+ kOTP_RST_SHIFT_RSTn \
+ } /* Reset bits for OTP peripheral */
+#define PINT_RSTS \
+ { \
+ kPINT_RST_SHIFT_RSTn \
+ } /* Reset bits for PINT peripheral */
+#define RNG_RSTS \
+ { \
+ kRNG_RST_SHIFT_RSTn \
+ } /* Reset bits for RNG peripheral */
+#define SDIO_RST \
+ { \
+ kSDIO_RST_SHIFT_RSTn \
+ } /* Reset bits for SDIO peripheral */
+#define SCT_RSTS \
+ { \
+ kSCT0_RST_SHIFT_RSTn \
+ } /* Reset bits for SCT peripheral */
+#define SHA_RST \
+ { \
+ kSHA_RST_SHIFT_RSTn \
+ } /* Reset bits for SHA peripheral */
+#define SPIFI_RSTS \
+ { \
+ kSPIFI_RST_SHIFT_RSTn \
+ } /* Reset bits for SPIFI peripheral */
+#define USB0D_RST \
+ { \
+ kUSB0D_RST_SHIFT_RSTn \
+ } /* Reset bits for USB0D peripheral */
+#define USB0HMR_RST \
+ { \
+ kUSB0HMR_RST_SHIFT_RSTn \
+ } /* Reset bits for USB0HMR peripheral */
+#define USB0HSL_RST \
+ { \
+ kUSB0HSL_RST_SHIFT_RSTn \
+ } /* Reset bits for USB0HSL peripheral */
+#define USB1H_RST \
+ { \
+ kUSB1H_RST_SHIFT_RSTn \
+ } /* Reset bits for USB1H peripheral */
+#define USB1D_RST \
+ { \
+ kUSB1D_RST_SHIFT_RSTn \
+ } /* Reset bits for USB1D peripheral */
+#define USB1RAM_RST \
+ { \
+ kUSB1RAM_RST_SHIFT_RSTn \
+ } /* Reset bits for USB1RAM peripheral */
+#define UTICK_RSTS \
+ { \
+ kUTICK_RST_SHIFT_RSTn \
+ } /* Reset bits for UTICK peripheral */
+#define WWDT_RSTS \
+ { \
+ kWWDT_RST_SHIFT_RSTn \
+ } /* Reset bits for WWDT peripheral */
+
+typedef SYSCON_RSTn_t reset_ip_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_RESET_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_usart.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_usart.c new file mode 100644 index 000000000..dd35da6b4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_usart.c @@ -0,0 +1,981 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart"
+#endif
+
+/*!
+ * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t`
+ */
+typedef union usart_to_flexcomm
+{
+ flexcomm_usart_irq_handler_t usart_master_handler;
+ flexcomm_irq_handler_t flexcomm_handler;
+} usart_to_flexcomm_t;
+
+enum
+{
+ kUSART_TxIdle, /* TX idle. */
+ kUSART_TxBusy, /* TX busy. */
+ kUSART_RxIdle, /* RX idle. */
+ kUSART_RxBusy /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;
+
+/*! @brief Array to map USART instance number to base address. */
+static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get the index corresponding to the USART */
+/*! brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base)
+{
+ uint32_t i;
+
+ for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++)
+ {
+ if ((uint32_t)base == s_usartBaseAddrs[i])
+ {
+ break;
+ }
+ }
+
+ assert(i < FSL_FEATURE_SOC_USART_COUNT);
+ return i;
+}
+
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * param handle USART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
+{
+ size_t size;
+
+ /* Check arguments */
+ assert(NULL != handle);
+ uint16_t rxRingBufferHead = handle->rxRingBufferHead;
+ uint16_t rxRingBufferTail = handle->rxRingBufferTail;
+
+ if (rxRingBufferTail > rxRingBufferHead)
+ {
+ size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail;
+ }
+ else
+ {
+ size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail;
+ }
+ return size;
+}
+
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)
+{
+ bool full;
+
+ /* Check arguments */
+ assert(NULL != handle);
+
+ if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+ {
+ full = true;
+ }
+ else
+ {
+ full = false;
+ }
+ return full;
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+ /* Check arguments */
+ assert(NULL != base);
+ assert(NULL != handle);
+ assert(NULL != ringBuffer);
+
+ /* Setup the ringbuffer address */
+ handle->rxRingBuffer = ringBuffer;
+ handle->rxRingBufferSize = ringBufferSize;
+ handle->rxRingBufferHead = 0U;
+ handle->rxRingBufferTail = 0U;
+ /* ring buffer is ready we can start receiving data */
+ base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)
+{
+ /* Check arguments */
+ assert(NULL != base);
+ assert(NULL != handle);
+
+ if (handle->rxState == (uint8_t)kUSART_RxIdle)
+ {
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;
+ }
+ handle->rxRingBuffer = NULL;
+ handle->rxRingBufferSize = 0U;
+ handle->rxRingBufferHead = 0U;
+ handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * code
+ * usart_config_t usartConfig;
+ * usartConfig.baudRate_Bps = 115200U;
+ * usartConfig.parityMode = kUSART_ParityDisabled;
+ * usartConfig.stopBitCount = kUSART_OneStopBit;
+ * USART_Init(USART1, &usartConfig, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param config Pointer to user-defined configuration structure.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_InvalidArgument USART base address is not valid
+ * retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)
+{
+ int result;
+
+ /* check arguments */
+ assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz)));
+ if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* initialize flexcomm to USART mode */
+ result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);
+ if (kStatus_Success != result)
+ {
+ return result;
+ }
+
+ if (config->enableTx)
+ {
+ /* empty and enable txFIFO */
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;
+ /* setup trigger level */
+ base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);
+ base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);
+ /* enable trigger interrupt */
+ base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;
+ }
+
+ /* empty and enable rxFIFO */
+ if (config->enableRx)
+ {
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;
+ /* setup trigger level */
+ base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);
+ base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);
+ /* enable trigger interrupt */
+ base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;
+ }
+ /* setup configuration and enable USART */
+ base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
+ USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) |
+ USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) |
+ USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_ENABLE_MASK;
+
+ /* Setup baudrate */
+ result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+ if (kStatus_Success != result)
+ {
+ return result;
+ }
+ /* Setting continuous Clock configuration. used for synchronous mode. */
+ USART_EnableContinuousSCLK(base, config->enableContinuousSCLK);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base)
+{
+ /* Check arguments */
+ assert(NULL != base);
+ while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+ {
+ }
+ /* Disable interrupts, disable dma requests, disable peripheral */
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |
+ USART_FIFOINTENCLR_RXLVL_MASK;
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);
+ base->CFG &= ~(USART_CFG_ENABLE_MASK);
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ * usartConfig->baudRate_Bps = 115200U;
+ * usartConfig->parityMode = kUSART_ParityDisabled;
+ * usartConfig->stopBitCount = kUSART_OneStopBit;
+ * usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ * usartConfig->loopback = false;
+ * usartConfig->enableTx = false;
+ * usartConfig->enableRx = false;
+ *
+ * param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config)
+{
+ /* Check arguments */
+ assert(NULL != config);
+
+ /* Initializes the configure structure to zero. */
+ (void)memset(config, 0, sizeof(*config));
+
+ /* Set always all members ! */
+ config->baudRate_Bps = 115200U;
+ config->parityMode = kUSART_ParityDisabled;
+ config->stopBitCount = kUSART_OneStopBit;
+ config->bitCountPerChar = kUSART_8BitsPerChar;
+ config->loopback = false;
+ config->enableRx = false;
+ config->enableTx = false;
+ config->txWatermark = kUSART_TxFifo0;
+ config->rxWatermark = kUSART_RxFifo1;
+ config->syncMode = kUSART_SyncModeDisabled;
+ config->enableContinuousSCLK = false;
+ config->clockPolarity = kUSART_RxSampleOnFallingEdge;
+}
+
+/*!
+ * brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * code
+ * USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param baudrate_Bps USART baudrate to be set.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+ uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;
+ uint32_t osrval, brgval, diff, baudrate;
+
+ /* check arguments */
+ assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
+ if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* If synchronous master mode is enabled, only configure the BRG value. */
+ if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U)
+ {
+ if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U)
+ {
+ brgval = srcClock_Hz / baudrate_Bps;
+ base->BRG = brgval - 1U;
+ }
+ }
+ else
+ {
+ /*
+ * Smaller values of OSR can make the sampling position within a data bit less accurate and may
+ * potentially cause more noise errors or incorrect data.
+ */
+ for (osrval = best_osrval; osrval >= 8U; osrval--)
+ {
+ brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U;
+ if (brgval > 0xFFFFU)
+ {
+ continue;
+ }
+ baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U));
+ diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;
+ if (diff < best_diff)
+ {
+ best_diff = diff;
+ best_osrval = osrval;
+ best_brgval = brgval;
+ }
+ }
+
+ /* value over range */
+ if (best_brgval > 0xFFFFU)
+ {
+ return kStatus_USART_BaudrateNotSupport;
+ }
+
+ base->OSR = best_osrval;
+ base->BRG = best_brgval;
+ }
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ */
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
+{
+ /* Check arguments */
+ assert(!((NULL == base) || (NULL == data)));
+ if ((NULL == base) || (NULL == data))
+ {
+ return;
+ }
+ /* Check whether txFIFO is enabled */
+ if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
+ {
+ return;
+ }
+ for (; length > 0U; length--)
+ {
+ /* Loop until txFIFO get some space for new data */
+ while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+ {
+ }
+ base->FIFOWR = *data;
+ data++;
+ }
+ /* Wait to finish transfer */
+ while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+ {
+ }
+}
+
+/*!
+ * brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
+{
+ uint32_t statusFlag;
+ status_t status = kStatus_Success;
+
+ /* check arguments */
+ assert(!((NULL == base) || (NULL == data)));
+ if ((NULL == base) || (NULL == data))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* Check whether rxFIFO is enabled */
+ if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U)
+ {
+ return kStatus_Fail;
+ }
+ for (; length > 0U; length--)
+ {
+ /* loop until rxFIFO have some data to read */
+ while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U)
+ {
+ }
+ /* check rxFIFO statusFlag */
+ if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
+ {
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+ base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+ status = kStatus_USART_RxError;
+ break;
+ }
+ /* check receive statusFlag */
+ statusFlag = base->STAT;
+ /* Clear all status flags */
+ base->STAT |= statusFlag;
+ if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U)
+ {
+ status = kStatus_USART_ParityError;
+ }
+ if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U)
+ {
+ status = kStatus_USART_FramingError;
+ }
+ if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U)
+ {
+ status = kStatus_USART_NoiseError;
+ }
+
+ if (kStatus_Success == status)
+ {
+ *data = (uint8_t)base->FIFORD;
+ data++;
+ }
+ else
+ {
+ break;
+ }
+ }
+ return status;
+}
+
+/*!
+ * brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+ usart_handle_t *handle,
+ usart_transfer_callback_t callback,
+ void *userData)
+{
+ /* Check 'base' */
+ assert(!((NULL == base) || (NULL == handle)));
+
+ uint32_t instance = 0;
+ usart_to_flexcomm_t handler;
+ handler.usart_master_handler = USART_TransferHandleIRQ;
+
+ if ((NULL == base) || (NULL == handle))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ instance = USART_GetInstance(base);
+
+ (void)memset(handle, 0, sizeof(*handle));
+ /* Set the TX/RX state. */
+ handle->rxState = (uint8_t)kUSART_RxIdle;
+ handle->txState = (uint8_t)kUSART_TxIdle;
+ /* Set the callback and user data. */
+ handle->callback = callback;
+ handle->userData = userData;
+ handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base);
+ handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base);
+
+ FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle);
+
+ /* Enable interrupt in NVIC. */
+ (void)EnableIRQ(s_usartIRQ[instance]);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the ref kStatus_USART_TxIdle as status parameter.
+ *
+ * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure. See #usart_transfer_t.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)
+{
+ /* Check arguments */
+ assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+ if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+ {
+ return kStatus_InvalidArgument;
+ }
+ /* Check xfer members */
+ assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+ if ((0U == xfer->dataSize) || (NULL == xfer->data))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* Return error if current TX busy. */
+ if ((uint8_t)kUSART_TxBusy == handle->txState)
+ {
+ return kStatus_USART_TxBusy;
+ }
+ else
+ {
+ handle->txData = xfer->data;
+ handle->txDataSize = xfer->dataSize;
+ handle->txDataSizeAll = xfer->dataSize;
+ handle->txState = (uint8_t)kUSART_TxBusy;
+ /* Enable transmiter interrupt. */
+ base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;
+ }
+ return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ /* Disable interrupts */
+ USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable);
+ /* Empty txFIFO */
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;
+
+ handle->txDataSize = 0U;
+ handle->txState = (uint8_t)kUSART_TxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been written to USART TX register.
+ *
+ * This function gets the number of bytes that have been written to USART TX
+ * register by interrupt method.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+ assert(NULL != handle);
+ assert(NULL != count);
+
+ if ((uint8_t)kUSART_TxIdle == handle->txState)
+ {
+ return kStatus_NoTransferInProgress;
+ }
+
+ *count = handle->txDataSizeAll - handle->txDataSize;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure, see #usart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+ usart_handle_t *handle,
+ usart_transfer_t *xfer,
+ size_t *receivedBytes)
+{
+ uint32_t i;
+ /* How many bytes to copy from ring buffer to user memory. */
+ size_t bytesToCopy = 0U;
+ /* How many bytes to receive. */
+ size_t bytesToReceive;
+ /* How many bytes currently have received. */
+ size_t bytesCurrentReceived;
+ uint32_t regPrimask = 0U;
+
+ /* Check arguments */
+ assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+ if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+ {
+ return kStatus_InvalidArgument;
+ }
+ /* Check xfer members */
+ assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+ if ((0U == xfer->dataSize) || (NULL == xfer->data))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* How to get data:
+ 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+ to uart handle, enable interrupt to store received data to xfer->data. When
+ all data received, trigger callback.
+ 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+ If there are enough data in ring buffer, copy them to xfer->data and return.
+ If there are not enough data in ring buffer, copy all of them to xfer->data,
+ save the xfer->data remained empty space to uart handle, receive data
+ to this empty space and trigger callback when finished. */
+ if ((uint8_t)kUSART_RxBusy == handle->rxState)
+ {
+ return kStatus_USART_RxBusy;
+ }
+ else
+ {
+ bytesToReceive = xfer->dataSize;
+ bytesCurrentReceived = 0U;
+ /* If RX ring buffer is used. */
+ if (handle->rxRingBuffer != NULL)
+ {
+ /* Disable IRQ, protect ring buffer. */
+ regPrimask = DisableGlobalIRQ();
+ /* How many bytes in RX ring buffer currently. */
+ bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
+ if (bytesToCopy != 0U)
+ {
+ bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+ bytesToReceive -= bytesToCopy;
+ /* Copy data from ring buffer to user memory. */
+ for (i = 0U; i < bytesToCopy; i++)
+ {
+ xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+ /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+ if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferTail = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferTail++;
+ }
+ }
+ }
+ /* If ring buffer does not have enough data, still need to read more data. */
+ if (bytesToReceive != 0U)
+ {
+ /* No data in ring buffer, save the request to UART handle. */
+ handle->rxData = xfer->data + bytesCurrentReceived;
+ handle->rxDataSize = bytesToReceive;
+ handle->rxDataSizeAll = bytesToReceive;
+ handle->rxState = (uint8_t)kUSART_RxBusy;
+ }
+ /* Enable IRQ if previously enabled. */
+ EnableGlobalIRQ(regPrimask);
+ /* Call user callback since all data are received. */
+ if (0U == bytesToReceive)
+ {
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+ }
+ }
+ }
+ /* Ring buffer not used. */
+ else
+ {
+ handle->rxData = xfer->data + bytesCurrentReceived;
+ handle->rxDataSize = bytesToReceive;
+ handle->rxDataSizeAll = bytesToReceive;
+ handle->rxState = (uint8_t)kUSART_RxBusy;
+
+ /* Enable RX interrupt. */
+ base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;
+ }
+ /* Return the how many bytes have read. */
+ if (receivedBytes != NULL)
+ {
+ *receivedBytes = bytesCurrentReceived;
+ }
+ }
+ return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+ if (NULL == handle->rxRingBuffer)
+ {
+ /* Disable interrupts */
+ USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable);
+ /* Empty rxFIFO */
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+ }
+
+ handle->rxDataSize = 0U;
+ handle->rxState = (uint8_t)kUSART_RxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+ assert(NULL != handle);
+ assert(NULL != count);
+
+ if ((uint8_t)kUSART_RxIdle == handle->rxState)
+ {
+ return kStatus_NoTransferInProgress;
+ }
+
+ *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
+{
+ /* Check arguments */
+ assert((NULL != base) && (NULL != handle));
+
+ bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));
+ bool sendEnabled = (handle->txDataSize != 0U);
+ uint8_t rxdata;
+ size_t tmpsize;
+
+ /* If RX overrun. */
+ if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
+ {
+ /* Clear rx error state. */
+ base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+ /* clear rxFIFO */
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+ /* Trigger callback. */
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_USART_RxError, handle->userData);
+ }
+ }
+ while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) ||
+ (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)))
+ {
+ /* Receive data */
+ if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U))
+ {
+ /* Receive to app bufffer if app buffer is present */
+ if (handle->rxDataSize != 0U)
+ {
+ rxdata = (uint8_t)base->FIFORD;
+ *handle->rxData = rxdata;
+ handle->rxDataSize--;
+ handle->rxData++;
+ receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));
+ if (0U == handle->rxDataSize)
+ {
+ if (NULL == handle->rxRingBuffer)
+ {
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+ }
+ handle->rxState = (uint8_t)kUSART_RxIdle;
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+ }
+ }
+ }
+ /* Otherwise receive to ring buffer if ring buffer is present */
+ else
+ {
+ if (handle->rxRingBuffer != NULL)
+ {
+ /* If RX ring buffer is full, trigger callback to notify over run. */
+ if (USART_TransferIsRxRingBufferFull(handle))
+ {
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);
+ }
+ }
+ /* If ring buffer is still full after callback function, the oldest data is overridden. */
+ if (USART_TransferIsRxRingBufferFull(handle))
+ {
+ /* Increase handle->rxRingBufferTail to make room for new data. */
+ if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferTail = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferTail++;
+ }
+ }
+ /* Read data. */
+ rxdata = (uint8_t)base->FIFORD;
+ handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata;
+ /* Increase handle->rxRingBufferHead. */
+ if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferHead = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferHead++;
+ }
+ }
+ }
+ }
+ /* Send data */
+ if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))
+ {
+ base->FIFOWR = *handle->txData;
+ handle->txDataSize--;
+ handle->txData++;
+ sendEnabled = handle->txDataSize != 0U;
+ if (!sendEnabled)
+ {
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+ handle->txState = (uint8_t)kUSART_TxIdle;
+
+ base->INTENSET |= USART_INTENSET_TXIDLEEN_MASK;
+ }
+ }
+ }
+
+ /* Tx idle and the interrupt is enabled. */
+ if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) &&
+ (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK)) && (handle->txState == (uint8_t)kUSART_TxIdle))
+ {
+ /* Disable tx idle interrupt */
+ base->INTENCLR |= USART_INTENCLR_TXIDLECLR_MASK;
+ /* Trigger callback. */
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);
+ }
+ }
+
+ /* ring buffer is not used */
+ if (NULL == handle->rxRingBuffer)
+ {
+ tmpsize = handle->rxDataSize;
+
+ /* restore if rx transfer ends and rxLevel is different from default value */
+ if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))
+ {
+ base->FIFOTRIG =
+ (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);
+ }
+ /* decrease level if rx transfer is bellow */
+ if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U)))
+ {
+ base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U));
+ }
+ }
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_usart.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_usart.h new file mode 100644 index 000000000..b97ae487b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_usart.h @@ -0,0 +1,721 @@ +/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_USART_H_
+#define _FSL_USART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup usart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART driver version 2.1.1. */
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)
+#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief Error codes for the USART driver. */
+enum
+{
+ kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */
+ kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */
+ kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */
+ kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */
+ kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */
+ kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */
+ kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */
+ kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */
+ kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */
+ kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */
+ kStatus_USART_BaudrateNotSupport =
+ MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */
+};
+
+/*! @brief USART synchronous mode. */
+typedef enum _usart_sync_mode
+{
+ kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */
+ kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */
+ kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */
+} usart_sync_mode_t;
+
+/*! @brief USART parity mode. */
+typedef enum _usart_parity_mode
+{
+ kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */
+ kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+ kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */
+} usart_parity_mode_t;
+
+/*! @brief USART stop bit count. */
+typedef enum _usart_stop_bit_count
+{
+ kUSART_OneStopBit = 0U, /*!< One stop bit */
+ kUSART_TwoStopBit = 1U, /*!< Two stop bits */
+} usart_stop_bit_count_t;
+
+/*! @brief USART data size. */
+typedef enum _usart_data_len
+{
+ kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */
+ kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */
+} usart_data_len_t;
+
+/*! @brief USART clock polarity configuration, used in sync mode.*/
+typedef enum _usart_clock_polarity
+{
+ kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */
+ kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */
+} usart_clock_polarity_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _usart_txfifo_watermark
+{
+ kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */
+ kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */
+ kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */
+ kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */
+ kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */
+ kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */
+ kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */
+ kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */
+} usart_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _usart_rxfifo_watermark
+{
+ kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */
+ kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */
+ kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */
+ kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */
+ kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */
+ kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */
+ kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */
+ kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */
+} usart_rxfifo_watermark_t;
+
+/*!
+ * @brief USART interrupt configuration structure, default settings all disabled.
+ */
+enum _usart_interrupt_enable
+{
+ kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),
+ kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),
+ kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),
+ kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),
+};
+
+/*!
+ * @brief USART status flags.
+ *
+ * This provides constants for the USART status flags for use in the USART functions.
+ */
+enum _usart_flags
+{
+ kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */
+ kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */
+ kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */
+ kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */
+ kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */
+ kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */
+};
+
+/*! @brief USART configuration structure. */
+typedef struct _usart_config
+{
+ uint32_t baudRate_Bps; /*!< USART baud rate */
+ usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+ usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+ usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */
+ bool loopback; /*!< Enable peripheral loopback */
+ bool enableRx; /*!< Enable RX */
+ bool enableTx; /*!< Enable TX */
+ bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */
+ usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+ usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+ usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */
+ usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */
+} usart_config_t;
+
+/*! @brief USART transfer structure. */
+typedef struct _usart_transfer
+{
+ uint8_t *data; /*!< The buffer of data to be transfer.*/
+ size_t dataSize; /*!< The byte count to be transfer. */
+} usart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_handle usart_handle_t;
+
+/*! @brief USART transfer callback function. */
+typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief USART handle structure. */
+struct _usart_handle
+{
+ uint8_t *volatile txData; /*!< Address of remaining data to send. */
+ volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+ size_t txDataSizeAll; /*!< Size of the data to send out. */
+ uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
+ volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+ size_t rxDataSizeAll; /*!< Size of the data to receive. */
+
+ uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
+ size_t rxRingBufferSize; /*!< Size of the ring buffer. */
+ volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+ volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+ usart_transfer_callback_t callback; /*!< Callback function. */
+ void *userData; /*!< USART callback function parameter.*/
+
+ volatile uint8_t txState; /*!< TX transfer state. */
+ volatile uint8_t rxState; /*!< RX transfer state */
+
+ uint8_t txWatermark; /*!< txFIFO watermark */
+ uint8_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+/*! @brief Typedef for usart interrupt handler. */
+typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*! @brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * @code
+ * usart_config_t usartConfig;
+ * usartConfig.baudRate_Bps = 115200U;
+ * usartConfig.parityMode = kUSART_ParityDisabled;
+ * usartConfig.stopBitCount = kUSART_OneStopBit;
+ * USART_Init(USART1, &usartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param config Pointer to user-defined configuration structure.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_InvalidArgument USART base address is not valid
+ * @retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * @param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ * usartConfig->baudRate_Bps = 115200U;
+ * usartConfig->parityMode = kUSART_ParityDisabled;
+ * usartConfig->stopBitCount = kUSART_OneStopBit;
+ * usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ * usartConfig->loopback = false;
+ * usartConfig->enableTx = false;
+ * usartConfig->enableRx = false;
+ *
+ * @param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config);
+
+/*!
+ * @brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * @code
+ * USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param baudrate_Bps USART baudrate to be set.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get USART status flags.
+ *
+ * This function get all USART status flags, the flags are returned as the logical
+ * OR value of the enumerators @ref _usart_flags. To check a specific status,
+ * compare the return value with enumerators in @ref _usart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))
+ * {
+ * ...
+ * }
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @return USART status flags which are ORed by the enumerators in the _usart_flags.
+ */
+static inline uint32_t USART_GetStatusFlags(USART_Type *base)
+{
+ return base->FIFOSTAT;
+}
+
+/*!
+ * @brief Clear USART status flags.
+ *
+ * This function clear supported USART status flags
+ * Flags that can be cleared or set are:
+ * kUSART_TxError
+ * kUSART_RxError
+ * For example:
+ * @code
+ * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError)
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask status flags to be cleared.
+ */
+static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
+{
+ /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */
+ base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables USART interrupts according to the provided mask.
+ *
+ * This function enables the USART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt:
+ * @code
+ * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
+{
+ base->FIFOINTENSET = mask & 0xFUL;
+}
+
+/*!
+ * @brief Disables USART interrupts according to a provided mask.
+ *
+ * This function disables the USART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
+{
+ base->FIFOINTENCLR = mask & 0xFUL;
+}
+
+/*!
+ * @brief Returns enabled USART interrupts.
+ *
+ * This function returns the enabled USART interrupts.
+ *
+ * @param base USART peripheral base address.
+ */
+static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base)
+{
+ return base->FIFOINTENSET;
+}
+
+/*!
+ * @brief Enable DMA for Tx
+ */
+static inline void USART_EnableTxDMA(USART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;
+ }
+ else
+ {
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);
+ }
+}
+
+/*!
+ * @brief Enable DMA for Rx
+ */
+static inline void USART_EnableRxDMA(USART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;
+ }
+ else
+ {
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);
+ }
+}
+
+/*!
+ * @brief Enable CTS.
+ * This function will determine whether CTS is used for flow control.
+ *
+ * @param base USART peripheral base address.
+ * @param enable Enable CTS or not, true for enable and false for disable.
+ */
+static inline void USART_EnableCTS(USART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CFG |= USART_CFG_CTSEN_MASK;
+ }
+ else
+ {
+ base->CFG &= ~USART_CFG_CTSEN_MASK;
+ }
+}
+
+/*!
+ * @brief Continuous Clock generation.
+ * By default, SCLK is only output while data is being transmitted in synchronous mode.
+ * Enable this funciton, SCLK will run continuously in synchronous mode, allowing
+ * characters to be received on Un_RxD independently from transmission on Un_TXD).
+ *
+ * @param base USART peripheral base address.
+ * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable.
+ */
+static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CTL |= USART_CTL_CC_MASK;
+ }
+ else
+ {
+ base->CTL &= ~USART_CTL_CC_MASK;
+ }
+}
+
+/*!
+ * @brief Enable Continuous Clock generation bit auto clear.
+ * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete
+ * character has been received. This bit is cleared at the same time.
+ *
+ * @param base USART peripheral base address.
+ * @param enable Enable auto clear or not, true for enable and false for disable.
+ */
+static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CTL |= USART_CTL_CLRCCONRX_MASK;
+ }
+ else
+ {
+ base->CTL &= ~USART_CTL_CLRCCONRX_MASK;
+ }
+}
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Writes to the FIFOWR register.
+ *
+ * This function writes data to the txFIFO directly. The upper layer must ensure
+ * that txFIFO has space for data to write before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void USART_WriteByte(USART_Type *base, uint8_t data)
+{
+ base->FIFOWR = data;
+}
+
+/*!
+ * @brief Reads the FIFORD register directly.
+ *
+ * This function reads data from the rxFIFO directly. The upper layer must
+ * ensure that the rxFIFO is not empty before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @return The byte read from USART data register.
+ */
+static inline uint8_t USART_ReadByte(USART_Type *base)
+{
+ return (uint8_t)base->FIFORD;
+}
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * @retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * @retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+ usart_handle_t *handle,
+ usart_transfer_callback_t callback,
+ void *userData);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the @ref kStatus_USART_TxIdle as status parameter.
+ *
+ * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure. See #usart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base,
+ usart_handle_t *handle,
+ uint8_t *ringBuffer,
+ size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param handle USART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been written to USART TX register.
+ *
+ * This function gets the number of bytes that have been written to USART TX
+ * register by interrupt method.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure, see #usart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * @retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+ usart_handle_t *handle,
+ usart_transfer_t *xfer,
+ size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_USART_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/freertos_tasks_c_additions.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/freertos_tasks_c_additions.h new file mode 100644 index 000000000..00f564633 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/freertos_tasks_c_additions.h @@ -0,0 +1,122 @@ +/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* freertos_tasks_c_additions.h Rev. 1.3 */
+#ifndef FREERTOS_TASKS_C_ADDITIONS_H
+#define FREERTOS_TASKS_C_ADDITIONS_H
+
+#include <stdint.h>
+
+#if (configUSE_TRACE_FACILITY == 0)
+#error "configUSE_TRACE_FACILITY must be enabled"
+#endif
+
+#define FREERTOS_DEBUG_CONFIG_MAJOR_VERSION 1
+#define FREERTOS_DEBUG_CONFIG_MINOR_VERSION 3
+
+/* NOTE!!
+ * Default to a FreeRTOS version which didn't include these macros. FreeRTOS
+ * v7.5.3 is used here.
+ */
+#ifndef tskKERNEL_VERSION_BUILD
+#define tskKERNEL_VERSION_BUILD 3
+#endif
+#ifndef tskKERNEL_VERSION_MINOR
+#define tskKERNEL_VERSION_MINOR 5
+#endif
+#ifndef tskKERNEL_VERSION_MAJOR
+#define tskKERNEL_VERSION_MAJOR 7
+#endif
+
+/* NOTE!!
+ * The configFRTOS_MEMORY_SCHEME macro describes the heap scheme using a value
+ * 1 - 5 which corresponds to the following schemes:
+ *
+ * heap_1 - the very simplest, does not permit memory to be freed
+ * heap_2 - permits memory to be freed, but not does coalescence adjacent free
+ * blocks.
+ * heap_3 - simply wraps the standard malloc() and free() for thread safety
+ * heap_4 - coalesces adjacent free blocks to avoid fragmentation. Includes
+ * absolute address placement option
+ * heap_5 - as per heap_4, with the ability to span the heap across
+ * multiple nonOadjacent memory areas
+ */
+#ifndef configFRTOS_MEMORY_SCHEME
+#define configFRTOS_MEMORY_SCHEME 3 /* thread safe malloc */
+#endif
+
+#if ((configFRTOS_MEMORY_SCHEME > 5) || (configFRTOS_MEMORY_SCHEME < 1))
+#error "Invalid configFRTOS_MEMORY_SCHEME setting!"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint8_t FreeRTOSDebugConfig[];
+
+/* NOTES!!
+ * IAR documentation is confusing. It suggests the data must be statically
+ * linked, and the #pragma placed immediately before the symbol definition.
+ * The IAR supplied examples violate both "rules", so this is a best guess.
+ */
+
+#if (tskKERNEL_VERSION_MAJOR >= 10) && (tskKERNEL_VERSION_MINOR >= 2)
+#if defined(__GNUC__)
+char *const portArch_Name __attribute__((section(".rodata"))) = portARCH_NAME;
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+char *const portArch_Name __attribute__((used)) = portARCH_NAME;
+#elif defined(__IAR_SYSTEMS_ICC__)
+char *const portArch_Name = portARCH_NAME;
+#pragma required=portArch_Name
+#endif
+#else
+char *const portArch_Name = NULL;
+#endif // tskKERNEL_VERSION_MAJOR
+
+#if defined(__GNUC__)
+const uint8_t FreeRTOSDebugConfig[] __attribute__((section(".rodata"))) =
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+const uint8_t FreeRTOSDebugConfig[] __attribute__((used)) =
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma required=FreeRTOSDebugConfig
+const uint8_t FreeRTOSDebugConfig[] =
+#endif
+{
+ FREERTOS_DEBUG_CONFIG_MAJOR_VERSION,
+ FREERTOS_DEBUG_CONFIG_MINOR_VERSION,
+ tskKERNEL_VERSION_MAJOR,
+ tskKERNEL_VERSION_MINOR,
+ tskKERNEL_VERSION_BUILD,
+ configFRTOS_MEMORY_SCHEME,
+ offsetof(struct tskTaskControlBlock, pxTopOfStack),
+#if (tskKERNEL_VERSION_MAJOR > 8)
+ offsetof(struct tskTaskControlBlock, xStateListItem),
+#else
+ offsetof(struct tskTaskControlBlock, xGenericListItem),
+#endif
+ offsetof(struct tskTaskControlBlock, xEventListItem),
+ offsetof(struct tskTaskControlBlock, pxStack),
+ offsetof(struct tskTaskControlBlock, pcTaskName),
+ offsetof(struct tskTaskControlBlock, uxTCBNumber),
+ offsetof(struct tskTaskControlBlock, uxTaskNumber),
+ configMAX_TASK_NAME_LEN,
+ configMAX_PRIORITIES,
+ configENABLE_MPU,
+ configENABLE_FPU,
+ configENABLE_TRUSTZONE,
+ configRUN_FREERTOS_SECURE_ONLY,
+ 0, // 32-bit align
+ 0, 0, 0, 0 // padding
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // FREERTOS_TASKS_C_ADDITIONS_H
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_assert.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_assert.c new file mode 100644 index 000000000..db65df030 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_assert.c @@ -0,0 +1,44 @@ +/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+ PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+ for (;;)
+ {
+ __BKPT(0);
+ }
+}
+#elif (defined(__GNUC__))
+#if defined(__REDLIB__)
+void __assertion_failed(char *failedExpr)
+{
+ PRINTF("ASSERT ERROR \" %s \n", failedExpr);
+ for (;;)
+ {
+ __BKPT(0);
+ }
+}
+#else
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+ PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+ for (;;)
+ {
+ __BKPT(0);
+ }
+}
+#endif /* defined(__REDLIB__) */
+#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */
+#endif /* NDEBUG */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c new file mode 100644 index 000000000..76aee9c2a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c @@ -0,0 +1,1211 @@ +/*
+ * This is a modified version of the file printf.c, which was distributed
+ * by Motorola as part of the M5407C3BOOT.zip package used to initialize
+ * the M5407C3 evaluation board.
+ *
+ * Copyright:
+ * 1999-2000 MOTOROLA, INC. All Rights Reserved.
+ * You are hereby granted a copyright license to use, modify, and
+ * distribute the SOFTWARE so long as this entire notice is
+ * retained without alteration in any modified and/or redistributed
+ * versions, and that such modified versions are clearly identified
+ * as such. No licenses are granted by implication, estoppel or
+ * otherwise under any patents or trademarks of Motorola, Inc. This
+ * software is provided on an "AS IS" basis and without warranty.
+ *
+ * To the maximum extent permitted by applicable law, MOTOROLA
+ * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
+ * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
+ * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
+ * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
+ * ACCOMPANYING WRITTEN MATERIALS.
+ *
+ * To the maximum extent permitted by applicable law, IN NO EVENT
+ * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
+ * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
+ * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
+ * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ * Motorola assumes no responsibility for the maintenance and support
+ * of this software
+
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdarg.h>
+#include <stdlib.h>
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#include <stdio.h>
+#endif
+
+#ifdef FSL_RTOS_FREE_RTOS
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+#endif
+
+#include "fsl_debug_console_conf.h"
+#include "fsl_str.h"
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+
+#include "fsl_debug_console.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if SDK_DEBUGCONSOLE
+#define DEBUG_CONSOLE_FUNCTION_PREFIX
+#else
+#define DEBUG_CONSOLE_FUNCTION_PREFIX static
+#endif
+
+/*! @brief character backspace ASCII value */
+#define DEBUG_CONSOLE_BACKSPACE 127U
+
+/* lock definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+
+static SemaphoreHandle_t s_debugConsoleReadSemaphore;
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore;
+#endif
+
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+static volatile uint8_t s_debugConsoleReadWaitSemaphore;
+#endif
+
+#else
+
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+/*! @brief get current runing environment is ISR or not */
+#ifdef __CA7_REV
+#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel()
+#else
+#define IS_RUNNING_IN_ISR() __get_IPSR()
+#endif /* __CA7_REV */
+
+/* semaphore definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+
+/* mutex semaphore */
+/* clang-format off */
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex())
+#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) \
+ do \
+ { \
+ if(NULL != mutex) \
+ { \
+ vSemaphoreDelete(mutex); \
+ mutex = NULL; \
+ } \
+ } while(0)
+
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \
+{ \
+ if (IS_RUNNING_IN_ISR() == 0U) \
+ { \
+ (void)xSemaphoreGive(mutex); \
+ } \
+}
+
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \
+{ \
+ if (IS_RUNNING_IN_ISR() == 0U) \
+ { \
+ (void)xSemaphoreTake(mutex, portMAX_DELAY); \
+ } \
+}
+
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \
+{ \
+ if (IS_RUNNING_IN_ISR() == 0U) \
+ { \
+ result = xSemaphoreTake(mutex, 0U); \
+ } \
+ else \
+ { \
+ result = 1U; \
+ } \
+}
+
+/* Binary semaphore */
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary())
+#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) \
+ do \
+ { \
+ if(NULL != binary) \
+ { \
+ vSemaphoreDelete(binary); \
+ binary = NULL; \
+ } \
+ } while(0)
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake(binary, portMAX_DELAY))
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR(binary, NULL))
+
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE)
+
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex)
+#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
+
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary)
+#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary)
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \
+ { \
+ while (!binary) \
+ { \
+ } \
+ binary = false; \
+ }
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true)
+#else
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+/* clang-format on */
+
+/* add other implementation here
+ *such as :
+ * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx)
+ */
+
+#else
+
+#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE.
+
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/* receive state structure */
+typedef struct _debug_console_write_ring_buffer
+{
+ uint32_t ringBufferSize;
+ volatile uint32_t ringHead;
+ volatile uint32_t ringTail;
+ uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN];
+} debug_console_write_ring_buffer_t;
+#endif
+
+typedef struct _debug_console_state_struct
+{
+ uint8_t serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
+ serial_handle_t serialHandle; /*!< serial manager handle */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+ debug_console_write_ring_buffer_t writeRingBuffer;
+ uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN];
+#endif
+ uint8_t serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
+ uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];
+} debug_console_state_struct_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Debug console state information. */
+#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE > 0))
+AT_NONCACHEABLE_SECTION(static debug_console_state_struct_t s_debugConsoleState);
+#else
+static debug_console_state_struct_t s_debugConsoleState;
+#endif
+serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief This is a printf call back function which is used to relocate the log to buffer
+ * or print the log immediately when the local buffer is full.
+ *
+ * @param[in] buf Buffer to store log.
+ * @param[in] indicator Buffer index.
+ * @param[in] val Target character to store.
+ * @param[in] len length of the character
+ *
+ */
+#if SDK_DEBUGCONSOLE
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len);
+#endif
+
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch);
+int DbgConsole_SendData(uint8_t *ch, size_t size);
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size);
+int DbgConsole_ReadLine(uint8_t *buf, size_t size);
+int DbgConsole_ReadCharacter(uint8_t *ch);
+
+#if ((SDK_DEBUGCONSOLE > 0U) || \
+ ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+static void DbgConsole_SerialManagerTxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ debug_console_state_struct_t *ioState;
+ uint32_t sendDataLength;
+
+ if ((NULL == callbackParam) || (NULL == message))
+ {
+ return;
+ }
+
+ ioState = (debug_console_state_struct_t *)callbackParam;
+
+ ioState->writeRingBuffer.ringTail += message->length;
+ if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize)
+ {
+ ioState->writeRingBuffer.ringTail = 0U;
+ }
+
+ if (kStatus_SerialManager_Success == status)
+ {
+ if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead)
+ {
+ if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail)
+ {
+ sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail;
+ }
+ else
+ {
+ sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail;
+ }
+
+ (void)SerialManager_WriteNonBlocking(
+ ((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]),
+ &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail], sendDataLength);
+ }
+ }
+ else if (kStatus_SerialManager_Canceled == status)
+ {
+ ioState->writeRingBuffer.ringTail = 0U;
+ ioState->writeRingBuffer.ringHead = 0U;
+ }
+ else
+ {
+ /*MISRA rule 16.4*/
+ }
+}
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+
+static void DbgConsole_SerialManagerRxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ if ((NULL == callbackParam) || (NULL == message))
+ {
+ return;
+ }
+
+ if (kStatus_SerialManager_Notify == status)
+ {
+ }
+ else if (kStatus_SerialManager_Success == status)
+ {
+ /* release s_debugConsoleReadWaitSemaphore from RX callback */
+ DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore);
+ }
+ else
+ {
+ /*MISRA rule 16.4*/
+ }
+}
+#endif
+
+#endif
+
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch)
+{
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+ (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
+ return kStatus_Fail;
+#else
+ status_t status = (status_t)kStatus_SerialManager_Error;
+
+/* recieve one char every time */
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ status = (status_t)SerialManager_ReadNonBlocking(
+ ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
+#else
+ status = (status_t)SerialManager_ReadBlocking(
+ ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
+#endif
+ if ((status_t)kStatus_SerialManager_Success != status)
+ {
+ return (status_t)kStatus_Fail;
+ }
+ /* wait s_debugConsoleReadWaitSemaphore from RX callback */
+ DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore);
+
+ return (status_t)kStatus_Success;
+#endif
+
+#else
+
+ return (status_t)kStatus_Fail;
+
+#endif
+}
+
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index)
+{
+ /* Due to scanf take \n and \r as end of string,should not echo */
+ if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar))
+ {
+ /* recieve one char every time */
+ if (1 != DbgConsole_SendDataReliable(ch, 1U))
+ {
+ return (status_t)kStatus_Fail;
+ }
+ }
+
+ if ((!isGetChar) && (index != NULL))
+ {
+ if (DEBUG_CONSOLE_BACKSPACE == *ch)
+ {
+ if ((*index >= 2))
+ {
+ *index -= 2;
+ }
+ else
+ {
+ *index = 0;
+ }
+ }
+ }
+
+ return (status_t)kStatus_Success;
+}
+#endif
+
+int DbgConsole_SendData(uint8_t *ch, size_t size)
+{
+ status_t status = (status_t)kStatus_SerialManager_Error;
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ uint32_t sendDataLength;
+ int txBusy = 0;
+#endif
+ assert(NULL != ch);
+ assert(0 != size);
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ uint32_t regPrimask = DisableGlobalIRQ();
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ txBusy = 1;
+ sendDataLength =
+ (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
+ s_debugConsoleState.writeRingBuffer.ringTail) %
+ s_debugConsoleState.writeRingBuffer.ringBufferSize;
+ }
+ else
+ {
+ sendDataLength = 0U;
+ }
+ sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1;
+ if (sendDataLength < size)
+ {
+ EnableGlobalIRQ(regPrimask);
+ return -1;
+ }
+ for (int i = 0; i < (int)size; i++)
+ {
+ s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i];
+ if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize)
+ {
+ s_debugConsoleState.writeRingBuffer.ringHead = 0U;
+ }
+ }
+
+ status = (status_t)kStatus_SerialManager_Success;
+
+ if (txBusy == 0)
+ {
+ if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ sendDataLength =
+ s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail;
+ }
+ else
+ {
+ sendDataLength =
+ s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail;
+ }
+
+ status = (status_t)SerialManager_WriteNonBlocking(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+ &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail],
+ sendDataLength);
+ }
+ EnableGlobalIRQ(regPrimask);
+#else
+ status = (status_t)SerialManager_WriteBlocking(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
+#endif
+ return (((status_t)kStatus_Success == status) ? (int)size : -1);
+}
+
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size)
+{
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
+ status_t status = kStatus_SerialManager_Error;
+ uint32_t sendDataLength;
+ uint32_t totalLength = size;
+ int sentLength;
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+#else
+ status_t status = kStatus_SerialManager_Error;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+ assert(NULL != ch);
+ assert(0 != size);
+
+ if (NULL == g_serialHandle)
+ {
+ return 0;
+ }
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
+ do
+ {
+ uint32_t regPrimask = DisableGlobalIRQ();
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ sendDataLength =
+ (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
+ s_debugConsoleState.writeRingBuffer.ringTail) %
+ s_debugConsoleState.writeRingBuffer.ringBufferSize;
+ }
+ else
+ {
+ sendDataLength = 0U;
+ }
+ sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U;
+
+ if (sendDataLength > 0U)
+ {
+ if (sendDataLength > totalLength)
+ {
+ sendDataLength = totalLength;
+ }
+
+ sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength);
+ if (sentLength > 0)
+ {
+ totalLength = totalLength - (uint32_t)sentLength;
+ }
+ }
+ EnableGlobalIRQ(regPrimask);
+
+ if (totalLength != 0U)
+ {
+ status = DbgConsole_Flush();
+ if ((status_t)kStatus_Success != status)
+ {
+ break;
+ }
+ }
+ } while (totalLength != 0U);
+ return (status_t)(uint32_t)((uint32_t)size - totalLength);
+#else
+ return DbgConsole_SendData(ch, size);
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+
+#else
+ status = (status_t)SerialManager_WriteBlocking(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
+ return (((status_t)kStatus_Success == status) ? (int)size : -1);
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+}
+
+int DbgConsole_ReadLine(uint8_t *buf, size_t size)
+{
+ int i = 0;
+
+ assert(buf != NULL);
+
+ if (NULL == g_serialHandle)
+ {
+ return -1;
+ }
+
+ /* take mutex lock function */
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+
+ do
+ {
+ /* recieve one char every time */
+ if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i]))
+ {
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+ i = -1;
+ break;
+ }
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+ (void)DbgConsole_EchoCharacter(&buf[i], false, &i);
+#endif
+ /* analysis data */
+ if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i]))
+ {
+ /* End of Line. */
+ if (0 == i)
+ {
+ buf[i] = (uint8_t)'\0';
+ continue;
+ }
+ else
+ {
+ break;
+ }
+ }
+ i++;
+ } while (i < (int)size);
+
+ /* get char should not add '\0'*/
+ if (i == (int)size)
+ {
+ buf[i] = (uint8_t)'\0';
+ }
+ else
+ {
+ buf[i + 1] = (uint8_t)'\0';
+ }
+
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+
+ return i;
+}
+
+int DbgConsole_ReadCharacter(uint8_t *ch)
+{
+ int ret;
+
+ assert(ch);
+
+ if (NULL == g_serialHandle)
+ {
+ return -1;
+ }
+
+ /* take mutex lock function */
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+ /* read one character */
+ if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch))
+ {
+ ret = 1;
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+ (void)DbgConsole_EchoCharacter(ch, true, NULL);
+#endif
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+
+ return ret;
+}
+
+#if SDK_DEBUGCONSOLE
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len)
+{
+ int i = 0;
+
+ for (i = 0; i < len; i++)
+ {
+ if (((uint32_t)*indicator + 1UL) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
+ {
+ (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator));
+ *indicator = 0;
+ }
+
+ buf[*indicator] = dbgVal;
+ (*indicator)++;
+ }
+}
+#endif
+
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
+
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)
+{
+ serial_manager_config_t serialConfig;
+ status_t status = (status_t)kStatus_SerialManager_Error;
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ serial_port_uart_config_t uartConfig = {
+ .instance = instance,
+ .clockRate = clkSrcFreq,
+ .baudRate = baudRate,
+ .parityMode = kSerialManager_UartParityDisabled,
+ .stopBitCount = kSerialManager_UartOneStopBit,
+ .enableRx = 1,
+ .enableTx = 1,
+ };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ serial_port_usb_cdc_config_t usbCdcConfig = {
+ .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance,
+ };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ serial_port_swo_config_t swoConfig = {
+ .clockRate = clkSrcFreq,
+ .baudRate = baudRate,
+ .port = instance,
+ .protocol = kSerialManager_SwoProtocolNrz,
+ };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ serial_port_usb_cdc_virtual_config_t usbCdcVirtualConfig = {
+ .controllerIndex = (serial_port_usb_cdc_virtual_controller_index_t)instance,
+ };
+#endif
+ serialConfig.type = device;
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0];
+ serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN;
+#endif
+
+ if (kSerialPort_Uart == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ serialConfig.portConfig = &uartConfig;
+#else
+ return status;
+#endif
+ }
+ else if (kSerialPort_UsbCdc == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ serialConfig.portConfig = &usbCdcConfig;
+#else
+ return status;
+#endif
+ }
+ else if (kSerialPort_Swo == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ serialConfig.portConfig = &swoConfig;
+#else
+ return status;
+#endif
+ }
+ else if (kSerialPort_UsbCdcVirtual == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ serialConfig.portConfig = &usbCdcVirtualConfig;
+#else
+ return status;
+#endif
+ }
+ else
+ {
+ return status;
+ }
+
+ (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState));
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN;
+#endif
+
+ s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0];
+ status = (status_t)SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig);
+
+ assert(kStatus_SerialManager_Success == status);
+
+ DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
+#endif
+
+ {
+ status = (status_t)SerialManager_OpenWriteHandle(
+ s_debugConsoleState.serialHandle, ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+ assert(kStatus_SerialManager_Success == status);
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ (void)SerialManager_InstallTxCallback(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+ DbgConsole_SerialManagerTxCallback, &s_debugConsoleState);
+#endif
+ }
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ {
+ status = (status_t)SerialManager_OpenReadHandle(
+ s_debugConsoleState.serialHandle, ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+ assert(kStatus_SerialManager_Success == status);
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ (void)SerialManager_InstallRxCallback(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]),
+ DbgConsole_SerialManagerRxCallback, &s_debugConsoleState);
+#endif
+ }
+#endif
+
+ g_serialHandle = s_debugConsoleState.serialHandle;
+
+ return kStatus_Success;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Deinit(void)
+{
+ {
+ if (s_debugConsoleState.serialHandle != NULL)
+ {
+ (void)SerialManager_CloseWriteHandle(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+ }
+ }
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ {
+ if (s_debugConsoleState.serialHandle != NULL)
+ {
+ (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+ }
+ }
+#endif
+ if (s_debugConsoleState.serialHandle)
+ {
+ if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle))
+ {
+ s_debugConsoleState.serialHandle = NULL;
+ g_serialHandle = NULL;
+ }
+ }
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
+#endif
+ DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+
+ return (status_t)kStatus_Success;
+}
+#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
+
+#if ((SDK_DEBUGCONSOLE > 0U) || \
+ ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void)
+{
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
+
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ return (status_t)kStatus_Fail;
+ }
+
+#else
+
+ while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+ if (0U == IS_RUNNING_IN_ISR())
+ {
+ if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState())
+ {
+ vTaskDelay(1);
+ }
+ }
+ else
+ {
+ return (status_t)kStatus_Fail;
+ }
+#endif
+ }
+
+#endif
+
+#endif
+ return (status_t)kStatus_Success;
+}
+#endif
+
+#if SDK_DEBUGCONSOLE
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Printf(const char *formatString, ...)
+{
+ va_list ap;
+ int logLength = 0, dbgResult = 0;
+ char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};
+
+ if (NULL == g_serialHandle)
+ {
+ return 0;
+ }
+
+ va_start(ap, formatString);
+ /* format print log first */
+ logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);
+ /* print log */
+ dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength);
+
+ va_end(ap);
+
+ return dbgResult;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Putchar(int ch)
+{
+ /* print char */
+ return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U);
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Scanf(char *formatString, ...)
+{
+ va_list ap;
+ int formatResult;
+ char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'};
+
+ /* scanf log */
+ (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);
+ /* get va_list */
+ va_start(ap, formatString);
+ /* format scanf log */
+ formatResult = StrFormatScanf(scanfBuf, formatString, ap);
+
+ va_end(ap);
+
+ return formatResult;
+}
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_BlockingPrintf(const char *formatString, ...)
+{
+ va_list ap;
+ status_t status = (status_t)kStatus_SerialManager_Error;
+ int logLength = 0, dbgResult = 0;
+ char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};
+
+ if (NULL == g_serialHandle)
+ {
+ return 0;
+ }
+
+ va_start(ap, formatString);
+ /* format print log first */
+ logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ SerialManager_CancelWriting(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+#endif
+ /* print log */
+ status =
+ (status_t)SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+ (uint8_t *)printBuf, (size_t)logLength);
+ dbgResult = (((status_t)kStatus_Success == status) ? (int)logLength : -1);
+ va_end(ap);
+
+ return dbgResult;
+}
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+status_t DbgConsole_TryGetchar(char *ch)
+{
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ uint32_t length = 0;
+ status_t status = (status_t)kStatus_Fail;
+
+ assert(ch);
+
+ if (NULL == g_serialHandle)
+ {
+ return kStatus_Fail;
+ }
+
+ /* take mutex lock function */
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+
+ if (kStatus_SerialManager_Success ==
+ SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1,
+ &length))
+ {
+ if (length != 0U)
+ {
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+ (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL);
+#endif
+ status = (status_t)kStatus_Success;
+ }
+ }
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+ return status;
+#else
+ return (status_t)kStatus_Fail;
+#endif
+}
+#endif
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Getchar(void)
+{
+ uint8_t ch = 0U;
+
+ /* Get char */
+ (void)DbgConsole_ReadCharacter(&ch);
+
+ return (int)ch;
+}
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*************Code to support toolchain's printf, scanf *******************************/
+/* These function __write and __read is used to support IAR toolchain to printf and scanf*/
+#if (defined(__ICCARM__))
+#if defined(SDK_DEBUGCONSOLE_UART)
+#pragma weak __write
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+ if (buffer == 0)
+ {
+ /*
+ * This means that we should flush internal buffers. Since we don't we just return.
+ * (Remember, "handle" == -1 means that all handles should be flushed.)
+ */
+ return 0;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return ((size_t)-1);
+ }
+
+ /* Send data. */
+ DbgConsole_SendDataReliable((uint8_t *)buffer, size);
+
+ return size;
+}
+
+#pragma weak __read
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+ uint8_t ch = 0U;
+ int actualSize = 0U;
+
+ /* This function only reads from "standard in", for all other file handles it returns failure. */
+ if (handle != 0)
+ {
+ return ((size_t)-1);
+ }
+
+ /* Receive data.*/
+ for (; size > 0; size--)
+ {
+ DbgConsole_ReadCharacter(&ch);
+ if (ch == 0)
+ {
+ break;
+ }
+
+ *buffer++ = ch;
+ actualSize++;
+ }
+
+ return actualSize;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* support LPC Xpresso with RedLib */
+#elif (defined(__REDLIB__))
+
+#if (defined(SDK_DEBUGCONSOLE_UART))
+int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
+{
+ if (buffer == 0)
+ {
+ /* return -1 if error. */
+ return -1;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ DbgConsole_SendDataReliable((uint8_t *)buffer, size);
+
+ return 0;
+}
+
+int __attribute__((weak)) __sys_readc(void)
+{
+ char tmp;
+
+ /* Receive data. */
+ DbgConsole_ReadCharacter((uint8_t *)&tmp);
+
+ return tmp;
+}
+#endif
+
+/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#if defined(SDK_DEBUGCONSOLE_UART)
+#if defined(__CC_ARM)
+struct __FILE
+{
+ int handle;
+ /*
+ * Whatever you require here. If the only file you are using is standard output using printf() for debugging,
+ * no file handling is required.
+ */
+};
+#endif
+
+/* FILE is typedef in stdio.h. */
+#pragma weak __stdout
+#pragma weak __stdin
+FILE __stdout;
+FILE __stdin;
+
+#pragma weak fputc
+int fputc(int ch, FILE *f)
+{
+ /* Send data. */
+ return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1);
+}
+
+#pragma weak fgetc
+int fgetc(FILE *f)
+{
+ char ch;
+
+ /* Receive data. */
+ DbgConsole_ReadCharacter((uint8_t *)&ch);
+
+ return ch;
+}
+
+/*
+ * Terminate the program, passing a return code back to the user.
+ * This function may not return.
+ */
+void _sys_exit(int returncode)
+{
+ while (1)
+ {
+ }
+}
+
+/*
+ * Writes a character to the output channel. This function is used
+ * for last-resort error message output.
+ */
+void _ttywrch(int ch)
+{
+ char ench = ch;
+ DbgConsole_SendDataReliable((uint8_t *)(&ench), 1);
+}
+
+char *_sys_command_string(char *cmd, int len)
+{
+ return (cmd);
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
+#elif (defined(__GNUC__))
+
+#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \
+ (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART))))
+int __attribute__((weak)) _write(int handle, char *buffer, int size);
+int __attribute__((weak)) _write(int handle, char *buffer, int size)
+{
+ if (buffer == NULL)
+ {
+ /* return -1 if error. */
+ return -1;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size);
+
+ return size;
+}
+
+int __attribute__((weak)) _read(int handle, char *buffer, int size);
+int __attribute__((weak)) _read(int handle, char *buffer, int size)
+{
+ uint8_t ch = 0U;
+ int actualSize = 0;
+
+ /* This function only reads from "standard in", for all other file handles it returns failure. */
+ if (handle != 0)
+ {
+ return -1;
+ }
+
+ /* Receive data. */
+ for (; size > 0; size--)
+ {
+ if (DbgConsole_ReadCharacter(&ch) < 0)
+ {
+ break;
+ }
+
+ *buffer++ = (char)ch;
+ actualSize++;
+
+ if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r'))
+ {
+ break;
+ }
+ }
+
+ return (actualSize > 0) ? actualSize : -1;
+}
+#endif
+
+#endif /* __ICCARM__ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h new file mode 100644 index 000000000..ec50606a5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h @@ -0,0 +1,244 @@ +/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Debug console shall provide input and output functions to scan and print formatted data.
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
+ * - [flags] :'-', '+', '#', ' ', '0'
+ * - [width]: number (0,1...)
+ * - [.precision]: number (0,1...)
+ * - [length]: do not support
+ * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
+ * - [*]: is supported.
+ * - [width]: number (0,1...)
+ * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
+ * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
+ */
+
+#ifndef _FSL_DEBUGCONSOLE_H_
+#define _FSL_DEBUGCONSOLE_H_
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+extern serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
+#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
+#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */
+#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */
+
+/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
+ * to be redefined in project setting.
+ */
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE 1U
+#endif
+
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
+#include <stdio.h>
+#endif
+
+/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
+ *
+ * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
+ * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
+ * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
+ */
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
+#define PRINTF
+#define SCANF
+#define PUTCHAR
+#define GETCHAR
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
+#define PRINTF DbgConsole_Printf
+#define SCANF DbgConsole_Scanf
+#define PUTCHAR DbgConsole_Putchar
+#define GETCHAR DbgConsole_Getchar
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
+ */
+#define PRINTF printf
+#define SCANF scanf
+#define PUTCHAR putchar
+#define GETCHAR getchar
+#endif /* SDK_DEBUGCONSOLE */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+/*!
+ * @brief Initializes the peripheral used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.
+ *
+ * @param instance The instance of the module.
+ * @param baudRate The desired baud rate in bits per second.
+ * @param device Low level device type for the debug console, can be one of the following.
+ * @arg kSerialPort_Uart,
+ * @arg kSerialPort_UsbCdc
+ * @arg kSerialPort_UsbCdcVirtual.
+ * @param clkSrcFreq Frequency of peripheral source clock.
+ *
+ * @return Indicates whether initialization was successful or not.
+ * @retval kStatus_Success Execution successfully
+ */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-initializes the peripheral used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_Deinit(void);
+#else
+/*!
+ * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_Init(uint8_t instance,
+ uint32_t baudRate,
+ serial_port_type_t device,
+ uint32_t clkSrcFreq)
+{
+ (void)instance;
+ (void)baudRate;
+ (void)device;
+ (void)clkSrcFreq;
+ return (status_t)kStatus_Fail;
+}
+/*!
+ * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_Deinit(void)
+{
+ return (status_t)kStatus_Fail;
+}
+#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
+
+#if SDK_DEBUGCONSOLE
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param formatString Format control string.
+ * @return Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Printf(const char *formatString, ...);
+
+/*!
+ * @brief Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param ch Character to be written.
+ * @return Returns the character written.
+ */
+int DbgConsole_Putchar(int ch);
+
+/*!
+ * @brief Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @param formatString Format control string.
+ * @return Returns the number of fields successfully converted and assigned.
+ */
+int DbgConsole_Scanf(char *formatString, ...);
+
+/*!
+ * @brief Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @return Returns the character read.
+ */
+int DbgConsole_Getchar(void);
+
+/*!
+ * @brief Writes formatted output to the standard output stream with the blocking mode.
+ *
+ * Call this function to write a formatted output to the standard output stream with the blocking mode.
+ * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set
+ * or not.
+ * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set.
+ *
+ * @param formatString Format control string.
+ * @return Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_BlockingPrintf(const char *formatString, ...);
+
+/*!
+ * @brief Debug console flush.
+ *
+ * Call this function to wait the tx buffer empty.
+ * If interrupt transfer is using, make sure the global IRQ is enable before call this function
+ * This function should be called when
+ * 1, before enter power down mode
+ * 2, log is required to print to terminal immediately
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t DbgConsole_Flush(void);
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*!
+ * @brief Debug console try to get char
+ * This function provides a API which will not block current task, if character is
+ * available return it, otherwise return fail.
+ * @param ch the address of char to receive
+ * @return Indicates get char was successful or not.
+ */
+status_t DbgConsole_TryGetchar(char *ch);
+#endif
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console_conf.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console_conf.h new file mode 100644 index 000000000..4c36a7dd8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console_conf.h @@ -0,0 +1,158 @@ +/*
+ * Copyright 2017 - 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
+#define _FSL_DEBUG_CONSOLE_CONF_H_
+
+/****************Debug console configuration********************/
+
+/*! @brief If Non-blocking mode is needed, please define it at project setting,
+ * otherwise blocking mode is the default transfer mode.
+ * Warning: If you want to use non-blocking transfer,please make sure the corresponding
+ * IO interrupt is enable, otherwise there is no output.
+ * And non-blocking is combine with buffer, no matter bare-metal or rtos.
+ * Below shows how to configure in your project if you want to use non-blocking mode.
+ * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
+ * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
+ * For ARMGCC, open CmakeLists.txt and add the following lines,
+ * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
+ * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
+ * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
+ * Complier->Preprocessor".
+ *
+ */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
+ * when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed , because the log will not be
+ * buffered if the buffer is full, and the print will return immediately with -1.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
+
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
+
+/*!@ brief Whether enable the reliable TX function
+ * If the macro is zero, the reliable TX function of the debug console is disabled.
+ * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
+ */
+#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
+#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+#else
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!@ brief Whether enable the RX function
+ * If the macro is zero, the receive function of the debug console is disabled.
+ */
+#ifndef DEBUG_CONSOLE_RX_ENABLE
+#define DEBUG_CONSOLE_RX_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
+ * length can not bigger than this value.
+ * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
+ * the buffer is too big and current task stack size not big enough.
+ */
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
+
+/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
+ * length can not bigger than this value.
+ * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
+ */
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
+
+/*! @brief Debug console synchronization
+ * User should not change these macro for synchronization mode, but add the
+ * corresponding synchronization mechanism per different software environment.
+ * Such as, if another RTOS is used,
+ * add:
+ * #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
+ * in this configuration file and implement the synchronization in fsl.log.c.
+ */
+/*! @brief synchronization for baremetal software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
+/*! @brief synchronization for freertos software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
+
+/*! @brief RTOS synchronization mechanism disable
+ * If not defined, default is enable, to avoid multitask log print mess.
+ * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
+ * If synchronization is disabled, log maybe messed on terminal.
+ */
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#ifdef FSL_RTOS_FREE_RTOS
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* FSL_RTOS_FREE_RTOS */
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
+
+/*! @brief echo function support
+ * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
+ * at your project setting.
+ */
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
+#else
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
+
+/*********************************************************************/
+
+/***************Debug console other configuration*********************/
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
+#ifndef BOARD_USE_VIRTUALCOM
+#define BOARD_USE_VIRTUALCOM 0U
+#endif
+/*******************************************************************/
+
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_str.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_str.c new file mode 100644 index 000000000..1a49a45e9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_str.c @@ -0,0 +1,1324 @@ +/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <math.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include "fsl_str.h"
+#include "fsl_debug_console_conf.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief The overflow value.*/
+#ifndef HUGE_VAL
+#define HUGE_VAL (99.e99)
+#endif /* HUGE_VAL */
+
+#if PRINTF_ADVANCED_ENABLE
+/*! @brief Specification modifier flags for printf. */
+enum _debugconsole_printf_flag
+{
+ kPRINTF_Minus = 0x01U, /*!< Minus FLag. */
+ kPRINTF_Plus = 0x02U, /*!< Plus Flag. */
+ kPRINTF_Space = 0x04U, /*!< Space Flag. */
+ kPRINTF_Zero = 0x08U, /*!< Zero Flag. */
+ kPRINTF_Pound = 0x10U, /*!< Pound Flag. */
+ kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */
+ kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */
+ kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */
+ kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
+};
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Specification modifier flags for scanf. */
+enum _debugconsole_scanf_flag
+{
+ kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */
+ kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */
+ kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */
+ kSCANF_DestString = 0x8U, /*!< Destination String FLag. */
+ kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */
+ kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */
+ kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */
+ kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
+#if SCANF_ADVANCED_ENABLE
+ kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */
+ kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */
+ kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */
+ kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+ kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
+#endif /*PRINTF_FLOAT_ENABLE */
+ kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */
+};
+
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
+#if defined(__CC_ARM)
+#pragma diag_suppress 1256
+#endif /* __CC_ARM */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Scanline function which ignores white spaces.
+ *
+ * @param[in] s The address of the string pointer to update.
+ * @return String without white spaces.
+ */
+static uint32_t ScanIgnoreWhiteSpace(const char **s);
+
+/*!
+ * @brief Converts a radix number to a string and return its length.
+ *
+ * @param[in] numstr Converted string of the number.
+ * @param[in] nump Pointer to the number.
+ * @param[in] neg Polarity of the number.
+ * @param[in] radix The radix to be converted to.
+ * @param[in] use_caps Used to identify %x/X output format.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps);
+
+#if PRINTF_FLOAT_ENABLE
+/*!
+ * @brief Converts a floating radix number to a string and return its length.
+ *
+ * @param[in] numstr Converted string of the number.
+ * @param[in] nump Pointer to the number.
+ * @param[in] radix The radix to be converted to.
+ * @param[in] precision_width Specify the precision width.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width);
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*!
+ *
+ */
+double modf(double input_dbl, double *intpart_ptr);
+
+/*************Code for process formatted data*******************************/
+
+static uint32_t ScanIgnoreWhiteSpace(const char **s)
+{
+ uint8_t count = 0;
+ uint8_t c;
+
+ c = **s;
+ while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
+ {
+ count++;
+ (*s)++;
+ c = **s;
+ }
+ return count;
+}
+
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)
+{
+#if PRINTF_ADVANCED_ENABLE
+ int64_t a;
+ int64_t b;
+ int64_t c;
+
+ uint64_t ua;
+ uint64_t ub;
+ uint64_t uc;
+#else
+ int32_t a;
+ int32_t b;
+ int32_t c;
+
+ uint32_t ua;
+ uint32_t ub;
+ uint32_t uc;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ int32_t nlen;
+ char *nstrp;
+
+ nlen = 0;
+ nstrp = numstr;
+ *nstrp++ = '\0';
+
+ if (neg)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ a = *(int64_t *)nump;
+#else
+ a = *(int32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (a == 0)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ while (a != 0)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ b = (int64_t)a / (int64_t)radix;
+ c = (int64_t)a - ((int64_t)b * (int64_t)radix);
+ if (c < 0)
+ {
+ uc = (uint64_t)c;
+ c = (int64_t)(~uc) + 1 + '0';
+ }
+#else
+ b = a / radix;
+ c = a - (b * radix);
+ if (c < 0)
+ {
+ uc = (uint32_t)c;
+ c = (uint32_t)(~uc) + 1 + '0';
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ c = c + '0';
+ }
+ a = b;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ }
+ else
+ {
+#if PRINTF_ADVANCED_ENABLE
+ ua = *(uint64_t *)nump;
+#else
+ ua = *(uint32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (ua == 0)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ while (ua != 0)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ ub = (uint64_t)ua / (uint64_t)radix;
+ uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);
+#else
+ ub = ua / (uint32_t)radix;
+ uc = ua - (ub * (uint32_t)radix);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ if (uc < 10)
+ {
+ uc = uc + '0';
+ }
+ else
+ {
+ uc = uc - 10 + (use_caps ? 'A' : 'a');
+ }
+ ua = ub;
+ *nstrp++ = (char)uc;
+ ++nlen;
+ }
+ }
+ return nlen;
+}
+
+#if PRINTF_FLOAT_ENABLE
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width)
+{
+ int32_t a;
+ int32_t b;
+ int32_t c;
+ int32_t i;
+ uint32_t uc;
+ double fa;
+ double dc;
+ double fb;
+ double r;
+ double fractpart;
+ double intpart;
+
+ int32_t nlen;
+ char *nstrp;
+ nlen = 0;
+ nstrp = numstr;
+ *nstrp++ = '\0';
+ r = *(double *)nump;
+ if (!r)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ fractpart = modf((double)r, (double *)&intpart);
+ /* Process fractional part. */
+ for (i = 0; i < precision_width; i++)
+ {
+ fractpart *= radix;
+ }
+ if (r >= 0)
+ {
+ fa = fractpart + (double)0.5;
+ if (fa >= pow(10, precision_width))
+ {
+ intpart++;
+ }
+ }
+ else
+ {
+ fa = fractpart - (double)0.5;
+ if (fa <= -pow(10, precision_width))
+ {
+ intpart--;
+ }
+ }
+ for (i = 0; i < precision_width; i++)
+ {
+ fb = fa / (int32_t)radix;
+ dc = (fa - (int64_t)fb * (int32_t)radix);
+ c = (int32_t)dc;
+ if (c < 0)
+ {
+ uc = (uint32_t)c;
+ c = (int32_t)(~uc) + 1 + '0';
+ }
+ else
+ {
+ c = c + '0';
+ }
+ fa = fb;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ *nstrp++ = (char)'.';
+ ++nlen;
+ a = (int32_t)intpart;
+ if (a == 0)
+ {
+ *nstrp++ = '0';
+ ++nlen;
+ }
+ else
+ {
+ while (a != 0)
+ {
+ b = (int32_t)a / (int32_t)radix;
+ c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+ if (c < 0)
+ {
+ uc = (uint32_t)c;
+ c = (int32_t)(~uc) + 1 + '0';
+ }
+ else
+ {
+ c = c + '0';
+ }
+ a = b;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ }
+ return nlen;
+}
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*!
+ * brief This function outputs its parameters according to a formatted string.
+ *
+ * note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * param[in] fmt_ptr Format string for printf.
+ * param[in] args_ptr Arguments to printf.
+ * param[in] buf pointer to the buffer
+ * param cb print callback function pointer
+ *
+ * return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb)
+{
+ /* va_list ap; */
+ char *p;
+ int32_t c;
+
+ char vstr[33];
+ char *vstrp = NULL;
+ int32_t vlen = 0;
+
+ int32_t done;
+ int32_t count = 0;
+
+ uint32_t field_width;
+ uint32_t precision_width;
+ char *sval;
+ int32_t cval;
+ bool use_caps;
+ uint8_t radix = 0;
+
+#if PRINTF_ADVANCED_ENABLE
+ uint32_t flags_used;
+ int32_t schar, dschar;
+ int64_t ival;
+ uint64_t uval = 0;
+ bool valid_precision_width;
+#else
+ int32_t ival;
+ uint32_t uval = 0;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_FLOAT_ENABLE
+ double fval;
+#endif /* PRINTF_FLOAT_ENABLE */
+
+ /* Start parsing apart the format string and display appropriate formats and data. */
+ for (p = (char *)fmt; (c = *p) != 0; p++)
+ {
+ /*
+ * All formats begin with a '%' marker. Special chars like
+ * '\n' or '\t' are normally converted to the appropriate
+ * character by the __compiler__. Thus, no need for this
+ * routine to account for the '\' character.
+ */
+ if (c != '%')
+ {
+ cb(buf, &count, c, 1);
+ /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
+ continue;
+ }
+
+ use_caps = true;
+
+#if PRINTF_ADVANCED_ENABLE
+ /* First check for specification modifier flags. */
+ flags_used = 0;
+ done = false;
+ while (!done)
+ {
+ switch (*++p)
+ {
+ case '-':
+ flags_used |= kPRINTF_Minus;
+ break;
+ case '+':
+ flags_used |= kPRINTF_Plus;
+ break;
+ case ' ':
+ flags_used |= kPRINTF_Space;
+ break;
+ case '0':
+ flags_used |= kPRINTF_Zero;
+ break;
+ case '#':
+ flags_used |= kPRINTF_Pound;
+ break;
+ default:
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ break;
+ }
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ /* Next check for minimum field width. */
+ field_width = 0;
+ done = false;
+ while (!done)
+ {
+ c = *++p;
+ if ((c >= '0') && (c <= '9'))
+ {
+ field_width = (field_width * 10) + (c - '0');
+ }
+#if PRINTF_ADVANCED_ENABLE
+ else if (c == '*')
+ {
+ field_width = (uint32_t)va_arg(ap, uint32_t);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ }
+ }
+ /* Next check for the width and precision field separator. */
+ precision_width = 6;
+#if PRINTF_ADVANCED_ENABLE
+ valid_precision_width = false;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (*++p == '.')
+ {
+ /* Must get precision field width, if present. */
+ precision_width = 0;
+ done = false;
+ while (!done)
+ {
+ c = *++p;
+ if ((c >= '0') && (c <= '9'))
+ {
+ precision_width = (precision_width * 10) + (c - '0');
+#if PRINTF_ADVANCED_ENABLE
+ valid_precision_width = true;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#if PRINTF_ADVANCED_ENABLE
+ else if (c == '*')
+ {
+ precision_width = (uint32_t)va_arg(ap, uint32_t);
+ valid_precision_width = true;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ }
+ }
+ }
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ /*
+ * Check for the length modifier.
+ */
+ switch (/* c = */ *++p)
+ {
+ case 'h':
+ if (*++p != 'h')
+ {
+ flags_used |= kPRINTF_LengthShortInt;
+ --p;
+ }
+ else
+ {
+ flags_used |= kPRINTF_LengthChar;
+ }
+ break;
+ case 'l':
+ if (*++p != 'l')
+ {
+ flags_used |= kPRINTF_LengthLongInt;
+ --p;
+ }
+ else
+ {
+ flags_used |= kPRINTF_LengthLongLongInt;
+ }
+ break;
+ default:
+ /* we've gone one char too far */
+ --p;
+ break;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ /* Now we're ready to examine the format. */
+ c = *++p;
+ {
+ if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') ||
+ (c == 'b') || (c == 'p') || (c == 'u'))
+ {
+ if ((c == 'd') || (c == 'i'))
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_LengthLongLongInt)
+ {
+ ival = (int64_t)va_arg(ap, int64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ ival = (int32_t)va_arg(ap, int32_t);
+ }
+ vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps);
+ vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+ if (ival < 0)
+ {
+ schar = '-';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Plus)
+ {
+ schar = '+';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Space)
+ {
+ schar = ' ';
+ ++vlen;
+ }
+ else
+ {
+ schar = 0;
+ }
+ }
+ }
+ dschar = false;
+ /* Do the ZERO pad. */
+ if (flags_used & kPRINTF_Zero)
+ {
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+ }
+ }
+ /* The string was built in reverse order, now display in correct order. */
+ if ((!dschar) && schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+
+#if PRINTF_FLOAT_ENABLE
+ if ((c == 'f') || (c == 'F'))
+ {
+ fval = (double)va_arg(ap, double);
+ vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
+ vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+ if (fval < 0)
+ {
+ schar = '-';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Plus)
+ {
+ schar = '+';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Space)
+ {
+ schar = ' ';
+ ++vlen;
+ }
+ else
+ {
+ schar = 0;
+ }
+ }
+ }
+ dschar = false;
+ if (flags_used & kPRINTF_Zero)
+ {
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+ }
+ }
+ if ((!dschar) && schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#endif /* PRINTF_FLOAT_ENABLE */
+ if ((c == 'X') || (c == 'x'))
+ {
+ if (c == 'x')
+ {
+ use_caps = false;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_LengthLongLongInt)
+ {
+ uval = (uint64_t)va_arg(ap, uint64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ uval = (uint32_t)va_arg(ap, uint32_t);
+ }
+ vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps);
+ vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+ dschar = false;
+ if (flags_used & kPRINTF_Zero)
+ {
+ if (flags_used & kPRINTF_Pound)
+ {
+ cb(buf, &count, '0', 1);
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+ dschar = true;
+ }
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ if (flags_used & kPRINTF_Pound)
+ {
+ vlen += 2;
+ }
+ cb(buf, &count, ' ', field_width - vlen);
+ if (flags_used & kPRINTF_Pound)
+ {
+ cb(buf, &count, '0', 1);
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+ dschar = true;
+ }
+ }
+ }
+
+ if ((flags_used & kPRINTF_Pound) && (!dschar))
+ {
+ cb(buf, &count, '0', 1);
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+ vlen += 2;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_LengthLongLongInt)
+ {
+ uval = (uint64_t)va_arg(ap, uint64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ uval = (uint32_t)va_arg(ap, uint32_t);
+ }
+
+ if (c == 'o')
+ {
+ radix = 8;
+ }
+ else if (c == 'b')
+ {
+ radix = 2;
+ }
+ else if (c == 'p')
+ {
+ radix = 16;
+ }
+ else
+ {
+ radix = 10;
+ }
+
+ vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps);
+ vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_Zero)
+ {
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#if !PRINTF_ADVANCED_ENABLE
+ cb(buf, &count, ' ', field_width - vlen);
+#endif /* !PRINTF_ADVANCED_ENABLE */
+ if (vstrp != NULL)
+ {
+ while (*vstrp)
+ {
+ cb(buf, &count, *vstrp--, 1);
+ }
+ }
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_Minus)
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ else if (c == 'c')
+ {
+ cval = (char)va_arg(ap, uint32_t);
+ cb(buf, &count, cval, 1);
+ }
+ else if (c == 's')
+ {
+ sval = (char *)va_arg(ap, char *);
+ if (sval)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (valid_precision_width)
+ {
+ vlen = precision_width;
+ }
+ else
+ {
+ vlen = strlen(sval);
+ }
+#else
+ vlen = strlen(sval);
+#endif /* PRINTF_ADVANCED_ENABLE */
+#if PRINTF_ADVANCED_ENABLE
+ if (!(flags_used & kPRINTF_Minus))
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+
+#if PRINTF_ADVANCED_ENABLE
+ if (valid_precision_width)
+ {
+ while ((*sval) && (vlen > 0))
+ {
+ cb(buf, &count, *sval++, 1);
+ vlen--;
+ }
+ /* In case that vlen sval is shorter than vlen */
+ vlen = precision_width - vlen;
+ }
+ else
+ {
+#endif /* PRINTF_ADVANCED_ENABLE */
+ while (*sval)
+ {
+ cb(buf, &count, *sval++, 1);
+ }
+#if PRINTF_ADVANCED_ENABLE
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_Minus)
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ }
+ else
+ {
+ cb(buf, &count, c, 1);
+ }
+ }
+ }
+
+ return count;
+}
+
+/*!
+ * brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * param[in] line_ptr The input line of ASCII data.
+ * param[in] format Format first points to the format string.
+ * param[in] args_ptr The list of parameters.
+ *
+ * return Number of input items converted and assigned.
+ * retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr)
+{
+ uint8_t base;
+ int8_t neg;
+ /* Identifier for the format string. */
+ char *c = format;
+ char temp;
+ char *buf;
+ /* Flag telling the conversion specification. */
+ uint32_t flag = 0;
+ /* Filed width for the matching input streams. */
+ uint32_t field_width;
+ /* How many arguments are assigned except the suppress. */
+ uint32_t nassigned = 0;
+ /* How many characters are read from the input streams. */
+ uint32_t n_decode = 0;
+
+ int32_t val;
+
+ const char *s;
+ /* Identifier for the input string. */
+ const char *p = line_ptr;
+
+#if SCANF_FLOAT_ENABLE
+ double fnum = 0.0;
+#endif /* SCANF_FLOAT_ENABLE */
+ /* Return EOF error before any conversion. */
+ if (*p == '\0')
+ {
+ return -1;
+ }
+
+ /* Decode directives. */
+ while ((*c) && (*p))
+ {
+ /* Ignore all white-spaces in the format strings. */
+ if (ScanIgnoreWhiteSpace((const char **)&c))
+ {
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ }
+ else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))
+ {
+ /* Ordinary characters. */
+ c++;
+ if (*p == *c)
+ {
+ n_decode++;
+ p++;
+ c++;
+ }
+ else
+ {
+ /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
+ * However, it is deserted now. */
+ break;
+ }
+ }
+ else
+ {
+ /* convernsion specification */
+ c++;
+ /* Reset. */
+ flag = 0;
+ field_width = 0;
+ base = 0;
+
+ /* Loop to get full conversion specification. */
+ while ((*c) && (!(flag & kSCANF_DestMask)))
+ {
+ switch (*c)
+ {
+#if SCANF_ADVANCED_ENABLE
+ case '*':
+ if (flag & kSCANF_Suppress)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+ flag |= kSCANF_Suppress;
+ c++;
+ break;
+ case 'h':
+ if (flag & kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+
+ if (c[1] == 'h')
+ {
+ flag |= kSCANF_LengthChar;
+ c++;
+ }
+ else
+ {
+ flag |= kSCANF_LengthShortInt;
+ }
+ c++;
+ break;
+ case 'l':
+ if (flag & kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+
+ if (c[1] == 'l')
+ {
+ flag |= kSCANF_LengthLongLongInt;
+ c++;
+ }
+ else
+ {
+ flag |= kSCANF_LengthLongInt;
+ }
+ c++;
+ break;
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+ case 'L':
+ if (flag & kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+ flag |= kSCANF_LengthLongLongDouble;
+ c++;
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ case '0':
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ if (field_width)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+ do
+ {
+ field_width = field_width * 10 + *c - '0';
+ c++;
+ } while ((*c >= '0') && (*c <= '9'));
+ break;
+ case 'd':
+ base = 10;
+ flag |= kSCANF_TypeSinged;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'u':
+ base = 10;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'o':
+ base = 8;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'x':
+ case 'X':
+ base = 16;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'i':
+ base = 0;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+#if SCANF_FLOAT_ENABLE
+ case 'a':
+ case 'A':
+ case 'e':
+ case 'E':
+ case 'f':
+ case 'F':
+ case 'g':
+ case 'G':
+ flag |= kSCANF_DestFloat;
+ c++;
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ case 'c':
+ flag |= kSCANF_DestChar;
+ if (!field_width)
+ {
+ field_width = 1;
+ }
+ c++;
+ break;
+ case 's':
+ flag |= kSCANF_DestString;
+ c++;
+ break;
+ default:
+ return nassigned;
+ }
+ }
+
+ if (!(flag & kSCANF_DestMask))
+ {
+ /* Format strings are exhausted. */
+ return nassigned;
+ }
+
+ if (!field_width)
+ {
+ /* Large than length of a line. */
+ field_width = 99;
+ }
+
+ /* Matching strings in input streams and assign to argument. */
+ switch (flag & kSCANF_DestMask)
+ {
+ case kSCANF_DestChar:
+ s = (const char *)p;
+ buf = va_arg(args_ptr, char *);
+ while ((field_width--) && (*p))
+ {
+ if (!(flag & kSCANF_Suppress))
+ {
+ *buf++ = *p++;
+ }
+ else
+ {
+ p++;
+ }
+ n_decode++;
+ }
+
+ if ((!(flag & kSCANF_Suppress)) && (s != p))
+ {
+ nassigned++;
+ }
+ break;
+ case kSCANF_DestString:
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ s = p;
+ buf = va_arg(args_ptr, char *);
+ while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&
+ (*p != '\r') && (*p != '\v') && (*p != '\f'))
+ {
+ if (flag & kSCANF_Suppress)
+ {
+ p++;
+ }
+ else
+ {
+ *buf++ = *p++;
+ }
+ n_decode++;
+ }
+
+ if ((!(flag & kSCANF_Suppress)) && (s != p))
+ {
+ /* Add NULL to end of string. */
+ *buf = '\0';
+ nassigned++;
+ }
+ break;
+ case kSCANF_DestInt:
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ s = p;
+ val = 0;
+ if ((base == 0) || (base == 16))
+ {
+ if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))
+ {
+ base = 16;
+ if (field_width >= 1)
+ {
+ p += 2;
+ n_decode += 2;
+ field_width -= 2;
+ }
+ }
+ }
+
+ if (base == 0)
+ {
+ if (s[0] == '0')
+ {
+ base = 8;
+ }
+ else
+ {
+ base = 10;
+ }
+ }
+
+ neg = 1;
+ switch (*p)
+ {
+ case '-':
+ neg = -1;
+ n_decode++;
+ p++;
+ field_width--;
+ break;
+ case '+':
+ neg = 1;
+ n_decode++;
+ p++;
+ field_width--;
+ break;
+ default:
+ break;
+ }
+
+ while ((*p) && (field_width--))
+ {
+ if ((*p <= '9') && (*p >= '0'))
+ {
+ temp = *p - '0';
+ }
+ else if ((*p <= 'f') && (*p >= 'a'))
+ {
+ temp = *p - 'a' + 10;
+ }
+ else if ((*p <= 'F') && (*p >= 'A'))
+ {
+ temp = *p - 'A' + 10;
+ }
+ else
+ {
+ temp = base;
+ }
+
+ if (temp >= base)
+ {
+ break;
+ }
+ else
+ {
+ val = base * val + temp;
+ }
+ p++;
+ n_decode++;
+ }
+ val *= neg;
+ if (!(flag & kSCANF_Suppress))
+ {
+#if SCANF_ADVANCED_ENABLE
+ switch (flag & kSCANF_LengthMask)
+ {
+ case kSCANF_LengthChar:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed char *) = (signed char)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned char *) = (unsigned char)val;
+ }
+ break;
+ case kSCANF_LengthShortInt:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed short *) = (signed short)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned short *) = (unsigned short)val;
+ }
+ break;
+ case kSCANF_LengthLongInt:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed long int *) = (signed long int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;
+ }
+ break;
+ case kSCANF_LengthLongLongInt:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed long long int *) = (signed long long int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;
+ }
+ break;
+ default:
+ /* The default type is the type int. */
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed int *) = (signed int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+ }
+ break;
+ }
+#else
+ /* The default type is the type int. */
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed int *) = (signed int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+ }
+#endif /* SCANF_ADVANCED_ENABLE */
+ nassigned++;
+ }
+ break;
+#if SCANF_FLOAT_ENABLE
+ case kSCANF_DestFloat:
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ fnum = strtod(p, (char **)&s);
+
+ if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))
+ {
+ break;
+ }
+
+ n_decode += (int)(s) - (int)(p);
+ p = s;
+ if (!(flag & kSCANF_Suppress))
+ {
+ if (flag & kSCANF_LengthLongLongDouble)
+ {
+ *va_arg(args_ptr, double *) = fnum;
+ }
+ else
+ {
+ *va_arg(args_ptr, float *) = (float)fnum;
+ }
+ nassigned++;
+ }
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ default:
+ return nassigned;
+ }
+ }
+ }
+ return nassigned;
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_str.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_str.h new file mode 100644 index 000000000..8255aec40 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_str.h @@ -0,0 +1,66 @@ +/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_STR_H
+#define _FSL_STR_H
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief A function pointer which is used when format printf log.
+ */
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] fmt Format string for printf.
+ * @param[in] ap Arguments to printf.
+ * @param[in] buf pointer to the buffer
+ * @param cb print callbck function pointer
+ *
+ * @return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_STR_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.cproject b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.cproject new file mode 100644 index 000000000..9cf60726c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.cproject @@ -0,0 +1,360 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="com.crt.advproject.config.exe.debug.1736457840">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.1736457840" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.1736457840" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size "${BuildArtifactFileName}"; # arm-none-eabi-objcopy -v -O binary "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.bin" ; # checksum -p ${TargetChip} -d "${BuildArtifactFileBaseName}.bin"; ">
+ <folderInfo id="com.crt.advproject.config.exe.debug.1736457840." name="/" resourcePath="">
+ <toolChain id="com.crt.advproject.toolchain.exe.debug.240336044" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
+ <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1779853764" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
+ <builder buildPath="${workspace_loc:/FreeRTOSDemo}/Debug" id="com.crt.advproject.builder.exe.debug.1263695098" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
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+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="FreeRTOSDemo.null.1072149409" name="FreeRTOSDemo" projectType="com.crt.advproject.projecttype.exe"/>
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+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
+ <sdkName>SDK_2.x_LPC54018-IoT-Module</sdkName>
+ <sdkExample>lpc54018iotmodule_freertos_hello</sdkExample>
+ <sdkVersion>2.7.0</sdkVersion>
+ <sdkComponents>platform.drivers.clock.LPC54018;platform.drivers.power.LPC54018;platform.drivers.common.LPC54018;device.LPC54018_CMSIS.LPC54018;platform.Include_core_cm4.LPC54018;platform.Include_common.LPC54018;platform.Include_dsp.LPC54018;platform.drivers.reset.LPC54018;middleware.amazon_freertos-kernel.heap_4.LPC54018;middleware.amazon_freertos-kernel.LPC54018;middleware.amazon_freertos-kernel.extension.LPC54018;utility.debug_console.LPC54018;component.serial_manager.LPC54018;component.lists.LPC54018;component.usart_adapter.LPC54018;platform.drivers.flexcomm_usart.LPC54018;platform.drivers.flexcomm.LPC54018;component.serial_manager_uart.LPC54018;device.LPC54018_startup.LPC54018;platform.drivers.lpc_iocon.LPC54018;platform.drivers.lpc_gpio.LPC54018;platform.drivers.emc.LPC54018;platform.utilities.assert.LPC54018;platform.utilities.misc_utilities.LPC54018;lpc54018iotmodule_freertos_hello;</sdkComponents>
+ <boardId>lpc54018iotmodule</boardId>
+ <package>LPC54018JET180</package>
+ <core>cm4</core>
+ <coreId>core0_LPC54018</coreId>
+ </storageModule>
+ <storageModule moduleId="com.crt.config">
+ <projectStorage><?xml version="1.0" encoding="UTF-8"?>
+<TargetConfig>
+<Properties property_3="NXP" property_4="LPC54018" property_count="5" version="100300"/>
+<infoList vendor="NXP">
+<info chip="LPC54018" name="LPC54018">
+<chip>
+<name>LPC54018</name>
+<family>LPC540xx</family>
+<vendor>NXP</vendor>
+<memory can_program="true" id="Flash" is_ro="true" size="0" type="Flash"/>
+<memory id="RAM" size="352" type="RAM"/>
+<memoryInstance derived_from="Flash" driver="LPC540xx_SPIFI_SFDP.cfx" edited="true" id="BOARD_FLASH" location="0x10000000" size="0x1000000"/>
+<memoryInstance derived_from="RAM" edited="true" id="SRAMX" location="0x0" size="0x30000"/>
+<memoryInstance derived_from="RAM" edited="true" id="SRAM_0_1_2_3" location="0x20000000" size="0x28000"/>
+<memoryInstance derived_from="RAM" edited="true" id="USB_RAM" location="0x40100000" size="0x2000"/>
+</chip>
+<processor>
+<name gcc_name="cortex-m4">Cortex-M4</name>
+<family>Cortex-M</family>
+</processor>
+</info>
+</infoList>
+</TargetConfig></projectStorage>
+ </storageModule>
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+ <storageModule moduleId="refreshScope"/>
+</cproject>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.project b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.project new file mode 100644 index 000000000..02eb533de --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.project @@ -0,0 +1,102 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>FreeRTOSDemo</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>com.nxp.mcuxpresso.core.datamodels.sdkNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ <nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>Config</name>
+ <type>2</type>
+ <locationURI>PARENT-2-PROJECT_LOC/Config</locationURI>
+ </link>
+ <link>
+ <name>Demo</name>
+ <type>2</type>
+ <locationURI>PARENT-2-PROJECT_LOC/Demo</locationURI>
+ </link>
+ <link>
+ <name>FreeRTOS</name>
+ <type>2</type>
+ <locationURI>PARENT-4-PROJECT_LOC/Source</locationURI>
+ </link>
+ <link>
+ <name>NXP_Code</name>
+ <type>2</type>
+ <locationURI>PARENT-2-PROJECT_LOC/NXP_Code</locationURI>
+ </link>
+ </linkedResources>
+ <filteredResources>
+ <filter>
+ <id>1578832143838</id>
+ <name>FreeRTOS/portable</name>
+ <type>9</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-GCC</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1578832143844</id>
+ <name>FreeRTOS/portable</name>
+ <type>9</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-MemMang</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1578832143849</id>
+ <name>FreeRTOS/portable</name>
+ <type>9</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-Common</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1578832168749</id>
+ <name>FreeRTOS/portable/GCC</name>
+ <type>9</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-ARM_CM4_MPU</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1578832213951</id>
+ <name>FreeRTOS/portable/MemMang</name>
+ <type>5</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-heap_4.c</arguments>
+ </matcher>
+ </filter>
+ </filteredResources>
+</projectDescription>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/FreeRTOSDemo.ld b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/FreeRTOSDemo.ld new file mode 100644 index 000000000..62a213c12 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/FreeRTOSDemo.ld @@ -0,0 +1,362 @@ +GROUP (
+ "libcr_semihost_nf.a"
+ "libcr_c.a"
+ "libcr_eabihelpers.a"
+ "libgcc.a"
+)
+
+/*
+ * LPC54018 does not execute from Flash but from RAM (SRAMX). As a result, the
+ * MPU needs to be programmed to set the portion of SRAMX containing kernel
+ * code as privileged Read Only and the portion of SRAMX containing remaining
+ * of the code as Read Only. To facilitate this, SRAMX is divided into two
+ * parts:
+ * 1. SRAMX_CODE - 128KB. Contains code.
+ * 2. SRAMX_DATA - 64 KB. Contains data (only stack and heap as of now).
+ *
+ * SRAM_0_1_2_3 is of size 160 KB which is not a power of 2. ARM v7 MPU requires
+ * the size of an MPU region to be a power of two. Since FreeRTOS Cortex M4 MPU
+ * port programs MPU to grant access to all SRAM (for tasks created using
+ * xTaskCreate), we need to ensure that the size of SRAM region is a power of
+ * two. This is why SRAM_0_1_2_3 is divided into two parts:
+ * 1. SRAM_0_1_2_3 - 128 KB. Contains data. Since the size is now a power
+ * of two, an MPU region can be used to grant access to it.
+ * 2. SRAM_0_1_2_3_UNUSED - 32 KB. Unused.
+ */
+MEMORY
+{
+ /* Define each memory region. */
+ BOARD_FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x1000000 /* 16M bytes (alias Flash). */
+ SRAMX_CODE (rwx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes. */
+ SRAMX_DATA (rwx) : ORIGIN = 0x20000, LENGTH = 0x10000 /* 64K bytes (alias RAM). */
+ SRAM_0_1_2_3 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000 /* 128K bytes (alias RAM2). */
+ SRAM_0_1_2_3_UNUSED (rwx) : ORIGIN = 0x20020000, LENGTH = 0x8000 /* 32K bytes. */
+ USB_RAM (rwx) : ORIGIN = 0x40100000, LENGTH = 0x2000 /* 8K bytes (alias RAM3). */
+}
+
+/* Initial 32K SRAMX_CODE is used to store kernel functions and
+ * initial 512 bytes of SRAM_0_1_2_3 is used to store kernel data. */
+__privileged_functions_region_size__ = 32K;
+__privileged_data_region_size__ = 512;
+
+/* Symbols needed by the MPU setup code. */
+__FLASH_segment_start__ = ORIGIN( SRAMX_CODE );
+__FLASH_segment_end__ = __FLASH_segment_start__ + LENGTH( SRAMX_CODE );
+__SRAM_segment_start__ = ORIGIN( SRAM_0_1_2_3 );
+__SRAM_segment_end__ = __SRAM_segment_start__ + LENGTH( SRAM_0_1_2_3 );
+
+/* Entry point. */
+ENTRY(ResetISR)
+
+/* Sections. */
+SECTIONS
+{
+ /* The startup code and FreeRTOS kernel code are placed at the beginning
+ * of SRAMX_CODE. */
+ .privileged_functions : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.);
+ __FLASH_segment_start__ = __vectors_start__;
+ __privileged_functions_start__ = __vectors_start__;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table. */
+ . = ALIGN(4);
+ __section_table_start = .;
+
+ __data_section_table = .;
+ LONG((LOADADDR(.data_RAM) - LOADADDR(.privileged_functions)) + ORIGIN(SRAMX_CODE));
+ LONG( ADDR(.data_RAM));
+ LONG( SIZEOF(.data_RAM));
+
+ LONG((LOADADDR(.data) - LOADADDR(.privileged_functions)) + ORIGIN(SRAMX_CODE));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+
+ LONG((LOADADDR(.data_RAM3) - LOADADDR(.privileged_functions)) + ORIGIN(SRAMX_CODE));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ __data_section_table_end = .;
+
+ __bss_section_table = .;
+ LONG( ADDR(.bss_RAM));
+ LONG( SIZEOF(.bss_RAM));
+
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ __bss_section_table_end = .;
+
+ __section_table_end = .;
+ /* End of Global Section Table. */
+
+ /* Functions placed after vector table. */
+ *(.after_vectors*)
+
+ /* Kernel code. */
+ *(privileged_functions)
+
+ FILL(0xDEAD);
+ /* Ensure that non-privileged code is placed after the region reserved for
+ * privileged kernel code. */
+ /* Note that dot (.) actually refers to the byte offset from the start of
+ * the current section (.privileged_functions in this case). As a result,
+ * setting dot (.) to a value sets the size of the section. */
+ . = __privileged_functions_region_size__;
+ __privileged_functions_end__ = .;
+ } > SRAMX_CODE AT> BOARD_FLASH
+
+ /* Text Section. */
+ .text : ALIGN(4)
+ {
+ /* Place the FreeRTOS System Calls first in the unprivileged region. */
+ __syscalls_flash_start__ = .;
+ *(freertos_system_calls)
+ __syscalls_flash_end__ = .;
+
+ /* Unprivileged code and RO data. */
+ *(.text*)
+ KEEP(*freertos*/tasks.o(.rodata*)) /* FreeRTOS Debug Config. */
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > SRAMX_CODE AT> BOARD_FLASH
+
+ /* For exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this. */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > SRAMX_CODE AT> BOARD_FLASH
+
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > SRAMX_CODE AT> BOARD_FLASH
+
+ __exidx_end = .;
+
+ /* End of text section. */
+ _etext = .;
+
+ /* USB_RAM. */
+ .m_usb_data (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > USB_RAM AT> USB_RAM
+
+ /* Data section for SRAMX_DATA. */
+ .data_RAM : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM = .);
+ PROVIDE(__start_data_SRAMX_DATA = .);
+ *(.ramfunc.$RAM)
+ *(.ramfunc.$SRAMX)
+ *(.data.$RAM)
+ *(.data.$SRAMX)
+ *(.data.$RAM.*)
+ *(.data.$SRAMX.*)
+ . = ALIGN(4);
+ PROVIDE(__end_data_RAM = .);
+ PROVIDE(__end_data_SRAMX_DATA = .);
+ } > SRAMX_DATA AT>BOARD_FLASH
+
+ /* Data section for USB_RAM. */
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM3 = .);
+ PROVIDE(__start_data_USB_RAM = .);
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$USB_RAM)
+ *(.data.$RAM3)
+ *(.data.$USB_RAM)
+ *(.data.$RAM3.*)
+ *(.data.$USB_RAM.*)
+ . = ALIGN(4);
+ PROVIDE(__end_data_RAM3 = .);
+ PROVIDE(__end_data_USB_RAM = .);
+ } > USB_RAM AT>BOARD_FLASH
+
+ /* Main Data Section - Reserved. */
+ .uninit_RESERVED (NOLOAD) : ALIGN(4)
+ {
+ _start_uninit_RESERVED = .;
+ __privileged_data_start__ = _start_uninit_RESERVED;
+
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4);
+
+ _end_uninit_RESERVED = .;
+ } > SRAM_0_1_2_3 AT> SRAM_0_1_2_3
+
+ /* Main DATA section (SRAM_0_1_2_3). */
+ .data : ALIGN(4)
+ {
+ _data = .;
+ PROVIDE(__start_data_RAM2 = .);
+ PROVIDE(__start_data_SRAM_0_1_2_3 = .);
+
+ /* FreeRTOS kernel data. */
+ *(privileged_data)
+ FILL(0xDEAD);
+ /* Ensure that non-privileged data is placed after the region reserved for
+ * privileged kernel data. */
+ /* Note that dot (.) actually refers to the byte offset from the start of
+ * the current section (.data in this case). As a result, setting
+ * dot (.) to a value extends the size of the section. */
+ . = __privileged_data_region_size__;
+ __privileged_data_end__ = .;
+
+ FILL(0xff)
+ *(vtable)
+ *(.ramfunc*)
+ KEEP(*(CodeQuickAccess))
+ KEEP(*(DataQuickAccess))
+ *(RamFunction)
+ *(.data*)
+ . = ALIGN(4);
+ _edata = .;
+ PROVIDE(__end_data_RAM2 = .);
+ PROVIDE(__end_data_SRAM_0_1_2_3 = .);
+ } > SRAM_0_1_2_3 AT>BOARD_FLASH
+
+ /* BSS section for SRAMX_DATA. */
+ .bss_RAM : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM = .);
+ PROVIDE(__start_bss_SRAMX_DATA = .);
+ *(.bss.$RAM)
+ *(.bss.$SRAMX)
+ *(.bss.$RAM.*)
+ *(.bss.$SRAMX.*)
+ . = ALIGN (. != 0 ? 4 : 1); /* Avoid empty segment. */
+ PROVIDE(__end_bss_RAM = .);
+ PROVIDE(__end_bss_SRAMX_DATA = .);
+ } > SRAMX_DATA AT> SRAMX_DATA
+
+ /* BSS section for USB_RAM. */
+ .bss_RAM3 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM3 = .);
+ PROVIDE(__start_bss_USB_RAM = .);
+ *(.bss.$RAM3)
+ *(.bss.$USB_RAM)
+ *(.bss.$RAM3.*)
+ *(.bss.$USB_RAM.*)
+ . = ALIGN (. != 0 ? 4 : 1); /* Avoid empty segment. */
+ PROVIDE(__end_bss_RAM3 = .);
+ PROVIDE(__end_bss_USB_RAM = .);
+ } > USB_RAM AT> USB_RAM
+
+ /* Main BSS Section. */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ PROVIDE(__start_bss_RAM2 = .);
+ PROVIDE(__start_bss_SRAM_0_1_2_3 = .);
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ PROVIDE(__end_bss_RAM2 = .);
+ PROVIDE(__end_bss_SRAM_0_1_2_3 = .);
+ PROVIDE(end = .);
+ } > SRAM_0_1_2_3 AT> SRAM_0_1_2_3
+
+ /* NOINIT section for SRAMX_DATA. */
+ .noinit_RAM (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM = .);
+ PROVIDE(__start_noinit_SRAMX_DATA = .);
+ *(.noinit.$RAM)
+ *(.noinit.$SRAMX)
+ *(.noinit.$RAM.*)
+ *(.noinit.$SRAMX.*)
+ . = ALIGN(4);
+ PROVIDE(__end_noinit_RAM = .);
+ PROVIDE(__end_noinit_SRAMX_DATA = .);
+ } > SRAMX_DATA AT> SRAMX_DATA
+
+ /* NOINIT section for USB_RAM. */
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM3 = .);
+ PROVIDE(__start_noinit_USB_RAM = .);
+ *(.noinit.$RAM3)
+ *(.noinit.$USB_RAM)
+ *(.noinit.$RAM3.*)
+ *(.noinit.$USB_RAM.*)
+ . = ALIGN(4);
+ PROVIDE(__end_noinit_RAM3 = .);
+ PROVIDE(__end_noinit_USB_RAM = .);
+ } > USB_RAM AT> USB_RAM
+
+ /* Default NOINIT Section. */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ PROVIDE(__start_noinit_RAM2 = .);
+ PROVIDE(__start_noinit_SRAM_0_1_2_3 = .);
+ *(.noinit*)
+ . = ALIGN(4);
+ _end_noinit = .;
+ PROVIDE(__end_noinit_RAM2 = .);
+ PROVIDE(__end_noinit_SRAM_0_1_2_3 = .);
+ } > SRAM_0_1_2_3 AT> SRAM_0_1_2_3
+
+ /* Reserve and place Heap within memory map. */
+ _HeapSize = 0x1000;
+ .heap : ALIGN(4)
+ {
+ _pvHeapStart = .;
+ . += _HeapSize;
+ . = ALIGN(4);
+ _pvHeapLimit = .;
+ } > SRAMX_DATA
+
+ /* Reserve space in memory for Stack. */
+ _StackSize = 0x1000;
+ .heap2stackfill :
+ {
+ . += _StackSize;
+ } > SRAMX_DATA
+
+ /* Locate actual Stack in memory map. */
+ .stack ORIGIN(SRAMX_DATA) + LENGTH(SRAMX_DATA) - _StackSize - 0: ALIGN(4)
+ {
+ _vStackBase = .;
+ . = ALIGN(4);
+ _vStackTop = . + _StackSize;
+ } > SRAMX_DATA
+
+ /* ## Create checksum value (used in startup). ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined. */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined. */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined. */
+ ) );
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks). */
+ _image_start = LOADADDR(.privileged_functions);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+
+ /* Provide symbols for LPC540xx parts for startup code to use
+ * to set image to be plain load image or XIP.
+ * Config : Plain load image = true. */
+ __imghdr_loadaddress = ADDR(.privileged_functions);
+ __imghdr_imagetype = 1;
+}
\ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c new file mode 100644 index 000000000..f0e1b92e3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c @@ -0,0 +1,48 @@ +/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * @brief Mem fault handler.
+ */
+void MemManage_Handler( void ) __attribute__ (( naked ));
+/*-----------------------------------------------------------*/
+
+void MemManage_Handler( void )
+{
+ __asm volatile
+ (
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, handler_address_const \n"
+ " bx r1 \n"
+ " \n"
+ " handler_address_const: .word vHandleMemoryFault \n"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/semihost_hardfault.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/semihost_hardfault.c new file mode 100644 index 000000000..be4729157 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/semihost_hardfault.c @@ -0,0 +1,109 @@ +// **************************************************************************** +// semihost_hardfault.c +// - Provides hard fault handler to allow semihosting code not +// to hang application when debugger not connected. +// +// **************************************************************************** +// Copyright 2017-2020 NXP +// All rights reserved. +// +// Software that is described herein is for illustrative purposes only +// which provides customers with programming information regarding the +// NXP Cortex-M based MCUs. This software is supplied "AS IS" without any +// warranties of any kind, and NXP Semiconductors and its licensor disclaim any +// and all warranties, express or implied, including all implied warranties of +// merchantability, fitness for a particular purpose and non-infringement of +// intellectual property rights. NXP Semiconductors assumes no responsibility +// or liability for the use of the software, conveys no license or rights under +// any patent, copyright, mask work right, or any other intellectual property +// rights in or to any products. NXP Semiconductors reserves the right to make +// changes in the software without notification. NXP Semiconductors also makes +// no representation or warranty that such application will be suitable for the +// specified use without further testing or modification. +// +// Permission to use, copy, modify, and distribute this software and its +// documentation is hereby granted, under NXP Semiconductors' and its +// licensor's relevant copyrights in the software, without fee, provided that it +// is used in conjunction with NXP Semiconductors microcontrollers. This +// copyright, permission, and disclaimer notice must appear in all copies of +// this code. +// **************************************************************************** +// +// ===== DESCRIPTION ===== +// +// One of the issues with applications that make use of semihosting operations +// (such as printf calls) is that the code will not execute correctly when the +// debugger is not connected. Generally this will show up with the application +// appearing to just hang. This may include the application running from reset +// or powering up the board (with the application already in FLASH), and also +// as the application failing to continue to execute after a debug session is +// terminated. +// +// The problem here is that the "bottom layer" of the semihosted variants of +// the C library, semihosting is implemented by a "BKPT 0xAB" instruction. +// When the debug tools are not connected, this instruction triggers a hard +// fault - and the default hard fault handler within an application will +// typically just contains an infinite loop - causing the application to +// appear to have hang when no debugger is connected. +// +// The below code provides an example hard fault handler which instead looks +// to see what the instruction that caused the hard fault was - and if it +// was a "BKPT 0xAB", then it instead returns back to the user application. +// +// In most cases this will allow applications containing semihosting +// operations to execute (to some degree) when the debugger is not connected. +// +// == NOTE == +// +// Correct execution of the application containing semihosted operations +// which are vectored onto this hard fault handler cannot be guaranteed. This +// is because the handler may not return data or return codes that the higher +// level C library code or application code expects. This hard fault handler +// is meant as a development aid, and it is not recommended to leave +// semihosted code in a production build of your application! +// +// **************************************************************************** + +// Allow handler to be removed by setting a define (via command line) +#if !defined (__SEMIHOST_HARDFAULT_DISABLE) + +__attribute__((naked)) +void HardFault_Handler(void){ + __asm( ".syntax unified\n" + // Check which stack is in use + "MOVS R0, #4 \n" + "MOV R1, LR \n" + "TST R0, R1 \n" + "BEQ _MSP \n" + "MRS R0, PSP \n" + "B _process \n" + "_MSP: \n" + "MRS R0, MSP \n" + // Load the instruction that triggered hard fault + "_process: \n" + "LDR R1,[R0,#24] \n" + "LDRH R2,[r1] \n" + // Semihosting instruction is "BKPT 0xAB" (0xBEAB) + "LDR R3,=0xBEAB \n" + "CMP R2,R3 \n" + "BEQ _semihost_return \n" + // Wasn't semihosting instruction so enter infinite loop + "B . \n" + // Was semihosting instruction, so adjust location to + // return to by 1 instruction (2 bytes), then exit function + "_semihost_return: \n" + "ADDS R1,#2 \n" + "STR R1,[R0,#24] \n" + // Set a return value from semihosting operation. + // 32 is slightly arbitrary, but appears to allow most + // C Library IO functions sitting on top of semihosting to + // continue to operate to some degree + "MOVS R1,#32 \n" + "STR R1,[ R0,#0 ] \n" // R0 is at location 0 on stack + // Return from hard fault handler to application + "BX LR \n" + ".syntax divided\n") ; +} + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/startup_lpc54018.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/startup_lpc54018.c new file mode 100644 index 000000000..37f8fa145 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/startup_lpc54018.c @@ -0,0 +1,820 @@ +//*****************************************************************************
+// LPC54018 startup code for use with MCUXpresso IDE
+//
+// Version : 101019
+//*****************************************************************************
+//
+// Copyright 2016-2019 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC push_options
+#pragma GCC optimize ("Og")
+#endif // (DEBUG)
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+#include <NXP/crp.h>
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
+
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+#if defined (__USE_CMSIS)
+extern void SystemInit(void);
+#endif // (__USE_CMSIS)
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void WDT_BOD_IRQHandler(void);
+WEAK void DMA0_IRQHandler(void);
+WEAK void GINT0_IRQHandler(void);
+WEAK void GINT1_IRQHandler(void);
+WEAK void PIN_INT0_IRQHandler(void);
+WEAK void PIN_INT1_IRQHandler(void);
+WEAK void PIN_INT2_IRQHandler(void);
+WEAK void PIN_INT3_IRQHandler(void);
+WEAK void UTICK0_IRQHandler(void);
+WEAK void MRT0_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void SCT0_IRQHandler(void);
+WEAK void CTIMER3_IRQHandler(void);
+WEAK void FLEXCOMM0_IRQHandler(void);
+WEAK void FLEXCOMM1_IRQHandler(void);
+WEAK void FLEXCOMM2_IRQHandler(void);
+WEAK void FLEXCOMM3_IRQHandler(void);
+WEAK void FLEXCOMM4_IRQHandler(void);
+WEAK void FLEXCOMM5_IRQHandler(void);
+WEAK void FLEXCOMM6_IRQHandler(void);
+WEAK void FLEXCOMM7_IRQHandler(void);
+WEAK void ADC0_SEQA_IRQHandler(void);
+WEAK void ADC0_SEQB_IRQHandler(void);
+WEAK void ADC0_THCMP_IRQHandler(void);
+WEAK void DMIC0_IRQHandler(void);
+WEAK void HWVAD0_IRQHandler(void);
+WEAK void USB0_NEEDCLK_IRQHandler(void);
+WEAK void USB0_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void FLEXCOMM10_IRQHandler(void);
+WEAK void Reserved47_IRQHandler(void);
+WEAK void PIN_INT4_IRQHandler(void);
+WEAK void PIN_INT5_IRQHandler(void);
+WEAK void PIN_INT6_IRQHandler(void);
+WEAK void PIN_INT7_IRQHandler(void);
+WEAK void CTIMER2_IRQHandler(void);
+WEAK void CTIMER4_IRQHandler(void);
+WEAK void RIT_IRQHandler(void);
+WEAK void SPIFI0_IRQHandler(void);
+WEAK void FLEXCOMM8_IRQHandler(void);
+WEAK void FLEXCOMM9_IRQHandler(void);
+WEAK void SDIO_IRQHandler(void);
+WEAK void CAN0_IRQ0_IRQHandler(void);
+WEAK void CAN0_IRQ1_IRQHandler(void);
+WEAK void CAN1_IRQ0_IRQHandler(void);
+WEAK void CAN1_IRQ1_IRQHandler(void);
+WEAK void USB1_IRQHandler(void);
+WEAK void USB1_NEEDCLK_IRQHandler(void);
+WEAK void ETHERNET_IRQHandler(void);
+WEAK void ETHERNET_PMT_IRQHandler(void);
+WEAK void ETHERNET_MACLP_IRQHandler(void);
+WEAK void Reserved68_IRQHandler(void);
+WEAK void LCD_IRQHandler(void);
+WEAK void SHA_IRQHandler(void);
+WEAK void SMARTCARD0_IRQHandler(void);
+WEAK void SMARTCARD1_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMIC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void HWVAD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM10_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved47_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SPIFI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM9_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_PMT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_MACLP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void LCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SHA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SMARTCARD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SMARTCARD1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+
+//*****************************************************************************
+// External declaration for the pointer to the stack top from the Linker Script
+//*****************************************************************************
+extern void _vStackTop(void);
+extern void _image_size(void);
+//*****************************************************************************
+// External declaration for LPC MCU vector table checksum from Linker Script
+//*****************************************************************************
+WEAK extern void __valid_user_code_checksum();
+
+//*****************************************************************************
+// External declaration for image type and load address from Linker Script
+//*****************************************************************************
+WEAK extern void __imghdr_loadaddress();
+WEAK extern void __imghdr_imagetype();
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+#ifndef IMG_BAUDRATE
+#define IMG_BAUDRATE 0
+#endif
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
+
+__attribute__ ((used, section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM4
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ __valid_user_code_checksum, // LPC MCU checksum
+ 0, // ECRP
+ (void (*)(void))0xEDDC94BD, // Reserved
+ (void (*)(void))0x160, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC54018
+ WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect
+ DMA0_IRQHandler, // 17: DMA controller
+ GINT0_IRQHandler, // 18: GPIO group 0
+ GINT1_IRQHandler, // 19: GPIO group 1
+ PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0
+ PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1
+ PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2
+ PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3
+ UTICK0_IRQHandler, // 24: Micro-tick Timer
+ MRT0_IRQHandler, // 25: Multi-rate timer
+ CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0
+ CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1
+ SCT0_IRQHandler, // 28: SCTimer/PWM
+ CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3
+ FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+ FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+ FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+ FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+ FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+ FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+ FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+ FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+ ADC0_SEQA_IRQHandler, // 38: ADC0 sequence A completion.
+ ADC0_SEQB_IRQHandler, // 39: ADC0 sequence B completion.
+ ADC0_THCMP_IRQHandler, // 40: ADC0 threshold compare and error.
+ DMIC0_IRQHandler, // 41: Digital microphone and DMIC subsystem
+ HWVAD0_IRQHandler, // 42: Hardware Voice Activity Detector
+ USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt
+ USB0_IRQHandler, // 44: USB device
+ RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts
+ FLEXCOMM10_IRQHandler, // 46: Flexcomm Interface 10 (SPI, FLEXCOMM)
+ Reserved47_IRQHandler, // 47: Reserved interrupt
+ PIN_INT4_IRQHandler, // 48: Pin interrupt 4 or pattern match engine slice 4 int
+ PIN_INT5_IRQHandler, // 49: Pin interrupt 5 or pattern match engine slice 5 int
+ PIN_INT6_IRQHandler, // 50: Pin interrupt 6 or pattern match engine slice 6 int
+ PIN_INT7_IRQHandler, // 51: Pin interrupt 7 or pattern match engine slice 7 int
+ CTIMER2_IRQHandler, // 52: Standard counter/timer CTIMER2
+ CTIMER4_IRQHandler, // 53: Standard counter/timer CTIMER4
+ RIT_IRQHandler, // 54: Repetitive Interrupt Timer
+ SPIFI0_IRQHandler, // 55: SPI flash interface
+ FLEXCOMM8_IRQHandler, // 56: Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+ FLEXCOMM9_IRQHandler, // 57: Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+ SDIO_IRQHandler, // 58: SD/MMC
+ CAN0_IRQ0_IRQHandler, // 59: CAN0 interrupt0
+ CAN0_IRQ1_IRQHandler, // 60: CAN0 interrupt1
+ CAN1_IRQ0_IRQHandler, // 61: CAN1 interrupt0
+ CAN1_IRQ1_IRQHandler, // 62: CAN1 interrupt1
+ USB1_IRQHandler, // 63: USB1 interrupt
+ USB1_NEEDCLK_IRQHandler, // 64: USB1 activity
+ ETHERNET_IRQHandler, // 65: Ethernet
+ ETHERNET_PMT_IRQHandler, // 66: Ethernet power management interrupt
+ ETHERNET_MACLP_IRQHandler, // 67: Ethernet MAC interrupt
+ Reserved68_IRQHandler, // 68: Reserved interrupt
+ LCD_IRQHandler, // 69: LCD interrupt
+ SHA_IRQHandler, // 70: SHA interrupt
+ SMARTCARD0_IRQHandler, // 71: Smart card 0 interrupt
+ SMARTCARD1_IRQHandler, // 72: Smart card 1 interrupt
+
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ (void (*)(void))0xFEEDA5A5, // Header Marker
+
+#if defined (ADD_CRC)
+ (__imghdr_imagetype - 1), // (0x04) Image Type
+ __imghdr_loadaddress, // (0x08) Load_address
+#else
+ __imghdr_imagetype, // (0x04) Image Type
+ __imghdr_loadaddress, // (0x08) Load_address
+#endif
+ (void (*)(void))(((unsigned)_image_size) - 4), // (0x0C) load_length, exclude 4 bytes CRC field.
+ 0, // (0x10) CRC value (only applicable to NON Non-secure images).
+ 0, // (0x14) Version (only applicable to DUAL_ENH image type.
+ 0, // (0x18) EMC static memory configuration settings, required for EMC boot
+ (void (*)(void))IMG_BAUDRATE, // (0x1C) image baudrate
+ 0, // (0x20) reserved
+ (void (*)(void))0xEDDC94BD, // (0x24) Image_marker
+ 0, // (0x28) SBZ
+ 0, // (0x2C) reserved
+ #ifdef W25Q128JVFM
+ /* SPIFI Descriptor - W25Q128JVFM */
+ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr
+ (void (*)(void))0x001870EF, // mfgId + extCount
+ (void (*)(void))0x00000000, // extid 0-3
+ (void (*)(void))0x00000000, // extid 4-7
+ (void (*)(void))0x0001001D, // caps
+ (void (*)(void))0x00000100, // Blks + RESV1
+ (void (*)(void))0x00010000, // blkSize
+ (void (*)(void))0x00000000, // subBlks + subBlkSize
+ (void (*)(void))0x00000100, // pageSize + RESV2
+ (void (*)(void))0x00003F00, // maxReadSize
+ (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
+ (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
+ (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
+ #endif
+
+ #ifdef MXL12835F
+ /* SPI Descriptor - MXL12835F */
+ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ;DevStrAdr
+ (void (*)(void))0x001820C2, // mfgId + extCount
+ (void (*)(void))0x00000000, // extid 0-3
+ (void (*)(void))0x00000000, // extid 4-7
+ (void (*)(void))0x0001001D, // caps
+ (void (*)(void))0x00000100, // Blks + RESV1
+ (void (*)(void))0x00010000, // blkSize
+ (void (*)(void))0x00000000, // subBlks + subBlkSize
+ (void (*)(void))0x00000100, // pageSize + RESV2
+ (void (*)(void))0x00003F00, // maxReadSize
+ (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
+ (void (*)(void))0x06030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId
+ (void (*)(void))0x14110F0B, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
+ #endif
+
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.init_data")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors.init_bss")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.reset")))
+void ResetISR(void) {
+
+ // Disable interrupts
+ __asm volatile ("cpsid i");
+
+
+ // Enable SRAM clock used by Stack
+ __asm volatile ("LDR R0, =0x40000220\n\t"
+ "MOV R1, #56\n\t"
+ "STR R1, [R0]");
+
+#if defined (__USE_CMSIS)
+// If __USE_CMSIS defined, then call CMSIS SystemInit code
+ SystemInit();
+
+#endif // (__USE_CMSIS)
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will enable the FPU
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+ //
+ // Code to enable the Cortex-M4 FPU only included
+ // if appropriate build options have been selected.
+ // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+ //
+ // Read CPACR (located at address 0xE000ED88)
+ // Set bits 20-23 to enable CP10 and CP11 coprocessors
+ // Write back the modified value to the CPACR
+ asm volatile ("LDR.W R0, =0xE000ED88\n\t"
+ "LDR R1, [R0]\n\t"
+ "ORR R1, R1, #(0xF << 20)\n\t"
+ "STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+#endif // (__USE_CMSIS)
+
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will setup the VTOR register
+
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+ unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+ if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;
+ }
+#endif // (__USE_CMSIS)
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+ // Reenable interrupts
+ __asm volatile ("cpsie i");
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main();
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void HardFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void MemManage_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void BusFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SVC_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void DebugMon_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void PendSV_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SysTick_Handler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void IntDefaultHandler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or IntDefaultHandler() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void WDT_BOD_IRQHandler(void)
+{ WDT_BOD_DriverIRQHandler();
+}
+
+WEAK void DMA0_IRQHandler(void)
+{ DMA0_DriverIRQHandler();
+}
+
+WEAK void GINT0_IRQHandler(void)
+{ GINT0_DriverIRQHandler();
+}
+
+WEAK void GINT1_IRQHandler(void)
+{ GINT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT0_IRQHandler(void)
+{ PIN_INT0_DriverIRQHandler();
+}
+
+WEAK void PIN_INT1_IRQHandler(void)
+{ PIN_INT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT2_IRQHandler(void)
+{ PIN_INT2_DriverIRQHandler();
+}
+
+WEAK void PIN_INT3_IRQHandler(void)
+{ PIN_INT3_DriverIRQHandler();
+}
+
+WEAK void UTICK0_IRQHandler(void)
+{ UTICK0_DriverIRQHandler();
+}
+
+WEAK void MRT0_IRQHandler(void)
+{ MRT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{ CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{ CTIMER1_DriverIRQHandler();
+}
+
+WEAK void SCT0_IRQHandler(void)
+{ SCT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER3_IRQHandler(void)
+{ CTIMER3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM0_IRQHandler(void)
+{ FLEXCOMM0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM1_IRQHandler(void)
+{ FLEXCOMM1_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM2_IRQHandler(void)
+{ FLEXCOMM2_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM3_IRQHandler(void)
+{ FLEXCOMM3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM4_IRQHandler(void)
+{ FLEXCOMM4_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM5_IRQHandler(void)
+{ FLEXCOMM5_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM6_IRQHandler(void)
+{ FLEXCOMM6_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM7_IRQHandler(void)
+{ FLEXCOMM7_DriverIRQHandler();
+}
+
+WEAK void ADC0_SEQA_IRQHandler(void)
+{ ADC0_SEQA_DriverIRQHandler();
+}
+
+WEAK void ADC0_SEQB_IRQHandler(void)
+{ ADC0_SEQB_DriverIRQHandler();
+}
+
+WEAK void ADC0_THCMP_IRQHandler(void)
+{ ADC0_THCMP_DriverIRQHandler();
+}
+
+WEAK void DMIC0_IRQHandler(void)
+{ DMIC0_DriverIRQHandler();
+}
+
+WEAK void HWVAD0_IRQHandler(void)
+{ HWVAD0_DriverIRQHandler();
+}
+
+WEAK void USB0_NEEDCLK_IRQHandler(void)
+{ USB0_NEEDCLK_DriverIRQHandler();
+}
+
+WEAK void USB0_IRQHandler(void)
+{ USB0_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{ RTC_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM10_IRQHandler(void)
+{ FLEXCOMM10_DriverIRQHandler();
+}
+
+WEAK void Reserved47_IRQHandler(void)
+{ Reserved47_DriverIRQHandler();
+}
+
+WEAK void PIN_INT4_IRQHandler(void)
+{ PIN_INT4_DriverIRQHandler();
+}
+
+WEAK void PIN_INT5_IRQHandler(void)
+{ PIN_INT5_DriverIRQHandler();
+}
+
+WEAK void PIN_INT6_IRQHandler(void)
+{ PIN_INT6_DriverIRQHandler();
+}
+
+WEAK void PIN_INT7_IRQHandler(void)
+{ PIN_INT7_DriverIRQHandler();
+}
+
+WEAK void CTIMER2_IRQHandler(void)
+{ CTIMER2_DriverIRQHandler();
+}
+
+WEAK void CTIMER4_IRQHandler(void)
+{ CTIMER4_DriverIRQHandler();
+}
+
+WEAK void RIT_IRQHandler(void)
+{ RIT_DriverIRQHandler();
+}
+
+WEAK void SPIFI0_IRQHandler(void)
+{ SPIFI0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM8_IRQHandler(void)
+{ FLEXCOMM8_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM9_IRQHandler(void)
+{ FLEXCOMM9_DriverIRQHandler();
+}
+
+WEAK void SDIO_IRQHandler(void)
+{ SDIO_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQ0_IRQHandler(void)
+{ CAN0_IRQ0_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQ1_IRQHandler(void)
+{ CAN0_IRQ1_DriverIRQHandler();
+}
+
+WEAK void CAN1_IRQ0_IRQHandler(void)
+{ CAN1_IRQ0_DriverIRQHandler();
+}
+
+WEAK void CAN1_IRQ1_IRQHandler(void)
+{ CAN1_IRQ1_DriverIRQHandler();
+}
+
+WEAK void USB1_IRQHandler(void)
+{ USB1_DriverIRQHandler();
+}
+
+WEAK void USB1_NEEDCLK_IRQHandler(void)
+{ USB1_NEEDCLK_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_IRQHandler(void)
+{ ETHERNET_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_PMT_IRQHandler(void)
+{ ETHERNET_PMT_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_MACLP_IRQHandler(void)
+{ ETHERNET_MACLP_DriverIRQHandler();
+}
+
+WEAK void Reserved68_IRQHandler(void)
+{ Reserved68_DriverIRQHandler();
+}
+
+WEAK void LCD_IRQHandler(void)
+{ LCD_DriverIRQHandler();
+}
+
+WEAK void SHA_IRQHandler(void)
+{ SHA_DriverIRQHandler();
+}
+
+WEAK void SMARTCARD0_IRQHandler(void)
+{ SMARTCARD0_DriverIRQHandler();
+}
+
+WEAK void SMARTCARD1_IRQHandler(void)
+{ SMARTCARD1_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC pop_options
+#endif // (DEBUG)
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