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Parked bits for SDMMC2 and SDMMC4 are part of CFGPAD register rather
than pinmux registers and contains bit for each of their pins.
So updating pinctrl Tegra driver to use bitmask for parked
configuration rather than bit.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
[treding@nvidia.com: reshuffle fields to match driver order]
[treding@nvidia.com: use bitmask 0 for unsupported]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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NVIDIA's Tegra210 support the park bit to make pinmux configuration
enable/disable. If parked bit is 1 then configuration does not apply
and if it is 0 then pinmux configuration applies. This is to support
to avoid any glitch in pinmux configurations.
The parked bit is part of mux register and mux bank and hence it is
not required to have member for the parked_reg and parked bank very
similar to other bit field of the same register.
Remove the need of the parked register and parked bank and get whether
parked function supported or not by parked_bit.
This is to make the parked bit handling same as other fields of mux
registers.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra210 has a parked bit for each pin. Add code to express this by
updating the kernel driver MACROs to add in parked_* fields so that
the kernel can handle them as it sees fit.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra210 changes the pinmux HW in a few ways; at least:
- The set of drive groups is much more 1:1 with the set of pins. Most
pins have an associated drive group register as well as an associated
pinmux register, and most drive groups cover a single pin.
- Some register fields have moved from the drive group registers into
the pinmux registers.
- The set of available options for each pin and group varies relative to
previous chips, and hence the register layouts vary a bit too.
This patch updates tegra-pinmux-scripts minimally to handle these
changes, to a level equivalent to the support for previous chips. For
example, some new options such as per-pin schmitt aren't handled since
the syseng-supplied pinmux spreadsheets don't provide a value for this
option.
csv-to-board-tegra124-xlsx.py is renamed to csv-to-board.py since it now
supports boards using different SoCs, and it's not worth encoding all
supported SoCs in the filename (Tegra30/114 aren't supported by it, hence
the previous naming).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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This aligns the output with what's check into the kernel. There are now
only minor white-space/formatting differences. I'll fix those in the
kernel soon, when I send patched to add Tegra210 SoC support.
Cc: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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A set of scripts to generate Linux kernel and U-Boot pinmux drivers and
board pinmux configuration tables. Also included are scripts to convert
existing Linux kernel pinmux drivers and NV-internal spreadsheets to the
internal data representation.
SoC configuration files are included for Tegra30, Tegra114, and Tegra124.
Board configuration files are included for Jetson TK1 and Venice2.
configs/tegra30.soc
configs/tegra114.soc
configs/tegra124.soc
SoC pin definitions
configs/jetson-tk1.board
configs/venice2.board
Board configurations
soc-to-kernel-pinctrl-driver.py
soc-to-uboot-driver.py
Generate Linux kernel and U-Boot pinmux drivers
board-to-kernel-dt.py
board-to-uboot.py
Generate board configuration tables for the Linux kernel (DT) and
U-Boot.
kernel-pinctrl-driver-to-soc.py
Convert an existing Linux kernel pinmux driver to the internal
representation of an SoC used by this project.
csv-to-board-tegra124-xlsx.py
Convert an NV-internal board configuration spreadsheet to the
internal representation of a board configuration used by this
project.
tegra_pmx_board_parser.py
tegra_pmx_parser_utils.py
tegra_pmx_soc_parser.py
tegra_pmx_utils.py
Internal Python modules used to parse the internal data
representations, and various other utilities.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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