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* x86: handle immediate operands for .insnJan Beulich2023-03-316-4/+182
* x86: allow for multiple immediates in output_disp()Jan Beulich2023-03-311-5/+5
* x86: handle EVEX Disp8 for .insnJan Beulich2023-03-315-1/+149
* x86: process instruction operands for .insnJan Beulich2023-03-316-21/+432
* x86: parse special opcode modifiers for .insnJan Beulich2023-03-311-1/+38
* x86: parse VEX and alike specifiers for .insnJan Beulich2023-03-315-6/+250
* x86: introduce .insn directiveJan Beulich2023-03-316-10/+213
* aarch64: Add the RPRFM instructionRichard Sandiford2023-03-307-1/+186
* aarch64: Add the SVE FCLAMP instructionRichard Sandiford2023-03-308-1/+102
* aarch64: Add new SVE shift instructionsRichard Sandiford2023-03-307-0/+97
* aarch64: Add new SVE saturating conversion instructionsRichard Sandiford2023-03-307-0/+93
* aarch64: Add new SVE dot-product instructionsRichard Sandiford2023-03-309-12/+186
* aarch64: Add the SVE BFMLSL instructionsRichard Sandiford2023-03-307-0/+143
* aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford2023-03-307-0/+352
* aarch64: Add the SME2 UNPK instructionsRichard Sandiford2023-03-307-0/+188
* aarch64: Add the SME2 shift instructionsRichard Sandiford2023-03-3015-3/+384
* aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford2023-03-3014-0/+328
* aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford2023-03-307-0/+102
* aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford2023-03-307-0/+245
* aarch64: Add the SME2 CLAMP instructionsRichard Sandiford2023-03-307-0/+407
* aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford2023-03-307-0/+177
* aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford2023-03-3028-0/+556
* aarch64: Add the SME2 dot-product instructionsRichard Sandiford2023-03-3028-0/+2355
* aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford2023-03-3022-0/+2317
* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-308-0/+2084
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-3015-0/+1129
* aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford2023-03-308-6/+2218
* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-3022-1/+1424
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-3011-12/+746
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-3026-24/+2680
* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-3029-0/+6804
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-3010-2/+1598
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-3015-3/+331
* aarch64; Add support for vector offset rangesRichard Sandiford2023-03-3011-0/+84
* aarch64: Add support for vgx2 and vgx4Richard Sandiford2023-03-3013-1/+119
* aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford2023-03-301-1/+1
* aarch64: Add +sme2Richard Sandiford2023-03-303-0/+6
* aarch64: Prefer register ranges & support wrappingRichard Sandiford2023-03-3011-982/+1038
* aarch64: Add support for strided register listsRichard Sandiford2023-03-304-27/+53
* aarch64: Rename some of GAS's REG_TYPE_* macrosRichard Sandiford2023-03-301-71/+71
* aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford2023-03-301-2/+1
* aarch64: Tweak priorities of parsing-related errorsRichard Sandiford2023-03-302-11/+51
* aarch64: Try to report invalid variants against the closest matchRichard Sandiford2023-03-304-93/+101
* aarch64: Tweak register list errorsRichard Sandiford2023-03-304-20/+18
* aarch64: Make AARCH64_OPDE_REG_LIST take a bitfieldRichard Sandiford2023-03-301-20/+34
* aarch64: Add an operand class for SVE register listsRichard Sandiford2023-03-301-13/+13
* aarch64: Add an error code for out-of-range registersRichard Sandiford2023-03-301-0/+8
* aarch64: Deprioritise AARCH64_OPDE_REG_LISTRichard Sandiford2023-03-301-3/+3
* aarch64: Update operand_mismatch_kind_namesRichard Sandiford2023-03-301-0/+2
* aarch64: Rework reporting of failed register checksRichard Sandiford2023-03-3023-972/+1202
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