diff options
Diffstat (limited to 'zephyr/shim/chip')
38 files changed, 667 insertions, 489 deletions
diff --git a/zephyr/shim/chip/CMakeLists.txt b/zephyr/shim/chip/CMakeLists.txt index 54281508aa..1d58857c11 100644 --- a/zephyr/shim/chip/CMakeLists.txt +++ b/zephyr/shim/chip/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/shim/chip/it8xxx2/CMakeLists.txt b/zephyr/shim/chip/it8xxx2/CMakeLists.txt index 539fd9f029..2a1c9d5909 100644 --- a/zephyr/shim/chip/it8xxx2/CMakeLists.txt +++ b/zephyr/shim/chip/it8xxx2/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/shim/chip/it8xxx2/clock.c b/zephyr/shim/chip/it8xxx2/clock.c index 0e7b7cb39e..14dbc0e7eb 100644 --- a/zephyr/shim/chip/it8xxx2/clock.c +++ b/zephyr/shim/chip/it8xxx2/clock.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,7 +8,6 @@ #include <zephyr/kernel.h> #include <zephyr/logging/log.h> #include <soc.h> -#include <zephyr/zephyr.h> #include <soc/ite_it8xxx2/reg_def_cros.h> #include <zephyr/sys/util.h> @@ -16,21 +15,13 @@ LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); -#define ECPM_NODE DT_INST(0, ite_it8xxx2_ecpm) -#define HAL_ECPM_REG_BASE_ADDR \ - ((struct ecpm_reg *)DT_REG_ADDR_BY_IDX(ECPM_NODE, 0)) -#define PLLFREQ_MASK 0xf +#define ECPM_NODE DT_INST(0, ite_it8xxx2_ecpm) +#define HAL_ECPM_REG_BASE_ADDR \ + ((struct ecpm_reg *)DT_REG_ADDR_BY_IDX(ECPM_NODE, 0)) +#define PLLFREQ_MASK 0xf -static const int pll_reg_to_freq[8] = { - MHZ(8), - MHZ(16), - MHZ(24), - MHZ(32), - MHZ(48), - MHZ(64), - MHZ(72), - MHZ(96) -}; +static const int pll_reg_to_freq[8] = { MHZ(8), MHZ(16), MHZ(24), MHZ(32), + MHZ(48), MHZ(64), MHZ(72), MHZ(96) }; int clock_get_freq(void) { diff --git a/zephyr/shim/chip/it8xxx2/gpio.c b/zephyr/shim/chip/it8xxx2/gpio.c index 3baf128eab..7106b2a294 100644 --- a/zephyr/shim/chip/it8xxx2/gpio.c +++ b/zephyr/shim/chip/it8xxx2/gpio.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h index 692eaa9db0..00aaba05fd 100644 --- a/zephyr/shim/chip/it8xxx2/include/flash_chip.h +++ b/zephyr/shim/chip/it8xxx2/include/flash_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,25 +9,25 @@ * One page program instruction allows maximum 256 bytes (a page) of data * to be programmed. */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE DT_PROP(DT_INST(0, soc_nv_flash), \ - write_block_size) +#define CONFIG_FLASH_WRITE_SIZE \ + DT_PROP(DT_INST(0, soc_nv_flash), write_block_size) /* Erase bank size */ -#define CONFIG_FLASH_ERASE_SIZE DT_PROP(DT_INST(0, soc_nv_flash), \ - erase_block_size) +#define CONFIG_FLASH_ERASE_SIZE \ + DT_PROP(DT_INST(0, soc_nv_flash), erase_block_size) /* Protect bank size */ -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE -#define CONFIG_RO_STORAGE_OFF 0x0 -#define CONFIG_RW_STORAGE_OFF 0x0 +#define CONFIG_RO_STORAGE_OFF 0x0 +#define CONFIG_RW_STORAGE_OFF 0x0 /* * The EC uses the one bank of flash to emulate a SPI-like write protect * register with persistent state. */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_FLASH_SIZE_BYTES / 2 - \ - CONFIG_FW_PSTATE_SIZE) +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF \ + (CONFIG_RO_STORAGE_OFF + CONFIG_RO_SIZE - CONFIG_FW_PSTATE_SIZE) #endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/chip/it8xxx2/keyboard_raw.c b/zephyr/shim/chip/it8xxx2/keyboard_raw.c index 480d528e41..0a117cda14 100644 --- a/zephyr/shim/chip/it8xxx2/keyboard_raw.c +++ b/zephyr/shim/chip/it8xxx2/keyboard_raw.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,7 +8,7 @@ #include <zephyr/device.h> #include <zephyr/logging/log.h> #include <soc.h> -#include <zephyr/zephyr.h> +#include <zephyr/kernel.h> #include "drivers/cros_kb_raw.h" #include "keyboard_raw.h" diff --git a/zephyr/shim/chip/it8xxx2/power_policy.c b/zephyr/shim/chip/it8xxx2/power_policy.c index 7c2e02e258..c8efb0ca96 100644 --- a/zephyr/shim/chip/it8xxx2/power_policy.c +++ b/zephyr/shim/chip/it8xxx2/power_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,7 +6,7 @@ #include <zephyr/pm/pm.h> #include <zephyr/pm/policy.h> #include <soc.h> -#include <zephyr/zephyr.h> +#include <zephyr/kernel.h> #include "system.h" @@ -29,8 +29,8 @@ const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks) * To check if given power state is enabled and * could be used. */ - if (pm_policy_state_lock_is_active( - pm_states[i].state, PM_ALL_SUBSTATES)) { + if (pm_policy_state_lock_is_active(pm_states[i].state, + PM_ALL_SUBSTATES)) { continue; } diff --git a/zephyr/shim/chip/it8xxx2/system.c b/zephyr/shim/chip/it8xxx2/system.c index d9dcd7ccfb..e5f9cc5cf0 100644 --- a/zephyr/shim/chip/it8xxx2/system.c +++ b/zephyr/shim/chip/it8xxx2/system.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/shim/chip/mchp/CMakeLists.txt b/zephyr/shim/chip/mchp/CMakeLists.txt index 0948424275..f59a1be2b1 100644 --- a/zephyr/shim/chip/mchp/CMakeLists.txt +++ b/zephyr/shim/chip/mchp/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/shim/chip/mchp/Kconfig.xec b/zephyr/shim/chip/mchp/Kconfig.xec index 3b18b1c192..28a6b3ea3c 100644 --- a/zephyr/shim/chip/mchp/Kconfig.xec +++ b/zephyr/shim/chip/mchp/Kconfig.xec @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/shim/chip/mchp/clock.c b/zephyr/shim/chip/mchp/clock.c index 3bdb6e4f99..6ee4cd931c 100644 --- a/zephyr/shim/chip/mchp/clock.c +++ b/zephyr/shim/chip/mchp/clock.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,16 +9,15 @@ #include <zephyr/kernel.h> #include <zephyr/logging/log.h> #include <soc.h> -#include <zephyr/zephyr.h> #include "clock_chip.h" #include "module_id.h" LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); -#define PCR_NODE DT_INST(0, microchip_xec_pcr) +#define PCR_NODE DT_INST(0, microchip_xec_pcr) #define HAL_PCR_REG_BASE_ADDR \ - ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0)) + ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0)) int clock_get_freq(void) { diff --git a/zephyr/shim/chip/mchp/gpio.c b/zephyr/shim/chip/mchp/gpio.c index 3a16b9639d..7801c6f7cc 100644 --- a/zephyr/shim/chip/mchp/gpio.c +++ b/zephyr/shim/chip/mchp/gpio.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/shim/chip/mchp/include/clock_chip.h b/zephyr/shim/chip/mchp/include/clock_chip.h index c317ccb415..4c14d60ff9 100644 --- a/zephyr/shim/chip/mchp/include/clock_chip.h +++ b/zephyr/shim/chip/mchp/include/clock_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/shim/chip/mchp/include/flash_chip.h b/zephyr/shim/chip/mchp/include/flash_chip.h index b3677fb45c..de8138614c 100644 --- a/zephyr/shim/chip/mchp/include/flash_chip.h +++ b/zephyr/shim/chip/mchp/include/flash_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,10 +11,10 @@ * Similar to W25X40, both only have one status reg */ #define CONFIG_SPI_FLASH_W25X40 /* Internal SPI flash type. */ -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_ERASE_SIZE 0x1000 -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_ERASE_SIZE 0x1000 +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE /* RO image resides at 4KB offset in protected region * The first 4KB in the protected region starting at offset 0 contains @@ -23,7 +23,7 @@ * RW image is never loaded by the Boot-ROM therefore no TAG or Header * is needed. RW starts at offset 0 in RW storage region. */ -#define CONFIG_RO_STORAGE_OFF 0x1000 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0x1000 +#define CONFIG_RW_STORAGE_OFF 0 #endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/chip/mchp/include/system_chip.h b/zephyr/shim/chip/mchp/include/system_chip.h index a62ea4a525..01cd1e7391 100644 --- a/zephyr/shim/chip/mchp/include/system_chip.h +++ b/zephyr/shim/chip/mchp/include/system_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,18 +6,18 @@ #ifndef __CROS_EC_SYSTEM_CHIP_H_ #define __CROS_EC_SYSTEM_CHIP_H_ -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) +#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) +#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) #undef IS_BIT_SET -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) +#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) /******************************************************************************/ /* Optional M4 Registers */ -#define CPU_MPU_CTRL REG32(0xE000ED94) -#define CPU_MPU_RNR REG32(0xE000ED98) -#define CPU_MPU_RBAR REG32(0xE000ED9C) -#define CPU_MPU_RASR REG32(0xE000EDA0) +#define CPU_MPU_CTRL REG32(0xE000ED94) +#define CPU_MPU_RNR REG32(0xE000ED98) +#define CPU_MPU_RBAR REG32(0xE000ED9C) +#define CPU_MPU_RASR REG32(0xE000EDA0) void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, uint32_t size, uint32_t exeAddr); diff --git a/zephyr/shim/chip/mchp/keyboard_raw.c b/zephyr/shim/chip/mchp/keyboard_raw.c index 0b9280aa41..95ad642d12 100644 --- a/zephyr/shim/chip/mchp/keyboard_raw.c +++ b/zephyr/shim/chip/mchp/keyboard_raw.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,7 +8,7 @@ #include <zephyr/device.h> #include <zephyr/logging/log.h> #include <soc.h> -#include <zephyr/zephyr.h> +#include <zephyr/kernel.h> #include "drivers/cros_kb_raw.h" #include "keyboard_raw.h" diff --git a/zephyr/shim/chip/mchp/system.c b/zephyr/shim/chip/mchp/system.c index 25fdfc9897..35ba806533 100644 --- a/zephyr/shim/chip/mchp/system.c +++ b/zephyr/shim/chip/mchp/system.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,8 +11,7 @@ LOG_MODULE_REGISTER(shim_xec_system, LOG_LEVEL_ERR); -#define GET_BBRAM_OFS(node) \ - DT_PROP(DT_PATH(named_bbram_regions, node), offset) +#define GET_BBRAM_OFS(node) DT_PROP(DT_PATH(named_bbram_regions, node), offset) #define GET_BBRAM_SZ(node) DT_PROP(DT_PATH(named_bbram_regions, node), size) /* diff --git a/zephyr/shim/chip/mchp/system_download_from_flash.c b/zephyr/shim/chip/mchp/system_download_from_flash.c index 99026fe822..ced7f4d89c 100644 --- a/zephyr/shim/chip/mchp/system_download_from_flash.c +++ b/zephyr/shim/chip/mchp/system_download_from_flash.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,30 +10,28 @@ #include "system_chip.h" /* Modules Map */ -#define WDT_NODE DT_INST(0, microchip_xec_watchdog) -#define STRUCT_WDT_REG_BASE_ADDR \ - ((struct wdt_regs *)(DT_REG_ADDR(WDT_NODE))) +#define WDT_NODE DT_INST(0, microchip_xec_watchdog) +#define STRUCT_WDT_REG_BASE_ADDR ((struct wdt_regs *)(DT_REG_ADDR(WDT_NODE))) -#define PCR_NODE DT_INST(0, microchip_xec_pcr) +#define PCR_NODE DT_INST(0, microchip_xec_pcr) #define STRUCT_PCR_REG_BASE_ADDR \ - ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0)) + ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0)) -#define QSPI_NODE DT_INST(0, microchip_xec_qmspi_ldma) +#define QSPI_NODE DT_INST(0, microchip_xec_qmspi_ldma) #define STRUCT_QSPI_REG_BASE_ADDR \ - ((struct qmspi_regs *)(DT_REG_ADDR(QSPI_NODE))) + ((struct qmspi_regs *)(DT_REG_ADDR(QSPI_NODE))) -#define SPI_READ_111 0x03 -#define SPI_READ_111_FAST 0x0b -#define SPI_READ_112_FAST 0x3b +#define SPI_READ_111 0x03 +#define SPI_READ_111_FAST 0x0b +#define SPI_READ_112_FAST 0x3b -#define QSPI_STATUS_DONE \ - (MCHP_QMSPI_STS_DONE | MCHP_QMSPI_STS_DMA_DONE) +#define QSPI_STATUS_DONE (MCHP_QMSPI_STS_DONE | MCHP_QMSPI_STS_DMA_DONE) -#define QSPI_STATUS_ERR \ - (MCHP_QMSPI_STS_TXB_ERR | MCHP_QMSPI_STS_RXB_ERR | \ +#define QSPI_STATUS_ERR \ + (MCHP_QMSPI_STS_TXB_ERR | MCHP_QMSPI_STS_RXB_ERR | \ MCHP_QMSPI_STS_PROG_ERR | MCHP_QMSPI_STS_LDMA_RX_ERR) -noreturn void __keep __attribute__ ((section(".code_in_sram2"))) +noreturn void __keep __attribute__((section(".code_in_sram2"))) __start_qspi(uint32_t resetVectAddr) { struct pcr_regs *pcr = STRUCT_PCR_REG_BASE_ADDR; @@ -79,7 +77,7 @@ uintptr_t __lfw_sram_start = CONFIG_CROS_EC_RAM_BASE + CONFIG_CROS_EC_RAM_SIZE; typedef void (*START_QSPI_IN_SRAM_FP)(uint32_t); void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t resetVectAddr) + uint32_t size, uint32_t resetVectAddr) { struct pcr_regs *pcr = STRUCT_PCR_REG_BASE_ADDR; struct qmspi_regs *qspi = STRUCT_QSPI_REG_BASE_ADDR; @@ -102,16 +100,16 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, qspi->CTRL = BIT(MCHP_QMSPI_C_DESCR_EN_POS); /* Transmit 4 bytes(opcode + 24-bit address) on IO0 */ - qspi->DESCR[0] = (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | - MCHP_QMSPI_C_XFR_UNITS_1 | - MCHP_QMSPI_C_XFR_NUNITS(4) | - MCHP_QMSPI_C_NEXT_DESCR(1)); + qspi->DESCR[0] = + (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | + MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4) | + MCHP_QMSPI_C_NEXT_DESCR(1)); /* Transmit 8 clocks with IO0 and IO1 tri-stated */ - qspi->DESCR[1] = (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | - MCHP_QMSPI_C_XFR_UNITS_1 | - MCHP_QMSPI_C_XFR_NUNITS(2) | - MCHP_QMSPI_C_NEXT_DESCR(2)); + qspi->DESCR[1] = + (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | + MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2) | + MCHP_QMSPI_C_NEXT_DESCR(2)); /* Read using LDMA RX Chan 0, IFM=2x, Last Descriptor, close */ qspi->DESCR[2] = (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | @@ -147,7 +145,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, /* Copy the __start_gdma_in_lpram instructions to LPRAM */ for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++) { *((uint32_t *)__lfw_sram_start + i) = - *(&__flash_lplfw_start + i); + *(&__flash_lplfw_start + i); } /* Call into SRAM routine to start QSPI */ diff --git a/zephyr/shim/chip/mchp/system_external_storage.c b/zephyr/shim/chip/mchp/system_external_storage.c index c326a07328..4250b05fe3 100644 --- a/zephyr/shim/chip/mchp/system_external_storage.c +++ b/zephyr/shim/chip/mchp/system_external_storage.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,12 +13,11 @@ #include "system_chip.h" #include "config_chip.h" -#define MCHP_ECRO_WORD 0x4F524345u /* ASCII ECRO */ -#define MCHP_ECRW_WORD 0x57524345u /* ASCII ECRW */ -#define MCHP_PCR_NODE DT_INST(0, microchip_xec_pcr) +#define MCHP_ECRO_WORD 0x4F524345u /* ASCII ECRO */ +#define MCHP_ECRW_WORD 0x57524345u /* ASCII ECRW */ +#define MCHP_PCR_NODE DT_INST(0, microchip_xec_pcr) -#define GET_BBRAM_OFS(node) \ - DT_PROP(DT_PATH(named_bbram_regions, node), offset) +#define GET_BBRAM_OFS(node) DT_PROP(DT_PATH(named_bbram_regions, node), offset) #define GET_BBRAM_SZ(node) DT_PROP(DT_PATH(named_bbram_regions, node), size) static const struct device *const bbram_dev = @@ -49,8 +48,8 @@ void system_jump_to_booter(void) */ switch (system_get_shrspi_image_copy()) { case EC_IMAGE_RW: - flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF; + flash_offset = + CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF; flash_used = CONFIG_CROS_EC_RW_SIZE; break; case EC_IMAGE_RO: diff --git a/zephyr/shim/chip/npcx/CMakeLists.txt b/zephyr/shim/chip/npcx/CMakeLists.txt index 3019118cf4..79b8cf2a62 100644 --- a/zephyr/shim/chip/npcx/CMakeLists.txt +++ b/zephyr/shim/chip/npcx/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/shim/chip/npcx/Kconfig.npcx b/zephyr/shim/chip/npcx/Kconfig.npcx index b044912ae1..5202d14448 100644 --- a/zephyr/shim/chip/npcx/Kconfig.npcx +++ b/zephyr/shim/chip/npcx/Kconfig.npcx @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -15,4 +15,52 @@ config CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY must be a lower priority than CONFIG_BBRAM_INIT_PRIORITY and must be a higher priority than PLATFORM_EC_SYSTEM_PRE_INIT. +config PLATFORM_EC_CONSOLE_CMD_GPIODBG + bool "Console command: gpiodbg" + depends on SOC_FAMILY_NPCX + help + Enable the "gpiodbg" command. This lists all IO pads used on platform + and turns on/off specific pad's input buffer to observe leakage + current through it. + + Example: + gpiodbg list + + IDX|ON| GPIO | Name + ---+--+------+---------- + 00 |* | io03 | recovery_l + 01 |* | io93 | wp_l + 02 |* | iod2 | ac_present + 03 |* | io00 | power_button_l + 04 |* | io01 | lid_open + 05 |* | io36 | entering_rw + 06 |* | io50 | pch_wake_l + 07 |* | ioc7 | pgood_fan + 08 |* | ioa5 | spi_cs_l + 09 |* | io64 | board_version1 + 10 |* | io65 | board_version2 + 11 |* | io66 | board_version3 + 12 |* | io52 | unused pin + 13 |* | io54 | unused pin + + gpiodbg off 11 + gpiodbg list + + IDX|ON| GPIO | Name + ---+--+------+---------- + 00 |* | io03 | recovery_l + 01 |* | io93 | wp_l + 02 |* | iod2 | ac_present + 03 |* | io00 | power_button_l + 04 |* | io01 | lid_open + 05 |* | io36 | entering_rw + 06 |* | io50 | pch_wake_l + 07 |* | ioc7 | pgood_fan + 08 |* | ioa5 | spi_cs_l + 09 |* | io64 | board_version1 + 10 |* | io65 | board_version2 + 11 | | io66 | board_version3 + 12 |* | io52 | unused pin + 13 |* | io54 | unused pin + endif # PLATFORM_EC diff --git a/zephyr/shim/chip/npcx/clock.c b/zephyr/shim/chip/npcx/clock.c index 4fc9bd12c0..fc483ef775 100644 --- a/zephyr/shim/chip/npcx/clock.c +++ b/zephyr/shim/chip/npcx/clock.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,16 +9,15 @@ #include <zephyr/kernel.h> #include <zephyr/logging/log.h> #include <soc.h> -#include <zephyr/zephyr.h> #include "clock_chip.h" #include "module_id.h" LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); -#define CDCG_NODE DT_INST(0, nuvoton_npcx_pcc) +#define CDCG_NODE DT_INST(0, nuvoton_npcx_pcc) #define HAL_CDCG_REG_BASE_ADDR \ - ((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1)) + ((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1)) int clock_get_freq(void) { @@ -63,7 +62,7 @@ void clock_normal(void) struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR; cdcg_base->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL); - cdcg_base->HFCBCD = (FIUDIV_VAL << 4); + cdcg_base->HFCBCD = (FIUDIV_VAL << 4); } void clock_enable_module(enum module_id module, int enable) diff --git a/zephyr/shim/chip/npcx/gpio.c b/zephyr/shim/chip/npcx/gpio.c index 3baf128eab..e8bf3dfdf5 100644 --- a/zephyr/shim/chip/npcx/gpio.c +++ b/zephyr/shim/chip/npcx/gpio.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,10 +6,13 @@ #include <zephyr/device.h> #include <zephyr/drivers/gpio.h> #include <zephyr/kernel.h> +#include <zephyr/shell/shell.h> #include <zephyr/logging/log.h> #include "gpio/gpio.h" +#include "soc_gpio.h" +#include "util.h" LOG_MODULE_REGISTER(shim_cros_gpio, LOG_LEVEL_ERR); @@ -53,3 +56,142 @@ int gpio_config_unused_pins(void) return 0; } + +#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_GPIODBG +/* + * IO information about each GPIO that is configured in the `named_gpios` and + *` unused_pins` device tree nodes. + */ +struct npcx_io_info { + /* A npcx gpio port device */ + const struct device *dev; + /* A npcx gpio port number */ + int port; + /* Bit number of pin within a npcx gpio port */ + gpio_pin_t pin; + /* GPIO net name */ + const char *name; + /* Enable flag of npcx gpio input buffer */ + bool enable; +}; + +#define NAMED_GPIO_INFO(node) \ + { \ + .dev = DEVICE_DT_GET(DT_GPIO_CTLR(node, gpios)), \ + .port = DT_PROP(DT_GPIO_CTLR(node, gpios), index), \ + .pin = DT_GPIO_PIN(node, gpios), \ + .name = DT_NODE_FULL_NAME(node), \ + .enable = true, \ + }, + +#define UNUSED_GPIO_INFO(node, prop, idx) \ + { \ + .dev = DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(node, prop, idx)), \ + .port = DT_PROP(DT_GPIO_CTLR_BY_IDX(node, prop, idx), index), \ + .pin = DT_GPIO_PIN_BY_IDX(node, prop, idx), \ + .name = "unused pin", \ + .enable = true, \ + }, + +#define NAMED_GPIO_INIT(node) \ + COND_CODE_1(DT_NODE_HAS_PROP(node, gpios), (NAMED_GPIO_INFO(node)), ()) + +static struct npcx_io_info gpio_info[] = { +#if DT_NODE_EXISTS(DT_PATH(named_gpios)) + DT_FOREACH_CHILD(DT_PATH(named_gpios), NAMED_GPIO_INIT) +#endif +#if DT_NODE_EXISTS(DT_PATH(unused_pins)) + DT_FOREACH_PROP_ELEM(DT_PATH(unused_pins), unused_gpios, + UNUSED_GPIO_INFO) +#endif +}; + +static int get_index_from_arg(const struct shell *sh, char **argv, int *index) +{ + char *end_ptr; + int num = strtol(argv[1], &end_ptr, 0); + const int gpio_cnt = ARRAY_SIZE(gpio_info); + + if (*end_ptr != '\0') { + shell_error(sh, "Failed to parse %s", argv[1]); + return -EINVAL; + } + + if (num >= gpio_cnt) { + shell_error(sh, "Index shall be less than %u, was %u", gpio_cnt, + num); + return -EINVAL; + } + + *index = num; + + return 0; +} + +static int cmd_gpio_list_all(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + ARG_UNUSED(argv); + + /* Print header */ + shell_print(sh, "IDX|ON| GPIO | Name"); + shell_print(sh, "---+--+------+----------"); + + /* List all GPIOs in 'named-gpios' and 'unused_pins' DT nodes */ + for (int i = 0; i < ARRAY_SIZE(gpio_info); i++) { + shell_print(sh, "%02d |%s | io%x%x | %s", i, + gpio_info[i].enable ? "*" : " ", gpio_info[i].port, + gpio_info[i].pin, gpio_info[i].name); + } + + return 0; +} + +static int cmd_gpio_turn_on(const struct shell *sh, size_t argc, char **argv) +{ + int index; + int res = get_index_from_arg(sh, argv, &index); + + if (res < 0) { + return res; + } + + /* Turn on GPIO's input buffer by index */ + gpio_info[index].enable = true; + npcx_gpio_enable_io_pads(gpio_info[index].dev, gpio_info[index].pin); + + return 0; +} + +static int cmd_gpio_turn_off(const struct shell *sh, size_t argc, char **argv) +{ + int index; + int res = get_index_from_arg(sh, argv, &index); + + if (res < 0) { + return res; + } + + /* Turn off GPIO's input buffer by index */ + gpio_info[index].enable = false; + npcx_gpio_disable_io_pads(gpio_info[index].dev, gpio_info[index].pin); + + return 0; +} + +SHELL_STATIC_SUBCMD_SET_CREATE( + sub_gpiodbg, + SHELL_CMD_ARG(list, NULL, "List all GPIOs used on platform by index", + cmd_gpio_list_all, 1, 0), + SHELL_CMD_ARG(on, NULL, "<index_in_list> Turn on GPIO's input buffer", + cmd_gpio_turn_on, 2, 0), + SHELL_CMD_ARG(off, NULL, "<index_in_list> Turn off GPIO's input buffer", + cmd_gpio_turn_off, 2, 0), + SHELL_SUBCMD_SET_END /* Array terminated. */ +); + +SHELL_CMD_ARG_REGISTER(gpiodbg, &sub_gpiodbg, + "Commands for power consumption " + "investigation", + NULL, 2, 0); +#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_GPIODBG */ diff --git a/zephyr/shim/chip/npcx/include/clock_chip.h b/zephyr/shim/chip/npcx/include/clock_chip.h index 0c39ed8174..6ecca330b6 100644 --- a/zephyr/shim/chip/npcx/include/clock_chip.h +++ b/zephyr/shim/chip/npcx/include/clock_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h index 1d7a76f1da..362d8b2414 100644 --- a/zephyr/shim/chip/npcx/include/flash_chip.h +++ b/zephyr/shim/chip/npcx/include/flash_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,17 +8,17 @@ #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_ERASE_SIZE 0x10000 -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_ERASE_SIZE 0x10000 +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE /* RO image resides at start of protected region, right after header */ -#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE +#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE #define CONFIG_RW_STORAGE_OFF 0 /* Use 4k sector erase for NPCX monitor flash erase operations. */ -#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000 +#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000 #endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/chip/npcx/include/rom_chip.h b/zephyr/shim/chip/npcx/include/rom_chip.h index aab166e6f1..d59a649c7b 100644 --- a/zephyr/shim/chip/npcx/include/rom_chip.h +++ b/zephyr/shim/chip/npcx/include/rom_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -38,17 +38,17 @@ enum API_RETURN_STATUS_T { }; /* Macro functions of ROM api functions */ -#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40) +#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *)0x40) #define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \ - status) \ - (((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \ - (src_offset, dest_addr, size, sign, exe_addr, status)) + status) \ + (((download_from_flash_ptr)ADDR_DOWNLOAD_FROM_FLASH)( \ + src_offset, dest_addr, size, sign, exe_addr, status)) /* Declarations of ROM api functions */ -typedef void (*download_from_flash_ptr) ( +typedef void (*download_from_flash_ptr)( uint32_t src_offset, /* The offset of the data to be downloaded */ - uint32_t dest_addr, /* The address of the downloaded data in the RAM*/ - uint32_t size, /* Number of bytes to download */ + uint32_t dest_addr, /* The address of the downloaded data in the RAM*/ + uint32_t size, /* Number of bytes to download */ enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */ uint32_t exe_addr, /* jump to this address after download if not zero */ enum API_RETURN_STATUS_T *status /* Status fo download */ diff --git a/zephyr/shim/chip/npcx/include/system_chip.h b/zephyr/shim/chip/npcx/include/system_chip.h index c77c2a8338..2f59ad4627 100644 --- a/zephyr/shim/chip/npcx/include/system_chip.h +++ b/zephyr/shim/chip/npcx/include/system_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,24 +6,24 @@ #ifndef __CROS_EC_SYSTEM_CHIP_H_ #define __CROS_EC_SYSTEM_CHIP_H_ -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) +#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) +#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) /* TODO(b:179900857) Clean this up too */ #undef IS_BIT_SET -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) +#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) /*****************************************************************************/ /* Memory mapping */ -#define CONFIG_LPRAM_BASE 0x40001400 /* memory address of lpwr ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ +#define CONFIG_LPRAM_BASE 0x40001400 /* memory address of lpwr ram */ +#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ /******************************************************************************/ /* Optional M4 Registers */ -#define CPU_MPU_CTRL REG32(0xE000ED94) -#define CPU_MPU_RNR REG32(0xE000ED98) -#define CPU_MPU_RBAR REG32(0xE000ED9C) -#define CPU_MPU_RASR REG32(0xE000EDA0) +#define CPU_MPU_CTRL REG32(0xE000ED94) +#define CPU_MPU_RNR REG32(0xE000ED98) +#define CPU_MPU_RBAR REG32(0xE000ED9C) +#define CPU_MPU_RASR REG32(0xE000EDA0) /* * Region assignment. 7 as the highest, a higher index has a higher priority. @@ -35,18 +35,18 @@ * made mutually exclusive. */ enum mpu_region { - REGION_DATA_RAM = 0, /* For internal data RAM */ - REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ - REGION_CODE_RAM = 2, /* For internal code RAM */ - REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ - REGION_STORAGE = 4, /* For mapped internal storage */ - REGION_STORAGE2 = 5, /* Second region for unaligned size */ - REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ - REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ + REGION_DATA_RAM = 0, /* For internal data RAM */ + REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ + REGION_CODE_RAM = 2, /* For internal code RAM */ + REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ + REGION_STORAGE = 4, /* For mapped internal storage */ + REGION_STORAGE2 = 5, /* Second region for unaligned size */ + REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ + REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ /* only for chips with MPU supporting 16 regions */ - REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ - REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ - REGION_ROLLBACK = 10, /* For rollback */ + REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ + REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ + REGION_ROLLBACK = 10, /* For rollback */ }; /* diff --git a/zephyr/shim/chip/npcx/keyboard_raw.c b/zephyr/shim/chip/npcx/keyboard_raw.c index 86d6af068b..4d43134482 100644 --- a/zephyr/shim/chip/npcx/keyboard_raw.c +++ b/zephyr/shim/chip/npcx/keyboard_raw.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,7 +10,7 @@ #include <zephyr/logging/log.h> #include <soc.h> #include <soc_gpio.h> -#include <zephyr/zephyr.h> +#include <zephyr/kernel.h> #include "drivers/cros_kb_raw.h" #include "keyboard_raw.h" diff --git a/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt b/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt index 661eb86e91..d74881b2d9 100644 --- a/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt +++ b/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c index c5ffd40fb5..e3fecc0cbd 100644 --- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c +++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -54,7 +54,7 @@ void sspi_flash_execute_cmd(uint8_t code, uint8_t cts) /* set UMA_CODE */ NPCX_UMA_CODE = code; /* execute UMA flash transaction */ - NPCX_UMA_CTS = cts; + NPCX_UMA_CTS = cts; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } @@ -81,7 +81,7 @@ void sspi_flash_wait_ready(void) sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY); do { /* Read status register */ - NPCX_UMA_CTS = MASK_RD_1BYTE; + NPCX_UMA_CTS = MASK_RD_1BYTE; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */ @@ -113,7 +113,7 @@ void sspi_flash_set_address(uint32_t dest_addr) } void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes, - const char *data) + const char *data) { unsigned int i; /* Chip Select down. */ @@ -202,7 +202,7 @@ void sspi_flash_physical_erase(int offset, int size) /* Alignment has been checked in upper layer */ for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE, - offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { + offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { /* Enable write */ sspi_flash_write_enable(); /* Set erase address */ @@ -226,7 +226,7 @@ int sspi_flash_verify(int offset, int size, const char *data) uint8_t cmp_data; ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset); - ptr_mram = (uint8_t *)data; + ptr_mram = (uint8_t *)data; result = 1; /* Disable tri-state */ @@ -260,12 +260,11 @@ int sspi_flash_get_image_used(const char *fw_base) for (size--; size > 0 && image[size] != 0xea; size--) ; - return size ? size + 1 : 0; /* 0xea byte IS part of the image */ - + return size ? size + 1 : 0; /* 0xea byte IS part of the image */ } /* Entry function of spi upload function */ -uint32_t __attribute__ ((section(".startup_text"))) +uint32_t __attribute__((section(".startup_text"))) sspi_flash_upload(int spi_offset, int spi_size) { /* @@ -320,7 +319,7 @@ sspi_flash_upload(int spi_offset, int spi_size) /* Start to write */ if (image_base != NULL) sspi_flash_physical_write(spi_offset, sz_image, - image_base); + image_base); /* Verify data */ if (sspi_flash_verify(spi_offset, sz_image, image_base)) *flag_upload |= 0x02; diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h index c5415d94db..80e605eea0 100644 --- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h +++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,11 +7,11 @@ #include <stdint.h> -#define NPCX_MONITOR_UUT_TAG 0xA5075001 -#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 +#define NPCX_MONITOR_UUT_TAG 0xA5075001 +#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 /* Flag to record the progress of programming SPI flash */ -#define SPI_PROGRAMMING_FLAG 0x200C4000 +#define SPI_PROGRAMMING_FLAG 0x200C4000 struct monitor_header_tag { /* offset 0x00: TAG NPCX_MONITOR_TAG */ @@ -23,9 +23,9 @@ struct monitor_header_tag { /* offset 0x0C: The Flash address to be programmed (Absolute address) */ uint32_t dest_addr; /* offset 0x10: Maximum allowable flash clock frequency */ - uint8_t max_clock; + uint8_t max_clock; /* offset 0x11: SPI Flash read mode */ - uint8_t read_mode; + uint8_t read_mode; /* offset 0x12: Reserved */ uint16_t reserved; } __packed; diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld index 03e38b0609..98892babc6 100644 --- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld +++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/zephyr/shim/chip/npcx/npcx_monitor/registers.h b/zephyr/shim/chip/npcx/npcx_monitor/registers.h index cc0a6b96fe..85ab3b2389 100644 --- a/zephyr/shim/chip/npcx/npcx_monitor/registers.h +++ b/zephyr/shim/chip/npcx/npcx_monitor/registers.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -21,32 +21,32 @@ #define REG64_ADDR(addr) ((volatile uint64_t *)(addr)) #define REG32_ADDR(addr) ((volatile uint32_t *)(addr)) #define REG16_ADDR(addr) ((volatile uint16_t *)(addr)) -#define REG8_ADDR(addr) ((volatile uint8_t *)(addr)) +#define REG8_ADDR(addr) ((volatile uint8_t *)(addr)) #define REG64(addr) (*REG64_ADDR(addr)) #define REG32(addr) (*REG32_ADDR(addr)) #define REG16(addr) (*REG16_ADDR(addr)) -#define REG8(addr) (*REG8_ADDR(addr)) +#define REG8(addr) (*REG8_ADDR(addr)) /* Standard macros / definitions */ #define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y)) #define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y)) #ifndef MAX -#define MAX(a, b) \ - ({ \ - __typeof__(a) temp_a = (a); \ - __typeof__(b) temp_b = (b); \ - \ - GENERIC_MAX(temp_a, temp_b); \ +#define MAX(a, b) \ + ({ \ + __typeof__(a) temp_a = (a); \ + __typeof__(b) temp_b = (b); \ + \ + GENERIC_MAX(temp_a, temp_b); \ }) #endif #ifndef MIN -#define MIN(a, b) \ - ({ \ - __typeof__(a) temp_a = (a); \ - __typeof__(b) temp_b = (b); \ - \ - GENERIC_MIN(temp_a, temp_b); \ +#define MIN(a, b) \ + ({ \ + __typeof__(a) temp_a = (a); \ + __typeof__(b) temp_b = (b); \ + \ + GENERIC_MIN(temp_a, temp_b); \ }) #endif #ifndef NULL @@ -58,32 +58,35 @@ * Macro Functions */ /* Bit functions */ -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) -#define UPDATE_BIT(reg, bit, cond) { if (cond) \ - SET_BIT(reg, bit); \ - else \ - CLEAR_BIT(reg, bit); } +#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) +#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) +#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) +#define UPDATE_BIT(reg, bit, cond) \ + { \ + if (cond) \ + SET_BIT(reg, bit); \ + else \ + CLEAR_BIT(reg, bit); \ + } /* Field functions */ -#define GET_POS_FIELD(pos, size) pos -#define GET_SIZE_FIELD(pos, size) size -#define FIELD_POS(field) GET_POS_##field -#define FIELD_SIZE(field) GET_SIZE_##field +#define GET_POS_FIELD(pos, size) pos +#define GET_SIZE_FIELD(pos, size) size +#define FIELD_POS(field) GET_POS_##field +#define FIELD_SIZE(field) GET_SIZE_##field /* Read field functions */ #define GET_FIELD(reg, field) \ _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field)) -#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1)) +#define _GET_FIELD_(reg, f_pos, f_size) \ + (((reg) >> (f_pos)) & ((1 << (f_size)) - 1)) /* Write field functions */ #define SET_FIELD(reg, field, value) \ _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value) -#define _SET_FIELD_(reg, f_pos, f_size, value) \ - ((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \ - | ((value) << (f_pos))) - +#define _SET_FIELD_(reg, f_pos, f_size, value) \ + ((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | \ + ((value) << (f_pos))) /* NPCX7 & NPCX9 */ -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) +#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) /******************************************************************************/ /* @@ -91,270 +94,267 @@ */ /* Modules Map */ -#define NPCX_ESPI_BASE_ADDR 0x4000A000 -#define NPCX_MDC_BASE_ADDR 0x4000C000 -#define NPCX_PMC_BASE_ADDR 0x4000D000 -#define NPCX_SIB_BASE_ADDR 0x4000E000 -#define NPCX_SHI_BASE_ADDR 0x4000F000 -#define NPCX_SHM_BASE_ADDR 0x40010000 -#define NPCX_GDMA_BASE_ADDR 0x40011000 -#define NPCX_FIU_BASE_ADDR 0x40020000 -#define NPCX_KBSCAN_REGS_BASE 0x400A3000 -#define NPCX_WOV_BASE_ADDR 0x400A4000 -#define NPCX_APM_BASE_ADDR 0x400A4800 -#define NPCX_GLUE_REGS_BASE 0x400A5000 -#define NPCX_BBRAM_BASE_ADDR 0x400AF000 -#define NPCX_PS2_BASE_ADDR 0x400B1000 -#define NPCX_HFCG_BASE_ADDR 0x400B5000 -#define NPCX_LFCG_BASE_ADDR 0x400B5100 -#define NPCX_FMUL2_BASE_ADDR 0x400B5200 -#define NPCX_MTC_BASE_ADDR 0x400B7000 -#define NPCX_MSWC_BASE_ADDR 0x400C1000 -#define NPCX_SCFG_BASE_ADDR 0x400C3000 -#define NPCX_KBC_BASE_ADDR 0x400C7000 -#define NPCX_ADC_BASE_ADDR 0x400D1000 -#define NPCX_SPI_BASE_ADDR 0x400D2000 -#define NPCX_PECI_BASE_ADDR 0x400D4000 -#define NPCX_TWD_BASE_ADDR 0x400D8000 +#define NPCX_ESPI_BASE_ADDR 0x4000A000 +#define NPCX_MDC_BASE_ADDR 0x4000C000 +#define NPCX_PMC_BASE_ADDR 0x4000D000 +#define NPCX_SIB_BASE_ADDR 0x4000E000 +#define NPCX_SHI_BASE_ADDR 0x4000F000 +#define NPCX_SHM_BASE_ADDR 0x40010000 +#define NPCX_GDMA_BASE_ADDR 0x40011000 +#define NPCX_FIU_BASE_ADDR 0x40020000 +#define NPCX_KBSCAN_REGS_BASE 0x400A3000 +#define NPCX_WOV_BASE_ADDR 0x400A4000 +#define NPCX_APM_BASE_ADDR 0x400A4800 +#define NPCX_GLUE_REGS_BASE 0x400A5000 +#define NPCX_BBRAM_BASE_ADDR 0x400AF000 +#define NPCX_PS2_BASE_ADDR 0x400B1000 +#define NPCX_HFCG_BASE_ADDR 0x400B5000 +#define NPCX_LFCG_BASE_ADDR 0x400B5100 +#define NPCX_FMUL2_BASE_ADDR 0x400B5200 +#define NPCX_MTC_BASE_ADDR 0x400B7000 +#define NPCX_MSWC_BASE_ADDR 0x400C1000 +#define NPCX_SCFG_BASE_ADDR 0x400C3000 +#define NPCX_KBC_BASE_ADDR 0x400C7000 +#define NPCX_ADC_BASE_ADDR 0x400D1000 +#define NPCX_SPI_BASE_ADDR 0x400D2000 +#define NPCX_PECI_BASE_ADDR 0x400D4000 +#define NPCX_TWD_BASE_ADDR 0x400D8000 /* Multi-Modules Map */ -#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl) * 0x2000L)) -#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl) * 0x2000L)) -#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl) * 0x2000L)) -#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl) * 0x2000L)) -#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl) * 0x2000L)) -#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl) * 0x2000L)) - +#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl)*0x2000L)) +#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl)*0x2000L)) +#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl)*0x2000L)) +#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl)*0x2000L)) +#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl)*0x2000L)) +#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl)*0x2000L)) /******************************************************************************/ /* System Configuration (SCFG) Registers */ -#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000) -#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001) -#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002) -#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006) -#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021) -#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028) -#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029) -#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F) - -#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037) -#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038) -#define BLKSEL 0 +#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000) +#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001) +#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002) +#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006) +#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021) +#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028) +#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029) +#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F) + +#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037) +#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038) +#define BLKSEL 0 /* SCFG register fields */ -#define NPCX_DEVCNT_F_SPI_TRIS 6 -#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) -#define NPCX_DEVCNT_JEN1_HEN 5 -#define NPCX_DEVCNT_JEN0_HEN 4 -#define NPCX_STRPST_TRIST 1 -#define NPCX_STRPST_TEST 2 -#define NPCX_STRPST_JEN1 4 -#define NPCX_STRPST_JEN0 5 -#define NPCX_STRPST_SPI_COMP 7 -#define NPCX_RSTCTL_VCC1_RST_STS 0 -#define NPCX_RSTCTL_DBGRST_STS 1 -#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3 -#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5 -#define NPCX_RSTCTL_HIPRST_MODE 6 -#define NPCX_DEV_CTL4_F_SPI_SLLK 2 -#define NPCX_DEV_CTL4_SPI_SP_SEL 4 -#define NPCX_DEV_CTL4_WP_IF 5 -#define NPCX_DEV_CTL4_VCC1_RST_LK 6 -#define NPCX_DEVPU0_I2C0_0_PUE 0 -#define NPCX_DEVPU0_I2C0_1_PUE 1 -#define NPCX_DEVPU0_I2C1_0_PUE 2 -#define NPCX_DEVPU0_I2C2_0_PUE 4 -#define NPCX_DEVPU0_I2C3_0_PUE 6 -#define NPCX_DEVPU1_F_SPI_PUD_EN 7 +#define NPCX_DEVCNT_F_SPI_TRIS 6 +#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) +#define NPCX_DEVCNT_JEN1_HEN 5 +#define NPCX_DEVCNT_JEN0_HEN 4 +#define NPCX_STRPST_TRIST 1 +#define NPCX_STRPST_TEST 2 +#define NPCX_STRPST_JEN1 4 +#define NPCX_STRPST_JEN0 5 +#define NPCX_STRPST_SPI_COMP 7 +#define NPCX_RSTCTL_VCC1_RST_STS 0 +#define NPCX_RSTCTL_DBGRST_STS 1 +#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3 +#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5 +#define NPCX_RSTCTL_HIPRST_MODE 6 +#define NPCX_DEV_CTL4_F_SPI_SLLK 2 +#define NPCX_DEV_CTL4_SPI_SP_SEL 4 +#define NPCX_DEV_CTL4_WP_IF 5 +#define NPCX_DEV_CTL4_VCC1_RST_LK 6 +#define NPCX_DEVPU0_I2C0_0_PUE 0 +#define NPCX_DEVPU0_I2C0_1_PUE 1 +#define NPCX_DEVPU0_I2C1_0_PUE 2 +#define NPCX_DEVPU0_I2C2_0_PUE 4 +#define NPCX_DEVPU0_I2C3_0_PUE 6 +#define NPCX_DEVPU1_F_SPI_PUD_EN 7 /* DEVALT */ /* pin-mux for SPI/FIU */ -#define NPCX_DEVALT0_SPIP_SL 0 -#define NPCX_DEVALT0_GPIO_NO_SPIP 3 -#define NPCX_DEVALT0_F_SPI_CS1_2 4 -#define NPCX_DEVALT0_F_SPI_CS1_1 5 -#define NPCX_DEVALT0_F_SPI_QUAD 6 -#define NPCX_DEVALT0_NO_F_SPI 7 +#define NPCX_DEVALT0_SPIP_SL 0 +#define NPCX_DEVALT0_GPIO_NO_SPIP 3 +#define NPCX_DEVALT0_F_SPI_CS1_2 4 +#define NPCX_DEVALT0_F_SPI_CS1_1 5 +#define NPCX_DEVALT0_F_SPI_QUAD 6 +#define NPCX_DEVALT0_NO_F_SPI 7 /******************************************************************************/ /* Flash Interface Unit (FIU) Registers */ -#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000) -#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001) -#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002) -#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014) -#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016) -#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017) -#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018) -#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019) -#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A) -#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B) -#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C) -#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D) -#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E) -#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F) -#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020) -#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030) -#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032) -#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033) -#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034) +#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000) +#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001) +#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002) +#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014) +#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016) +#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017) +#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018) +#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019) +#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A) +#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B) +#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C) +#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D) +#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E) +#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F) +#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020) +#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030) +#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032) +#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033) +#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034) /* FIU register fields */ -#define NPCX_RESP_CFG_IAD_EN 0 -#define NPCX_RESP_CFG_DEV_SIZE_EX 2 -#define NPCX_UMA_CTS_A_SIZE 3 -#define NPCX_UMA_CTS_C_SIZE 4 -#define NPCX_UMA_CTS_RD_WR 5 -#define NPCX_UMA_CTS_DEV_NUM 6 -#define NPCX_UMA_CTS_EXEC_DONE 7 -#define NPCX_UMA_ECTS_SW_CS0 0 -#define NPCX_UMA_ECTS_SW_CS1 1 -#define NPCX_UMA_ECTS_SEC_CS 2 -#define NPCX_UMA_ECTS_UMA_LOCK 3 +#define NPCX_RESP_CFG_IAD_EN 0 +#define NPCX_RESP_CFG_DEV_SIZE_EX 2 +#define NPCX_UMA_CTS_A_SIZE 3 +#define NPCX_UMA_CTS_C_SIZE 4 +#define NPCX_UMA_CTS_RD_WR 5 +#define NPCX_UMA_CTS_DEV_NUM 6 +#define NPCX_UMA_CTS_EXEC_DONE 7 +#define NPCX_UMA_ECTS_SW_CS0 0 +#define NPCX_UMA_ECTS_SW_CS1 1 +#define NPCX_UMA_ECTS_SEC_CS 2 +#define NPCX_UMA_ECTS_UMA_LOCK 3 /******************************************************************************/ /* KBC Registers */ -#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000) -#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002) -#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004) -#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006) -#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008) -#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009) -#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A) -#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B) +#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000) +#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002) +#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004) +#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006) +#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008) +#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009) +#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A) +#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B) /* KBC register field */ -#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */ -#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/ -#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */ -#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */ -#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */ -#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */ -#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */ -#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */ +#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */ +#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/ +#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */ +#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */ +#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */ +#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */ +#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */ +#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */ -#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */ +#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */ /******************************************************************************/ /* Timer Watch Dog (TWD) Registers */ -#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000) -#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002) -#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004) -#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006) -#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008) -#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A) -#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C) -#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E) -#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010) +#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000) +#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002) +#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004) +#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006) +#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008) +#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A) +#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C) +#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E) +#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010) /* TWD register fields */ -#define NPCX_TWCFG_LTWCFG 0 -#define NPCX_TWCFG_LTWCP 1 -#define NPCX_TWCFG_LTWDT0 2 -#define NPCX_TWCFG_LWDCNT 3 -#define NPCX_TWCFG_WDCT0I 4 -#define NPCX_TWCFG_WDSDME 5 -#define NPCX_TWCFG_WDRST_MODE 6 -#define NPCX_TWCFG_WDC2POR 7 -#define NPCX_T0CSR_RST 0 -#define NPCX_T0CSR_TC 1 -#define NPCX_T0CSR_WDLTD 3 -#define NPCX_T0CSR_WDRST_STS 4 -#define NPCX_T0CSR_WD_RUN 5 -#define NPCX_T0CSR_TESDIS 7 +#define NPCX_TWCFG_LTWCFG 0 +#define NPCX_TWCFG_LTWCP 1 +#define NPCX_TWCFG_LTWDT0 2 +#define NPCX_TWCFG_LWDCNT 3 +#define NPCX_TWCFG_WDCT0I 4 +#define NPCX_TWCFG_WDSDME 5 +#define NPCX_TWCFG_WDRST_MODE 6 +#define NPCX_TWCFG_WDC2POR 7 +#define NPCX_T0CSR_RST 0 +#define NPCX_T0CSR_TC 1 +#define NPCX_T0CSR_WDLTD 3 +#define NPCX_T0CSR_WDRST_STS 4 +#define NPCX_T0CSR_WD_RUN 5 +#define NPCX_T0CSR_TESDIS 7 /******************************************************************************/ /* SPI Register */ -#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00) -#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02) -#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04) +#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00) +#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02) +#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04) /* SPI register fields */ -#define NPCX_SPI_CTL1_SPIEN 0 -#define NPCX_SPI_CTL1_SNM 1 -#define NPCX_SPI_CTL1_MOD 2 -#define NPCX_SPI_CTL1_EIR 5 -#define NPCX_SPI_CTL1_EIW 6 -#define NPCX_SPI_CTL1_SCM 7 -#define NPCX_SPI_CTL1_SCIDL 8 -#define NPCX_SPI_CTL1_SCDV 9 -#define NPCX_SPI_STAT_BSY 0 -#define NPCX_SPI_STAT_RBF 1 +#define NPCX_SPI_CTL1_SPIEN 0 +#define NPCX_SPI_CTL1_SNM 1 +#define NPCX_SPI_CTL1_MOD 2 +#define NPCX_SPI_CTL1_EIR 5 +#define NPCX_SPI_CTL1_EIW 6 +#define NPCX_SPI_CTL1_SCM 7 +#define NPCX_SPI_CTL1_SCIDL 8 +#define NPCX_SPI_CTL1_SCDV 9 +#define NPCX_SPI_STAT_BSY 0 +#define NPCX_SPI_STAT_RBF 1 /******************************************************************************/ /* Flash Utiltiy definition */ /* * Flash commands for the W25Q16CV SPI flash */ -#define CMD_READ_ID 0x9F -#define CMD_READ_MAN_DEV_ID 0x90 -#define CMD_WRITE_EN 0x06 -#define CMD_WRITE_STATUS 0x50 -#define CMD_READ_STATUS_REG 0x05 -#define CMD_READ_STATUS_REG2 0x35 -#define CMD_WRITE_STATUS_REG 0x01 -#define CMD_FLASH_PROGRAM 0x02 -#define CMD_SECTOR_ERASE 0x20 -#define CMD_BLOCK_32K_ERASE 0x52 -#define CMD_BLOCK_64K_ERASE 0xd8 -#define CMD_PROGRAM_UINT_SIZE 0x08 -#define CMD_PAGE_SIZE 0x00 -#define CMD_READ_ID_TYPE 0x47 -#define CMD_FAST_READ 0x0B +#define CMD_READ_ID 0x9F +#define CMD_READ_MAN_DEV_ID 0x90 +#define CMD_WRITE_EN 0x06 +#define CMD_WRITE_STATUS 0x50 +#define CMD_READ_STATUS_REG 0x05 +#define CMD_READ_STATUS_REG2 0x35 +#define CMD_WRITE_STATUS_REG 0x01 +#define CMD_FLASH_PROGRAM 0x02 +#define CMD_SECTOR_ERASE 0x20 +#define CMD_BLOCK_32K_ERASE 0x52 +#define CMD_BLOCK_64K_ERASE 0xd8 +#define CMD_PROGRAM_UINT_SIZE 0x08 +#define CMD_PAGE_SIZE 0x00 +#define CMD_READ_ID_TYPE 0x47 +#define CMD_FAST_READ 0x0B /* * Status registers for the W25Q16CV SPI flash */ -#define SPI_FLASH_SR2_SUS BIT(7) -#define SPI_FLASH_SR2_CMP BIT(6) -#define SPI_FLASH_SR2_LB3 BIT(5) -#define SPI_FLASH_SR2_LB2 BIT(4) -#define SPI_FLASH_SR2_LB1 BIT(3) -#define SPI_FLASH_SR2_QE BIT(1) -#define SPI_FLASH_SR2_SRP1 BIT(0) -#define SPI_FLASH_SR1_SRP0 BIT(7) -#define SPI_FLASH_SR1_SEC BIT(6) -#define SPI_FLASH_SR1_TB BIT(5) -#define SPI_FLASH_SR1_BP2 BIT(4) -#define SPI_FLASH_SR1_BP1 BIT(3) -#define SPI_FLASH_SR1_BP0 BIT(2) -#define SPI_FLASH_SR1_WEL BIT(1) -#define SPI_FLASH_SR1_BUSY BIT(0) - +#define SPI_FLASH_SR2_SUS BIT(7) +#define SPI_FLASH_SR2_CMP BIT(6) +#define SPI_FLASH_SR2_LB3 BIT(5) +#define SPI_FLASH_SR2_LB2 BIT(4) +#define SPI_FLASH_SR2_LB1 BIT(3) +#define SPI_FLASH_SR2_QE BIT(1) +#define SPI_FLASH_SR2_SRP1 BIT(0) +#define SPI_FLASH_SR1_SRP0 BIT(7) +#define SPI_FLASH_SR1_SEC BIT(6) +#define SPI_FLASH_SR1_TB BIT(5) +#define SPI_FLASH_SR1_BP2 BIT(4) +#define SPI_FLASH_SR1_BP1 BIT(3) +#define SPI_FLASH_SR1_BP0 BIT(2) +#define SPI_FLASH_SR1_WEL BIT(1) +#define SPI_FLASH_SR1_BUSY BIT(0) /* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */ -#define FIU_CHIP_SELECT 0 +#define FIU_CHIP_SELECT 0 /* Create UMA control mask */ -#define MASK(bit) (0x1 << (bit)) -#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */ -#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */ -#define RD_WR 0x05 /* 0: Read 1: Write */ -#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */ -#define EXEC_DONE 0x07 -#define D_SIZE_1 0x01 -#define D_SIZE_2 0x02 -#define D_SIZE_3 0x03 -#define D_SIZE_4 0x04 -#define FLASH_SEL MASK(DEV_NUM) - -#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL) -#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE)) -#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - |MASK(A_SIZE) | D_SIZE_1) -#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1) -#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2) -#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3) -#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4) -#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1) -#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2) -#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3) -#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4) -#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)) -#define MASK_CMD_WR_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(C_SIZE) | D_SIZE_1) -#define MASK_CMD_WR_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(C_SIZE) | D_SIZE_2) -#define MASK_CMD_WR_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(A_SIZE)) - +#define MASK(bit) (0x1 << (bit)) +#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */ +#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */ +#define RD_WR 0x05 /* 0: Read 1: Write */ +#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */ +#define EXEC_DONE 0x07 +#define D_SIZE_1 0x01 +#define D_SIZE_2 0x02 +#define D_SIZE_3 0x03 +#define D_SIZE_4 0x04 +#define FLASH_SEL MASK(DEV_NUM) + +#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL) +#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE)) +#define MASK_CMD_ADR_WR \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE) | D_SIZE_1) +#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1) +#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2) +#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3) +#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4) +#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1) +#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2) +#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3) +#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4) +#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)) +#define MASK_CMD_WR_1BYTE \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_1) +#define MASK_CMD_WR_2BYTE \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_2) +#define MASK_CMD_WR_ADR \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE)) #endif /* __CROS_EC_REGISTERS_H */ diff --git a/zephyr/shim/chip/npcx/power_policy.c b/zephyr/shim/chip/npcx/power_policy.c index 1e5a7b15ce..aea6e62d30 100644 --- a/zephyr/shim/chip/npcx/power_policy.c +++ b/zephyr/shim/chip/npcx/power_policy.c @@ -1,9 +1,9 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ -#include <zephyr/zephyr.h> +#include <zephyr/kernel.h> #include <zephyr/pm/pm.h> #include <zephyr/pm/policy.h> #include <soc.h> diff --git a/zephyr/shim/chip/npcx/shi.c b/zephyr/shim/chip/npcx/shi.c index 9e52228e37..8bec57252d 100644 --- a/zephyr/shim/chip/npcx/shi.c +++ b/zephyr/shim/chip/npcx/shi.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,7 +9,7 @@ #include <zephyr/dt-bindings/clock/npcx_clock.h> #include <zephyr/logging/log.h> #include <soc.h> -#include <zephyr/zephyr.h> +#include <zephyr/kernel.h> #include <ap_power/ap_power.h> #include "chipset.h" @@ -83,12 +83,11 @@ static void shi_init(void) ap_power_ev_init_callback(&cb, shi_power_change, #if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK AP_POWER_RESUME_INIT | - AP_POWER_SUSPEND_COMPLETE + AP_POWER_SUSPEND_COMPLETE #else - AP_POWER_RESUME | - AP_POWER_SUSPEND + AP_POWER_RESUME | AP_POWER_SUSPEND #endif - ); + ); ap_power_ev_add_callback(&cb); if (IS_ENABLED(CONFIG_CROS_SHI_NPCX_DEBUG) || diff --git a/zephyr/shim/chip/npcx/system.c b/zephyr/shim/chip/npcx/system.c index ae28749ec0..2240acea54 100644 --- a/zephyr/shim/chip/npcx/system.c +++ b/zephyr/shim/chip/npcx/system.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -54,9 +54,9 @@ void system_mpu_config(void) CPU_MPU_CTRL = 0x7; /* Create a new MPU Region to allow execution from low-power ram */ - CPU_MPU_RNR = REGION_CHIP_RESERVED; + CPU_MPU_RNR = REGION_CHIP_RESERVED; CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */ - CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */ + CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */ /* * Set region size & attribute and enable region * [31:29] - Reserved. diff --git a/zephyr/shim/chip/npcx/system_download_from_flash.c b/zephyr/shim/chip/npcx/system_download_from_flash.c index f616dc6603..1aef9560d1 100644 --- a/zephyr/shim/chip/npcx/system_download_from_flash.c +++ b/zephyr/shim/chip/npcx/system_download_from_flash.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,40 +11,40 @@ #include "system_chip.h" /* Modules Map */ -#define NPCX_PMC_BASE_ADDR 0x4000D000 -#define NPCX_GDMA_BASE_ADDR 0x40011000 +#define NPCX_PMC_BASE_ADDR 0x4000D000 +#define NPCX_GDMA_BASE_ADDR 0x40011000 /******************************************************************************/ /* GDMA (General DMA) Registers */ -#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000) -#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004) -#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008) -#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C) +#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000) +#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004) +#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008) +#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C) /******************************************************************************/ /* GDMA register fields */ -#define NPCX_GDMA_CTL_GDMAEN 0 -#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2) -#define NPCX_GDMA_CTL_DADIR 4 -#define NPCX_GDMA_CTL_SADIR 5 -#define NPCX_GDMA_CTL_SAFIX 7 -#define NPCX_GDMA_CTL_SIEN 8 -#define NPCX_GDMA_CTL_BME 9 -#define NPCX_GDMA_CTL_SBMS 11 -#define NPCX_GDMA_CTL_TWS FIELD(12, 2) -#define NPCX_GDMA_CTL_DM 15 -#define NPCX_GDMA_CTL_SOFTREQ 16 -#define NPCX_GDMA_CTL_TC 18 -#define NPCX_GDMA_CTL_GDMAERR 20 -#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26 +#define NPCX_GDMA_CTL_GDMAEN 0 +#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2) +#define NPCX_GDMA_CTL_DADIR 4 +#define NPCX_GDMA_CTL_SADIR 5 +#define NPCX_GDMA_CTL_SAFIX 7 +#define NPCX_GDMA_CTL_SIEN 8 +#define NPCX_GDMA_CTL_BME 9 +#define NPCX_GDMA_CTL_SBMS 11 +#define NPCX_GDMA_CTL_TWS FIELD(12, 2) +#define NPCX_GDMA_CTL_DM 15 +#define NPCX_GDMA_CTL_SOFTREQ 16 +#define NPCX_GDMA_CTL_TC 18 +#define NPCX_GDMA_CTL_GDMAERR 20 +#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26 /******************************************************************************/ /* Low Power RAM definitions */ -#define NPCX_LPRAM_CTRL REG32(0x40001044) +#define NPCX_LPRAM_CTRL REG32(0x40001044) /******************************************************************************/ /* Sysjump utilities in low power ram for npcx series. */ -noreturn void __keep __attribute__ ((section(".lowpower_ram2"))) +noreturn void __keep __attribute__((section(".lowpower_ram2"))) __start_gdma(uint32_t exeAddr) { /* Enable GDMA now */ @@ -55,7 +55,7 @@ __start_gdma(uint32_t exeAddr) /* Wait for transfer to complete/fail */ while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) && - !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR)) + !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR)) ; /* Disable GDMA now */ @@ -81,11 +81,11 @@ __start_gdma(uint32_t exeAddr) } /* Begin address of Suspend RAM for little FW (GDMA utilities). */ -#define LFW_OFFSET 0x160 +#define LFW_OFFSET 0x160 uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET; void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t exeAddr) + uint32_t size, uint32_t exeAddr) { int i; uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */ @@ -94,7 +94,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, * it's a thumb branch for cortex-m series CPU. */ void (*__start_gdma_in_lpram)(uint32_t) = - (void(*)(uint32_t))(__lpram_lfw_start | 0x01); + (void (*)(uint32_t))(__lpram_lfw_start | 0x01); /* * Before enabling burst mode for better performance of GDMA, it's @@ -152,7 +152,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, /* Copy the __start_gdma_in_lpram instructions to LPRAM */ for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++) *((uint32_t *)__lpram_lfw_start + i) = - *(&__flash_lplfw_start + i); + *(&__flash_lplfw_start + i); /* Start GDMA in Suspend RAM */ __start_gdma_in_lpram(exeAddr); diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c index 96d13fd94e..81e1968cf4 100644 --- a/zephyr/shim/chip/npcx/system_external_storage.c +++ b/zephyr/shim/chip/npcx/system_external_storage.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,13 +26,13 @@ static const struct device *mdc_dev = DEVICE_DT_GET(DT_NODELABEL(mdc)); static uint32_t fwctrl_cached = 0xFFFFFFFF; #ifdef CONFIG_SOC_SERIES_NPCX7 -#define NPCX_FWCTRL 0x007 -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 +#define NPCX_FWCTRL 0x007 +#define NPCX_FWCTRL_RO_REGION 0 +#define NPCX_FWCTRL_FW_SLOT 1 #elif defined(CONFIG_SOC_SERIES_NPCX9) -#define NPCX_FWCTRL 0x009 -#define NPCX_FWCTRL_RO_REGION 6 -#define NPCX_FWCTRL_FW_SLOT 7 +#define NPCX_FWCTRL 0x009 +#define NPCX_FWCTRL_RO_REGION 6 +#define NPCX_FWCTRL_FW_SLOT 7 #else #error "Unsupported NPCX SoC series." #endif @@ -66,28 +66,28 @@ void system_jump_to_booter(void) */ switch (system_get_shrspi_image_copy()) { case EC_IMAGE_RW: - flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF; + flash_offset = + CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF; flash_used = CONFIG_RW_SIZE; break; #ifdef CONFIG_RW_B case EC_IMAGE_RW_B: flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_B_STORAGE_OFF; + CONFIG_RW_B_STORAGE_OFF; flash_used = CONFIG_RW_SIZE; break; #endif case EC_IMAGE_RO: default: /* Jump to RO by default */ - flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF; + flash_offset = + CONFIG_EC_PROTECTED_STORAGE_OFF + CONFIG_RO_STORAGE_OFF; flash_used = CONFIG_RO_SIZE; break; } /* Make sure the reset vector is inside the destination image */ - addr_entry = *(uintptr_t *)(flash_offset + - CONFIG_MAPPED_STORAGE_BASE + 4); + addr_entry = + *(uintptr_t *)(flash_offset + CONFIG_MAPPED_STORAGE_BASE + 4); /* * Speed up FW download time by increasing clock freq of EC. It will @@ -95,29 +95,34 @@ void system_jump_to_booter(void) */ clock_turbo(); -/* - * npcx9 Rev.1 has the problem for download_from_flash API. - * Workwaroud it by executing the system_download_from_flash function - * in the suspend RAM like npcx5. - * TODO: Removing npcx9 when Rev.2 is available. - */ + /* + * npcx9 Rev.1 has the problem for download_from_flash API. + * Workwaroud it by executing the system_download_from_flash function + * in the suspend RAM like npcx5. + * TODO: Removing npcx9 when Rev.2 is available. + */ /* Bypass for GMDA issue of ROM api utilities */ #if defined(CONFIG_SOC_SERIES_NPCX5) || \ defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API) - system_download_from_flash( - flash_offset, /* The offset of the data in spi flash */ - CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */ - flash_used, /* Number of bytes to download */ - addr_entry /* jump to this address after download */ + system_download_from_flash(flash_offset, /* The offset of the data in + spi flash */ + CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of + downloaded + data */ + flash_used, /* Number of bytes to download */ + addr_entry /* jump to this address after + download */ ); #else - download_from_flash( - flash_offset, /* The offset of the data in spi flash */ - CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */ - flash_used, /* Number of bytes to download */ - SIGN_NO_CHECK, /* Need CRC check or not */ - addr_entry, /* jump to this address after download */ - &status /* Status fo download */ + download_from_flash(flash_offset, /* The offset of the data in spi flash + */ + CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of + downloaded data */ + flash_used, /* Number of bytes to download */ + SIGN_NO_CHECK, /* Need CRC check or not */ + addr_entry, /* jump to this address after download + */ + &status /* Status fo download */ ); #endif } |