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Normally we don't do this, but enough changes have accumulated that
we're doing a tree-wide one-off update of the name & style.
BRANCH=none
BUG=chromium:1098010
TEST=`repo upload` works
Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Adjust configurations to fit SPI image generation
BUG=none
BRANCH=main
TEST=zmake testall
Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: I06da9b78fd3b3f42855ef197a37a18bc11ec3711
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3686761
Reviewed-by: Al Semjonovs <asemjonovs@google.com>
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Add cros_flash driver and related configs
BUG=none
BRANCH=main
TEST=zmake testall
Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: I4b8aadf5820871e0abcff0306eefae634a4ee8df
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3388451
Reviewed-by: Keith Short <keithshort@chromium.org>
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For npcx, sysjump to RO needs the PLATFORM_EC_RO_HEADER_SIZE
information in RW image. However, the dependency of
PLATFORM_EC_RO_HEADER lets RW image can't get this information. This CL
removes the dependency of PLATFORM_EC_RO_HEADER in Kconfig for those
configs & lets RW get this information back.
BRANCH=none
BUG=none
TEST='sysjump RO' correct & without abnormal delay.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I434216a4bcde6663cf363372206566b210236bad
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975170
Reviewed-by: Yuval Peress <peress@chromium.org>
Commit-Queue: Yuval Peress <peress@chromium.org>
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NPCX series ROM code changes the chip basic setting by firmware binary
header for loading the firmware from flash to RAM. All the NPCX series
chips could use it, so those configuration options are moved to
upstream.
The ecst chip version automatic select by CONFIG_SOC_NPCX7MNX.
Currently, the project setting doesn't set to the expected chip part
number. Change the following project to select the target chip &
configure ecst header:
- volteer: npcx7m7fc
- trogdor: npcx7m6fc
- kohaku: npcx7m6fc
BUG=b:184448653
BRANCH=none
TEST=zmake testall
TEST=volteer boot to OS
Cq-Depend: chromium:2872415
Signed-off-by: Yuval Peress <peress@chromium.org>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ieed6c21536401f70950ddd1f18d243b127d896ed
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2867128
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Tested-by: Keith Short <keithshort@chromium.org>
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This CL includes the following:
1. Add core clock to spi clock ratio header option.
2. CMakeLists uses the wrong config name. Fix it.
BUG=None.
BRANCH=None.
TEST=Check the firmware header can set by kconfig.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I106c0b6b5987444a77cf07878736374378bc25f2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2747554
Reviewed-by: Yuval Peress <peress@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Make npcx builds done by zephyr have valid format, this means:
1. Only the first section (RO) should have the header.
2. The header should use the chip information or add new Kconfig
values if needed.
3. This should not be done per board (one centralized place).
Move the cmake logic to generate the header via ecst.py script (
located in the zephyr repository and is used to generate the header
for the npcx chips) to a common place: zephyr/CMakeLists.txt. With
that change, the board-specific CMakeLists.txt is now removed, to
be replaced with a call to set ECST_CHIP_ARG. This value must be
set because zephyr only defines SOC_NPCX7M6FB while our specific chip
is different.
For the same reason, both volteer and kohaku require overriding
zephyr's default CONFIG_FLASH_SIZE for the npcx7m6fb.
Additionally, each build (RO/RW) will no longer generate the final
output using the board's name. This will help zmake find the image
with the header without requiring additional arguments.
BRANCH=none
BUG=b:164421798
TEST=build volteer, flash the joined binary, see it boot
TEST=build kohaku
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I418c138e33812c411503f8260fdaa85059a737c9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2682173
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Shim over the header configuration options for offset/size. Also, this
change sets the flash config option PLATFORM_EC_FLASH to depend on the
PLATFORM_EC_RO_HEADER and removes the hard-coded CONFIG_RO_HDR_SIZE
previously used.
BRANCH=none
BUG=b:174873770
TEST=zmake testall
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: Ia1e56b60770fc85eb2874434e37369a7f369fefd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2678928
Reviewed-by: Simon Glass <sjg@chromium.org>
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