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| author | uwe <uwe@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2008-11-28 21:36:51 +0000 |
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| committer | uwe <uwe@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2008-11-28 21:36:51 +0000 |
| commit | 7bddb369910f3bf32fe33138b8e66cde3faa8922 (patch) | |
| tree | b1e437eb9e184676bc4ca62472bfb103ca4d2196 /spi.h | |
| parent | 26f9fa7080777b1ed6d1c8b06e30520a0efe9537 (diff) | |
| download | flashrom-7bddb369910f3bf32fe33138b8e66cde3faa8922.tar.gz | |
Original v2 revision: 3779
Add support for the AMD/ATI SB600 southbridge SPI functionality.
This has been tested by Uwe Hermann on an RS690/SB600 board.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'spi.h')
| -rw-r--r-- | spi.h | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -80,6 +80,11 @@ #define JEDEC_RDSR_INSIZE 0x01 #define JEDEC_RDSR_BIT_WIP (0x01 << 0) +/* Write Status Enable */ +#define JEDEC_EWSR 0x50 +#define JEDEC_EWSR_OUTSIZE 0x01 +#define JEDEC_EWSR_INSIZE 0x00 + /* Write Status Register */ #define JEDEC_WRSR 0x01 #define JEDEC_WRSR_OUTSIZE 0x02 |