| Commit message (Collapse) | Author | Age | Files | Lines |
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register_programmer suggests that we register a programmer. However,
that function registers a master for a given bus type, and a programmer
may support multiple masters (e.g. SPI, FWH). Rename a few other
functions to be more consistent.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Move hwaccess.h #include from flash.h to individual drivers.
libflashrom users need flash.h, but they do not care about hwaccess.h
and should not see its definitions because they may conflict with
other hardware access functions and #defines used by the libflashrom
user.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Currently spi_aai_write() is implemented without an abstraction
mechanism for the programmer driver. This adds another function
pointer 'write_aai' to struct spi_programmer, which is set to
default_spi_write_aai (renamed spi_aai_write) for all programmers
for now.
A patch which utilises this abstraction in the dediprog driver will
follow.
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The ITE IT87 SPI driver uses a trick to speed up reading and writing:
If a flash chip is 512 kByte or less, the flash chip can be completely
mapped in memory and both read and write accesses are faster that way.
The current IT87 SPI code did use the parallel programmer interface for
memory mapped reads and writes, but that's the wrong abstraction. It has
been fixed to use mmio_read*/mmio_write* for that purpose.
The Winbond W83627 SPI driver uses the same trick in its read path for
all supported chip sizes. Fix it the same way.
Switch internal_chip_readn to use mmio_readn as proper abstraction.
Kudos to Michael Karcher for spotting the bugs.
Reported-by: Johan Svensson <flashrom.js@crypt.se>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Tested-by: Johan Svensson <flashrom.js@crypt.se>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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All programmer access function prototypes except init have been made
static and moved to the respective file.
A few internal functions in flash chip drivers had chipaddr parameters
which are no longer needed.
The lines touched by flashctx changes have been adjusted to 80 columns
except in header files.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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struct flashchip is used only for the flashchips array and for
operations which do not access hardware, e.g. printing a list of
supported flash chips.
struct flashctx (flash context) contains all data available in
struct flashchip, but it also contains runtime information like
mapping addresses. struct flashctx is expected to grow additional
members over time, a prime candidate being programmer info.
struct flashctx contains all of struct flashchip with identical
member layout, but struct flashctx has additional members at the end.
The separation between struct flashchip/flashctx shrinks the memory
requirement of the big flashchips array and allows future extension
of flashctx without having to worry about bloat.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Push those changes forward where needed to prevent new sign
conversion warnings where possible.
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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registered.
All programmers are now calling programmer registration functions and
direct manipulations of buses_supported are not needed/possible anymore.
Note: Programmers without parallel/LPC/FWH chip support should not call
register_par_programmer().
Additional fixes:
Set max_rom_decode.parallel for drkaiser.
Remove abuse of programmer_map_flash_region in it85spi.
Annotate several FIXMEs in it85spi.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-By: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- probe_timing was changed to unsigned although we use negative values
for special cases
- some code was not changed along hence did no longer compile:
* dediprog's read and write functions
* linux_spi's read and write functions
- it introduced a number of new sign conversion warnings
(http://paste.flashrom.org/view.php?id=832)
To be safe this patch reverts all changes made in r1448, a corrected
patch will follow later.
Thanks to idwer for pointing out the problem first!
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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this patch combines three previously posted patches in a revised form.
one is even stolen from Stefan Reinauer (remove umlauts from man page).
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
some parts are
Acked-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006@gmx.net>
the rest is
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Remove the array spi_programmer, replace it by dynamic registration
instead. Also initially start with no busses supported, and switch to
the default non-SPI only for the internal programmer.
Also this patch changes the initialization for the buses_supported variable
from "everything-except-SPI" to "nothing". All programmers have to set the
bus type on their own, and this enables register_spi_programmer to just add
the SPI both for on-board SPI interfaces (where the internal programmer
already detected the other bus types), as well as for external programmers
(where we have the default "none").
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Programmer specific functions are of absolutely no interest to any file
except those dealing with programmer specific actions (special SPI
commands and the generic core).
The new header structure is as follows (and yes, improvements are
possible):
flashchips.h flash chip IDs
chipdrivers.h chip-specific read/write/... functions
flash.h common header for all stuff that doesn't fit elsewhere
hwaccess.h hardware access functions
programmer.h programmer specific functions
coreboot_tables.h header from coreboot, internal programmer only
spi.h SPI command definitions
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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open-coding a variant which only aborts after it is too late.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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compat layer to allow converting the rest of flashrom later.
I actually have patches for most of the remaining conversion, but I
wanted to get this out and reviewed first.
Tested on Intel NM10 by David Hendricks.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Every board-enable function is passed a 'const char *name' (board name)
which is totally useless as the board name was already printed by flashrom
at that point. Also, 95% or so of the board-enables don't use the
parameter anyway. So, drop it.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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unistd.h was only used to get a definition of NULL in all files. Add our
own NULL #define and remove unistd.h from flash.h
stdio.h has no place in flash.h, it should be included only in files
which really need it.
Add #include statements in individual .c files where needed.
Replace a few printf with msg_* to eliminate the need for stdio.h.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- x86/x86_64 (little endian)
- PowerPC (big endian)
- MIPS (big+little endian)
No changes to programmer specific code. This means any drivers with MMIO
access will _not_ suddenly start working on big endian systems, but with
this patch everything is in place to fix them.
Compilation should work on all architectures listed above for all
drivers except nic3com and nicrealtek which require PCI Port IO which is
x86-only for now.
To compile without nic3com and nicrealtek, run
make distclean
make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no
Thanks to Misha Manulis for testing early versions of this patch on
PowerPC (big endian) with the satasii programmer.
Thanks to Segher Boessenkool for design review and for helping out with
compiler tricks and pointing out that we need eieio on PowerPC.
Thanks to Vladimir Serbinenko for compile testing on MIPS (little
endian) and PowerPC (big endian) and for runtime testing on MIPS (little
endian).
Thanks to David Daney for compile testing on MIPS (big endian).
Thanks to Uwe Hermann for compile and runtime testing on x86_64.
DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH!
This patch only provides the infrastructure, but does not convert any
drivers, so flashrom will compile, but it won't do the right thing on
non-x86 platforms.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Misha Manulis <misha@manulis.com>
Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Remove chipdriver.h include from flash.h
Some of the spi programmer drivers required chipdrivers.h, needs fixing later:
it87spi.c
ichspi.c
sb600spi.c
wbsio_spi.c
buspirate_spi.c
ft2232spi.c
bitbang_spi.c
dediprog.c
Signed-off-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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because they print hardware settings and desired configuration. They
help in getting a quick overview of hardware and software state on
startup and shutdown.
Programmer debug messages during flash chip access are mostly a
distraction in logs and should only be enabled if someone is having
problems which are suspected to stem from a programmer hardware or
programmer software bug. Disable those messages by default, they can be
reenabled by #define COMM_DEBUG in the affected programmer file.
An added benefit is a tremendous size reduction in verbose
probe/read/write/erase logs because only flash chip driver messages
remain. In some cases, logs will shrink from 65 MB to 10 kB or less.
The right(tm) fix would be two different debug levels (DEBUG and SPEW)
and the ability to differentiate between programmer debug messages and
flash chip debug messages. Until the design for the message printing
infrastructure is finished, this is the best stop-gap measure we can
get.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Sean Nelson <audioahcked@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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didn't include the automatic erase present in other chip drivers. Since
the majority is definitely auto-erase, change the remaining
explicit-erase cases to be auto-erase as well.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carlos Arnau Perez <cemede@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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length.
Some drivers support only a few combinations of read/write length and
return error otherwise. Having a distinct return code for this error
means we can handle it in upper layers.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested it on Epia-m700 worked okay.
Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
Tested-by: Jakob Bornecrantz <wallbraker@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Some SPI opcodes need to be sent in direct succession after each other
without any chip deselect happening in between. A prominent example is
WREN (Write Enable) directly before PP (Page Program). Intel calls the
first opcode in such a row "preopcode".
Right now, we ignore the direct succession requirement completely and it
works pretty well because most onboard SPI masters have a timing or
heuristics which make the problem disappear.
The FT2232 SPI flasher is different. Since it is an external flasher,
timing is very different to what we can expect from onboard flashers and
this leads to failure at slow speeds.
This patch allows any function to submit multiple SPI commands in a
stream to any flasher. Support in the individual flashers isn't
implemented yet, so there is one generic function which passes the each
command in the stream one-by-one to the command functions of the
selected SPI flash driver.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
Tested-by: Jakob Bornecrantz <wallbraker@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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single chip supported by flashrom.
That means you can tell flashrom to read exactly bytes 12345-56789
(start 12345, length 44445) and it will not fetch a single byte more.
Uwe tested this on one LPC, one SPI, and one parallel flash board.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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And even when it checks if the erase worked, the result of that check is
often ignored.
Convert all erase functions and actually check return codes
almost everywhere.
Check inside all erase_* routines if erase worked, not outside.
erase_sector_jedec and erase_block_jedec have changed prototypes to
enable erase checking.
Uwe successfully tested LPC on an CK804 box and SPI on some SB600 box.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This was partly due to a design problem in the abstraction layer.
There should be exactly two different functions for reading SPI chips:
- memory mapped reads
- SPI command reads.
Each of them should be contained in a separate function, optionally
taking parameters where needed.
This patch solves the problems mentioned above, shortens the code and
makes the code logic a lot more obvious.
Since open-coding the min() function leads to errors, include it in this
patch as well.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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handle the delay on their own if needed.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Urja Rannikko <urjaman@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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It doesn't make sense to probe for SPI chips on a LPC host, nor does it
make sense to probe for LPC chips on a Parallel host.
This change is backwards compatible, but adding host protocol info to
chipset init functions will speed up probing.
Once all chipset init functions are updated and the Winbond W29EE011 and
AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can
be deleted as the W29/A49 conflict magically disappears.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested on real hardware and
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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only differentiates between SPI and non-SPI. Anyone who knows more about
a specific flash chip should feel free to update it.
The existing flashbus variable was abused to denote the SPI controller
type. Use an aptly named variable for that purpose.
Once this patch is merged, the chipset/programmer init functions can set
supported flash chip types and flashrom can automatically select only
matching probe/read/erase/write functions.
A side benefit of that will be the elimination of the Winbond W29EE011
vs. AMIC A49LF040A conflict.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and even open-coded some functions in some places.
wbsio_read/regval -> sio_read
wbsio_write/regwrite -> sio_write
wbsio_mask -> sio_mask
board_biostar_p4m80_m4 now uses existing IT87 functions.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Build-tested on 32bit x86.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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outside AAI mode.
Change SPI architecture to handle 1-byte chunk chip writing differently
from 256-byte chunk chip writing.
Annotate SPI chip write functions with _256 or _1 suffix denoting the
number of bytes they write at maximum.
The 1-byte chunk writing is cut-n-pasted to different SPI drivers right
now. A later patch can move them to the generic spi_chip_write_1.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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should handle such special opcode failure gracefully on ICH and
compatible chipsets.
This fixes chip erase on almost all ICH+VIA SPI masters.
Thanks to Ali Nadalizadeh for helping track down this bug!
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Some coding style and consistency fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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flashrom: Winbond SuperIO SPI driver.
Developed and tested to work on Intel D201GLY in July 2008.
Tested by a helpful person on IRC whose name I've since forgotten. Sorry!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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