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author | Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com> | 2023-04-28 13:01:57 +0530 |
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committer | GitHub <noreply@github.com> | 2023-04-28 13:01:57 +0530 |
commit | 3fcb9a5ad001bb6558e17e82fec7936ad249b6cb (patch) | |
tree | eba03f339579427885c221968cdd663830dce7d2 /FreeRTOS | |
parent | 14a34fc9e5a7338cc118627ba2213edcf64a221b (diff) | |
download | freertos-git-3fcb9a5ad001bb6558e17e82fec7936ad249b6cb.tar.gz |
Add IAR projects for LPC55S69 (#1007)
* Add IAR projects for LPC55S69
* IAR Project for trustzone
* MCUXpresso and IAR projects for non-trustzone (NTZ) ports
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Fix build issues and warnings
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Fix formatting check
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---------
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Diffstat (limited to 'FreeRTOS')
48 files changed, 25781 insertions, 790 deletions
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore index 242758392..38a973882 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore @@ -1,6 +1,9 @@ # IDE autogenerated files. -.settings/ +*.settings.xml *.launch +settings/ +*.ewt +*.dep # Build Artifacts Debug/
\ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c index d3d04719f..d3d04719f 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h index 1362b4556..1362b4556 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h new file mode 100644 index 000000000..65b824b00 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include <intrinsics.h> + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_LPC55S69_cm33_core0.s b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_LPC55S69_cm33_core0.s new file mode 100644 index 000000000..e83185c1b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_LPC55S69_cm33_core0.s @@ -0,0 +1,635 @@ +;/***************************************************************************** +; * @file: startup_LPC55S69_cm33_core0.s +; * @purpose: CMSIS Cortex-M33 Core Device Startup File +; * LPC55S69_cm33_core0 +; * @version: 1.1 +; * @date: 2019-5-16 +; *---------------------------------------------------------------------------- +; * +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2021 NXP +; All rights reserved. +; +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD SecureFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt + DCD DMA0_IRQHandler ; DMA0 controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD ADC0_IRQHandler ; ADC0 + DCD Reserved39_IRQHandler ; Reserved interrupt + DCD ACMP_IRQHandler ; ACMP interrupts + DCD Reserved41_IRQHandler ; Reserved interrupt + DCD Reserved42_IRQHandler ; Reserved interrupt + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts + DCD Reserved55_IRQHandler ; Reserved interrupt + DCD Reserved56_IRQHandler ; Reserved interrupt + DCD Reserved57_IRQHandler ; Reserved interrupt + DCD SDIO_IRQHandler ; SD/MMC + DCD Reserved59_IRQHandler ; Reserved interrupt + DCD Reserved60_IRQHandler ; Reserved interrupt + DCD Reserved61_IRQHandler ; Reserved interrupt + DCD USB1_PHY_IRQHandler ; USB1_PHY + DCD USB1_IRQHandler ; USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ; USB1 activity + DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt + DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt + DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt + DCD PLU_IRQHandler ; PLU interrupt + DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt + DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt + DCD CASER_IRQHandler ; CASPER interrupt + DCD PUF_IRQHandler ; PUF interrupt + DCD PQ_IRQHandler ; PQ interrupt + DCD DMA1_IRQHandler ; DMA1 interrupt + DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) +__Vectors_End + + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + LDR R0, =sfb(CSTACK) + MSR MSPLIM, R0 + CPSIE I ; Unmask interrupts + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_IRQHandler + LDR R0, =ADC0_DriverIRQHandler + BX R0 + PUBWEAK Reserved39_IRQHandler + PUBWEAK Reserved39_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved39_IRQHandler + LDR R0, =Reserved39_DriverIRQHandler + BX R0 + PUBWEAK ACMP_IRQHandler + PUBWEAK ACMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ACMP_IRQHandler + LDR R0, =ACMP_DriverIRQHandler + BX R0 + PUBWEAK Reserved41_IRQHandler + PUBWEAK Reserved41_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved41_IRQHandler + LDR R0, =Reserved41_DriverIRQHandler + BX R0 + PUBWEAK Reserved42_IRQHandler + PUBWEAK Reserved42_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved42_IRQHandler + LDR R0, =Reserved42_DriverIRQHandler + BX R0 + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + PUBWEAK MAILBOX_IRQHandler + PUBWEAK MAILBOX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MAILBOX_IRQHandler + LDR R0, =MAILBOX_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + PUBWEAK OS_EVENT_IRQHandler + PUBWEAK OS_EVENT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +OS_EVENT_IRQHandler + LDR R0, =OS_EVENT_DriverIRQHandler + BX R0 + PUBWEAK Reserved55_IRQHandler + PUBWEAK Reserved55_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved55_IRQHandler + LDR R0, =Reserved55_DriverIRQHandler + BX R0 + PUBWEAK Reserved56_IRQHandler + PUBWEAK Reserved56_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved56_IRQHandler + LDR R0, =Reserved56_DriverIRQHandler + BX R0 + PUBWEAK Reserved57_IRQHandler + PUBWEAK Reserved57_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved57_IRQHandler + LDR R0, =Reserved57_DriverIRQHandler + BX R0 + PUBWEAK SDIO_IRQHandler + PUBWEAK SDIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SDIO_IRQHandler + LDR R0, =SDIO_DriverIRQHandler + BX R0 + PUBWEAK Reserved59_IRQHandler + PUBWEAK Reserved59_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved59_IRQHandler + LDR R0, =Reserved59_DriverIRQHandler + BX R0 + PUBWEAK Reserved60_IRQHandler + PUBWEAK Reserved60_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved60_IRQHandler + LDR R0, =Reserved60_DriverIRQHandler + BX R0 + PUBWEAK Reserved61_IRQHandler + PUBWEAK Reserved61_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved61_IRQHandler + LDR R0, =Reserved61_DriverIRQHandler + BX R0 + PUBWEAK USB1_PHY_IRQHandler + PUBWEAK USB1_PHY_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_PHY_IRQHandler + LDR R0, =USB1_PHY_DriverIRQHandler + BX R0 + PUBWEAK USB1_IRQHandler + PUBWEAK USB1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_IRQHandler + LDR R0, =USB1_DriverIRQHandler + BX R0 + PUBWEAK USB1_NEEDCLK_IRQHandler + PUBWEAK USB1_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_NEEDCLK_IRQHandler + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler + PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_HYPERVISOR_CALL_IRQHandler + LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler + BX R0 + PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler + PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_GPIO_INT0_IRQ0_IRQHandler + LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler + BX R0 + PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler + PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_GPIO_INT0_IRQ1_IRQHandler + LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK PLU_IRQHandler + PUBWEAK PLU_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PLU_IRQHandler + LDR R0, =PLU_DriverIRQHandler + BX R0 + PUBWEAK SEC_VIO_IRQHandler + PUBWEAK SEC_VIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_VIO_IRQHandler + LDR R0, =SEC_VIO_DriverIRQHandler + BX R0 + PUBWEAK HASHCRYPT_IRQHandler + PUBWEAK HASHCRYPT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HASHCRYPT_IRQHandler + LDR R0, =HASHCRYPT_DriverIRQHandler + BX R0 + PUBWEAK CASER_IRQHandler + PUBWEAK CASER_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CASER_IRQHandler + LDR R0, =CASER_DriverIRQHandler + BX R0 + PUBWEAK PUF_IRQHandler + PUBWEAK PUF_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PUF_IRQHandler + LDR R0, =PUF_DriverIRQHandler + BX R0 + PUBWEAK PQ_IRQHandler + PUBWEAK PQ_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PQ_IRQHandler + LDR R0, =PQ_DriverIRQHandler + BX R0 + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM8_IRQHandler + PUBWEAK FLEXCOMM8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM8_IRQHandler + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_DriverIRQHandler +Reserved39_DriverIRQHandler +ACMP_DriverIRQHandler +Reserved41_DriverIRQHandler +Reserved42_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +MAILBOX_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +OS_EVENT_DriverIRQHandler +Reserved55_DriverIRQHandler +Reserved56_DriverIRQHandler +Reserved57_DriverIRQHandler +SDIO_DriverIRQHandler +Reserved59_DriverIRQHandler +Reserved60_DriverIRQHandler +Reserved61_DriverIRQHandler +USB1_PHY_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +SEC_HYPERVISOR_CALL_DriverIRQHandler +SEC_GPIO_INT0_IRQ0_DriverIRQHandler +SEC_GPIO_INT0_IRQ1_DriverIRQHandler +PLU_DriverIRQHandler +SEC_VIO_DriverIRQHandler +HASHCRYPT_DriverIRQHandler +CASER_DriverIRQHandler +PUF_DriverIRQHandler +PQ_DriverIRQHandler +DMA1_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +DefaultISR + B . + + END diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.c index d3a18c74d..ee665709a 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.c @@ -1,272 +1,272 @@ -/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: TEE v3.0
-processor: LPC55S69
-package_id: LPC55S69JBD100
-mcu_data: ksdk2_0
-processor_version: 0.10.1
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/***********************************************************************************************************************
- * Included files
- **********************************************************************************************************************/
-#include "fsl_common.h"
-#include "tzm_config.h"
-
-/***********************************************************************************************************************
- * Definitions
- **********************************************************************************************************************/
-/* SAU region boundaries */
-#define SAU_REGION_0_BASE 0
-#define SAU_REGION_0_END 0x0FFFFFFFU
-#define SAU_REGION_1_BASE 0x20000000U
-#define SAU_REGION_1_END 0xDFFFFFFFU
-#define SAU_REGION_2_BASE 0x1000FE00U
-#define SAU_REGION_2_END 0x1000FFFFU
-
-
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-functional_group:
-- called_from_default_init: 'true'
-- id_prefix: ''
-- prefix_user_defined: 'true'
-- name: 'BOARD_InitTEE'
-- description: ''
-- ahb:
- - regions: [{memory: PROGRAM_FLASH, security: s_priv, start: '0x00000000', size: '0x00010000'}, {memory: PROGRAM_FLASH, security: ns_user, start: '0x00010000',
- size: '0x00090000'}, {memory: BootROM, security: ns_user, start: '0x00000000', size: '0x00020000'}, {memory: SRAMX, security: ns_user, start: '0x00000000',
- size: '0x00008000'}, {memory: SRAM0, security: s_priv, start: '0x00000000', size: '0x00008000'}, {memory: SRAM0, security: ns_user, start: '0x00008000', size: '0x00008000'},
- {memory: SRAM1, security: ns_user, start: '0x00000000', size: '0x00010000'}, {memory: SRAM2, security: ns_user, start: '0x00000000', size: '0x00010000'}, {memory: SRAM3,
- security: ns_user, start: '0x00000000', size: '0x00010000'}, {memory: SRAM4, security: ns_user, start: '0x00000000', size: '0x00004000'}, {memory: USB_RAM,
- security: ns_user, start: '0x00000000', size: '0x00004000'}]
- - masters: {ns_user: {id: [HASH, MCM33C, MCM33S, PQ, SDIO, SDMA0, SDMA1, USBFSD, USBFSH]}}
- - peripherals: {ns_user: {id: [ADC0, AHB_SECURE_CTRL, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DBGMAILBOX, DMA0, DMA1, FLASH,
- FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, GINT0, GINT1, GPIO, HASHCRYPT, INPUTMUX, MAILBOX, MRT0, OSTIMER, PINT, PLU, PMC,
- POWERQUAD, PRINCE, PUF, RNG, RTC, SCT0, SDIF, SECGPIO, SECPINT, SPI8, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT]}, s_priv: {id: [FLEXCOMM0,
- IOCON, SYSCON]}}
- - interrupts:
- - masking: {Non-masked: {id: [acmp_capt_irq, adc_irq, casper_irq, ctimer0_irq, ctimer1_irq, ctimer2_irq, ctimer3_irq, ctimer4_irq, flexcomm0_irq, flexcomm1_irq,
- flexcomm2_irq, flexcomm3_irq, flexcomm4_irq, flexcomm5_irq, flexcomm6_irq, flexcomm7_irq, global_irq0, global_irq1, lspi_hs_irq, mailbox_irq, mrt_irq, os_event_irq,
- pin_int4, pin_int5, pin_int6, pin_int7, pin_irq0, pin_irq1, pin_irq2, pin_irq3, plu_irq, pq_irq, qddkey_irq, rtc_irq, sct_irq, sdio_irq, sdma0_irq, sdma1_irq,
- sec_hypervisor_call_irq, sec_int0, sec_int1, sec_vio_irq, sha_irq, sys_irq, usb0_irq, usb0_needclk_irq, usb1_irq, usb1_needclk_irq, usb1_utmi_irq, utick_irq]}}
- - security: {Secure: {id: [acmp_capt_irq, adc_irq, casper_irq, ctimer0_irq, ctimer1_irq, ctimer2_irq, ctimer3_irq, ctimer4_irq, flexcomm0_irq, flexcomm1_irq,
- flexcomm2_irq, flexcomm3_irq, flexcomm4_irq, flexcomm5_irq, flexcomm6_irq, flexcomm7_irq, global_irq0, global_irq1, lspi_hs_irq, mailbox_irq, mrt_irq, os_event_irq,
- pin_int4, pin_int5, pin_int6, pin_int7, pin_irq0, pin_irq1, pin_irq2, pin_irq3, plu_irq, pq_irq, qddkey_irq, rtc_irq, sct_irq, sdio_irq, sdma0_irq, sdma1_irq,
- sec_hypervisor_call_irq, sec_int0, sec_int1, sec_vio_irq, sha_irq, sys_irq, usb0_irq, usb0_needclk_irq, usb1_irq, usb1_needclk_irq, usb1_utmi_irq, utick_irq]}}
- - pins_masks:
- - pio0: {Non-masked: {id: ['0', '1', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '2', '20', '21', '22', '23', '24', '25', '26', '27', '28',
- '3', '31', '4', '5', '6', '7', '8', '9']}, Masked: {id: ['29', '30']}}
- - pio1: {Non-masked: {id: ['0', '1', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '2', '20', '21', '22', '23', '24', '25', '26', '27', '28',
- '29', '3', '30', '31', '4', '5', '6', '7', '8', '9']}}
-- sau:
- - enabled: 'true'
- - all_non_secure: 'false'
- - generate_code_for_disabled_regions: 'false'
- - regions: [{index: '0', enabled: 'true', security: ns, start: '0x00000000', size: '0x10000000'}, {index: '1', enabled: 'true', security: ns, start: '0x20000000',
- size: '0xC0000000'}, {index: '2', enabled: 'true', security: nsc, start: '0x1000FE00', size: '0x00000200'}, {index: '3', enabled: 'false', security: ns, start: '0x00000000',
- size: '0x00000020'}, {index: '4', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}, {index: '5', enabled: 'false', security: ns, start: '0x00000000',
- size: '0x00000020'}, {index: '6', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}, {index: '7', enabled: 'false', security: ns, start: '0x00000000',
- size: '0x00000020'}]
-- global_options:
- - no:
- - id: [AIRCR_PRIS, AIRCR_BFHFNMINS, AIRCR_SYSRESETREQS, SCR_SLEEPDEEPS, SHCSR_SECUREFAULTENA, NSACR_CP2, NSACR_CP3, NSACR_CP4, NSACR_CP5, NSACR_CP6, NSACR_CP7,
- CPPWR_SU0, CPPWR_SUS0, CPPWR_SU1, CPPWR_SUS1, CPPWR_SU2, CPPWR_SUS2, CPPWR_SU3, CPPWR_SUS3, CPPWR_SU4, CPPWR_SUS4, CPPWR_SU5, CPPWR_SUS5, CPPWR_SU6, CPPWR_SUS6,
- CPPWR_SU7, CPPWR_SUS7, CPPWR_SU10, CPPWR_SUS10, CPPWR_SU11, CPPWR_SUS11, SEC_GPIO_MASK0_LOCK, SEC_GPIO_MASK1_LOCK, SEC_CPU1_INT_MASK0_LOCK, SEC_CPU1_INT_MASK1_LOCK,
- MASTER_SEC_LEVEL_LOCK, CPU0_LOCK_NS_VTOR, CPU0_LOCK_NS_MPU, CPU0_LOCK_S_VTAIRCR, CPU0_LOCK_S_MPU, CPU0_LOCK_SAU, CPU0_LOCK_REG_LOCK, CPU1_LOCK_NS_VTOR, CPU1_LOCK_NS_MPU,
- CPU1_LOCK_REG_LOCK, AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK, AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK, AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT, AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE,
- AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE, AHB_MISC_CTRL_REG_IDAU_ALL_NS]
- - yes:
- - id: [NSACR_CP0, NSACR_CP1, NSACR_CP10, NSACR_CP11, AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING, AHB_MISC_CTRL_REG_WRITE_LOCK, _legacy_source_names_]
- - c_code:
- - id: [_output_type_]
-- user_memory_regions: [{id: Region_1, security: s_priv, name: Secure Code, start: '0x10000000', size: '0x0000FE00'}, {id: Region_2, security: nsc_priv, name: Veneer
- Table, start: '0x1000FE00', size: '0x00000200'}, {id: Region_3, security: s_priv, name: Secure Stack and Data, start: '0x30000000', size: '0x00008000'}, {id: Region_4,
- security: ns_user, name: Non-secure Code, description: Privilege check is disabled so reset value (NS-User) can be used, start: '0x00010000', size: '0x00068000'},
- {id: Region_5, security: ns_user, name: Non-secure Stack and Data, description: 'Privilege check is disabled so reset value (NS-User) can be used. ', start: '0x20008000',
- size: '0x0002B000'}]
-- mpus:
- - mpu:
- - enabled: 'false'
- - id: 's'
- - priv_default_map: 'false'
- - handler_enabled: 'false'
- - generate_code_for_disabled_regions: 'false'
- - attributes: [{index: '0', id: '0', memory_type: device, device: nGnRE}, {index: '1', id: '1', memory_type: device, device: nGnRE}, {index: '2', id: '2', memory_type: device,
- device: nGnRE}, {index: '3', id: '3', memory_type: device, device: nGnRE}, {index: '4', id: '4', memory_type: device, device: nGnRE}, {index: '5', id: '5',
- memory_type: device, device: nGnRE}, {index: '6', id: '6', memory_type: device, device: nGnRE}, {index: '7', id: '7', memory_type: device, device: nGnRE}]
- - regions: [{executable: 'false', read_only: 'false', attributes_index: '0', index: '0', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'},
- {executable: 'false', read_only: 'false', attributes_index: '0', index: '1', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false',
- read_only: 'false', attributes_index: '0', index: '2', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false',
- attributes_index: '0', index: '3', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0',
- index: '4', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '5',
- enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '6', enabled: 'false',
- security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '7', enabled: 'false', security: priv,
- start: '0x00000000', size: '0x00000020'}]
- - mpu:
- - enabled: 'false'
- - id: 'ns'
- - priv_default_map: 'false'
- - handler_enabled: 'false'
- - generate_code_for_disabled_regions: 'false'
- - attributes: [{index: '0', id: '0', memory_type: device, device: nGnRE}, {index: '1', id: '1', memory_type: device, device: nGnRE}, {index: '2', id: '2', memory_type: device,
- device: nGnRE}, {index: '3', id: '3', memory_type: device, device: nGnRE}, {index: '4', id: '4', memory_type: device, device: nGnRE}, {index: '5', id: '5',
- memory_type: device, device: nGnRE}, {index: '6', id: '6', memory_type: device, device: nGnRE}, {index: '7', id: '7', memory_type: device, device: nGnRE}]
- - regions: [{executable: 'false', read_only: 'false', attributes_index: '0', index: '0', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'},
- {executable: 'false', read_only: 'false', attributes_index: '0', index: '1', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false',
- read_only: 'false', attributes_index: '0', index: '2', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false',
- attributes_index: '0', index: '3', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0',
- index: '4', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '5',
- enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '6', enabled: 'false',
- security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '7', enabled: 'false', security: priv,
- start: '0x00000000', size: '0x00000020'}]
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/***********************************************************************************************************************
- * BOARD_InitTrustZone function
- **********************************************************************************************************************/
-void BOARD_InitTrustZone()
-{
- /* SAU configuration */
-
- /* Set SAU Control register: Disable SAU and All Secure */
- SAU->CTRL = 0;
-
- /* Set SAU region number */
- SAU->RNR = 0;
- /* Region base address */
- SAU->RBAR = SAU_REGION_0_BASE & SAU_RBAR_BADDR_Msk;
- /* Region end address */
- SAU->RLAR = (SAU_REGION_0_END & SAU_RLAR_LADDR_Msk)
- | ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk)
- | ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
-
- /* Set SAU region number */
- SAU->RNR = 1;
- /* Region base address */
- SAU->RBAR = SAU_REGION_1_BASE & SAU_RBAR_BADDR_Msk;
- /* Region end address */
- SAU->RLAR = (SAU_REGION_1_END & SAU_RLAR_LADDR_Msk)
- | ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk)
- | ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
-
- /* Set SAU region number */
- SAU->RNR = 2;
- /* Region base address */
- SAU->RBAR = SAU_REGION_2_BASE & SAU_RBAR_BADDR_Msk;
- /* Region end address */
- SAU->RLAR = (SAU_REGION_2_END & SAU_RLAR_LADDR_Msk)
- | ((1U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk)
- | ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
-
- /* Force memory writes before continuing */
- __DSB();
- /* Flush and refill pipeline with updated permissions */
- __ISB();
-
- /* Set SAU Control register: Enable SAU and All Secure (applied only if disabled) */
- SAU->CTRL = ((0U << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk)
- | ((1U << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk);
-
- /* AHB configuration */
-
- /*--------------------------------------------------------------------
- - AHB Security Level Configurations
- -------------------------------------------------------------------*/
- /* Configuration of AHB Secure Controller
- Possible values for every memory sector or peripheral rule:
- 0 Non-secure, User access allowed.
- 1 Non-secure, Privileged access allowed.
- 2 Secure, User access allowed.
- 3 Secure, Privileged access allowed.
- */
-
- /* Security level configuration of MPC checker */
- AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] = 0x00000033U;
- AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[0] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[1] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[2] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[3] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_RAMX[0].MEM_RULE[0] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0] = 0x33333333U;
- AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0] = 0;
- AHB_SECURE_CTRL->SEC_CTRL_USB_HS[0].MEM_RULE[0] = 0;
-
- /* Security level configuration of PPC checker */
- AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 = 0xFCCCCCFFU;
- AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 = 0xFCCCFFCCU;
- AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 = 0xFFFFCFFFU;
- AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 = 0xFFFFCFFCU;
- AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 = 0xFFCCFCCCU;
- AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 = 0xFFCCFFFFU;
- AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 = 0xFFCFCCFCU;
- AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT8_SLAVE0_RULE = 0xCFCCFCFFU;
- AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT8_SLAVE1_RULE = 0xFFFCCCCCU;
- AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT9_SLAVE0_RULE = 0xCCCCFFFFU;
- AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT9_SLAVE1_RULE = 0xCFFCCFFCU;
- AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SLAVE0_RULE = 0xCCCCCCFCU;
- AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SLAVE1_RULE = 0xFFFFFFCCU;
-
- /* Security level configuration of masters */
- AHB_SECURE_CTRL->MASTER_SEC_LEVEL = 0x80000000U;
- AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG = 0xBFFFFFFFU;
-
- /*--------------------------------------------------------------------
- - Pins: Reading GPIO state
- -------------------------------------------------------------------*/
- /* Possible values for every pin:
- * 0b0 Deny
- * 0b1 Allow */
- AHB_SECURE_CTRL->SEC_GPIO_MASK0 = 0x9FFFFFFFU;
- AHB_SECURE_CTRL->SEC_GPIO_MASK1 = 0xFFFFFFFFU;
-
- /*--------------------------------------------------------------------
- - Interrupts: Interrupt handling by Core1
- -------------------------------------------------------------------*/
- /* Possible values for every interrupt:
- * 0b0 Deny
- * 0b1 Allow */
- AHB_SECURE_CTRL->SEC_CPU_INT_MASK0 = 0xFFFFFFFFU;
- AHB_SECURE_CTRL->SEC_CPU_INT_MASK1 = 0xFFFFFFFFU;
-
- /*--------------------------------------------------------------------
- - Interrupts: Interrupt security configuration
- -------------------------------------------------------------------*/
- /* Possible values for every interrupt:
- * 0b0 Secure
- * 0b1 Non-secure */
- NVIC->ITNS[0] = 0;
- NVIC->ITNS[1] = 0;
-
- /* Global Options */
- SCB->AIRCR = (SCB->AIRCR & 0x000009FF7U) | 0x005FA0000U;
- SCB->SCR &= 0x0FFFFFFF7U;
- SCB->SHCSR &= 0x0FFF7FFFFU;
- SCB->NSACR = 0x00000C03U;
- SCnSCB->CPPWR = 0;
- AHB_SECURE_CTRL->SEC_MASK_LOCK = 0x00000AAAU;
- AHB_SECURE_CTRL->MASTER_SEC_LEVEL = (AHB_SECURE_CTRL->MASTER_SEC_LEVEL & 0x03FFFFFFFU) | 0x080000000U;
- AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG = (AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG & 0x03FFFFFFFU) | 0x080000000U;
- AHB_SECURE_CTRL->CPU0_LOCK_REG = 0x800002AAU;
- AHB_SECURE_CTRL->CPU1_LOCK_REG = 0x8000000AU;
- AHB_SECURE_CTRL->MISC_CTRL_REG = (AHB_SECURE_CTRL->MISC_CTRL_REG & 0x0FFFF0003U) | 0x00000AAA4U;
- AHB_SECURE_CTRL->MISC_CTRL_DP_REG = 0x0000AAA5U;
-}
+/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: TEE v3.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 0.10.1 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "tzm_config.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* SAU region boundaries */ +#define SAU_REGION_0_BASE 0 +#define SAU_REGION_0_END 0x0FFFFFFFU +#define SAU_REGION_1_BASE 0x20000000U +#define SAU_REGION_1_END 0xDFFFFFFFU +#define SAU_REGION_2_BASE 0x1000FE00U +#define SAU_REGION_2_END 0x1000FFFFU + + + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +functional_group: +- called_from_default_init: 'true' +- id_prefix: '' +- prefix_user_defined: 'true' +- name: 'BOARD_InitTEE' +- description: '' +- ahb: + - regions: [{memory: PROGRAM_FLASH, security: s_priv, start: '0x00000000', size: '0x00010000'}, {memory: PROGRAM_FLASH, security: ns_user, start: '0x00010000', + size: '0x00090000'}, {memory: BootROM, security: ns_user, start: '0x00000000', size: '0x00020000'}, {memory: SRAMX, security: ns_user, start: '0x00000000', + size: '0x00008000'}, {memory: SRAM0, security: s_priv, start: '0x00000000', size: '0x00008000'}, {memory: SRAM0, security: ns_user, start: '0x00008000', size: '0x00008000'}, + {memory: SRAM1, security: ns_user, start: '0x00000000', size: '0x00010000'}, {memory: SRAM2, security: ns_user, start: '0x00000000', size: '0x00010000'}, {memory: SRAM3, + security: ns_user, start: '0x00000000', size: '0x00010000'}, {memory: SRAM4, security: ns_user, start: '0x00000000', size: '0x00004000'}, {memory: USB_RAM, + security: ns_user, start: '0x00000000', size: '0x00004000'}] + - masters: {ns_user: {id: [HASH, MCM33C, MCM33S, PQ, SDIO, SDMA0, SDMA1, USBFSD, USBFSH]}} + - peripherals: {ns_user: {id: [ADC0, AHB_SECURE_CTRL, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DBGMAILBOX, DMA0, DMA1, FLASH, + FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, GINT0, GINT1, GPIO, HASHCRYPT, INPUTMUX, MAILBOX, MRT0, OSTIMER, PINT, PLU, PMC, + POWERQUAD, PRINCE, PUF, RNG, RTC, SCT0, SDIF, SECGPIO, SECPINT, SPI8, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT]}, s_priv: {id: [FLEXCOMM0, + IOCON, SYSCON]}} + - interrupts: + - masking: {Non-masked: {id: [acmp_capt_irq, adc_irq, casper_irq, ctimer0_irq, ctimer1_irq, ctimer2_irq, ctimer3_irq, ctimer4_irq, flexcomm0_irq, flexcomm1_irq, + flexcomm2_irq, flexcomm3_irq, flexcomm4_irq, flexcomm5_irq, flexcomm6_irq, flexcomm7_irq, global_irq0, global_irq1, lspi_hs_irq, mailbox_irq, mrt_irq, os_event_irq, + pin_int4, pin_int5, pin_int6, pin_int7, pin_irq0, pin_irq1, pin_irq2, pin_irq3, plu_irq, pq_irq, qddkey_irq, rtc_irq, sct_irq, sdio_irq, sdma0_irq, sdma1_irq, + sec_hypervisor_call_irq, sec_int0, sec_int1, sec_vio_irq, sha_irq, sys_irq, usb0_irq, usb0_needclk_irq, usb1_irq, usb1_needclk_irq, usb1_utmi_irq, utick_irq]}} + - security: {Secure: {id: [acmp_capt_irq, adc_irq, casper_irq, ctimer0_irq, ctimer1_irq, ctimer2_irq, ctimer3_irq, ctimer4_irq, flexcomm0_irq, flexcomm1_irq, + flexcomm2_irq, flexcomm3_irq, flexcomm4_irq, flexcomm5_irq, flexcomm6_irq, flexcomm7_irq, global_irq0, global_irq1, lspi_hs_irq, mailbox_irq, mrt_irq, os_event_irq, + pin_int4, pin_int5, pin_int6, pin_int7, pin_irq0, pin_irq1, pin_irq2, pin_irq3, plu_irq, pq_irq, qddkey_irq, rtc_irq, sct_irq, sdio_irq, sdma0_irq, sdma1_irq, + sec_hypervisor_call_irq, sec_int0, sec_int1, sec_vio_irq, sha_irq, sys_irq, usb0_irq, usb0_needclk_irq, usb1_irq, usb1_needclk_irq, usb1_utmi_irq, utick_irq]}} + - pins_masks: + - pio0: {Non-masked: {id: ['0', '1', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '2', '20', '21', '22', '23', '24', '25', '26', '27', '28', + '3', '31', '4', '5', '6', '7', '8', '9']}, Masked: {id: ['29', '30']}} + - pio1: {Non-masked: {id: ['0', '1', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '2', '20', '21', '22', '23', '24', '25', '26', '27', '28', + '29', '3', '30', '31', '4', '5', '6', '7', '8', '9']}} +- sau: + - enabled: 'true' + - all_non_secure: 'false' + - generate_code_for_disabled_regions: 'false' + - regions: [{index: '0', enabled: 'true', security: ns, start: '0x00000000', size: '0x10000000'}, {index: '1', enabled: 'true', security: ns, start: '0x20000000', + size: '0xC0000000'}, {index: '2', enabled: 'true', security: nsc, start: '0x1000FE00', size: '0x00000200'}, {index: '3', enabled: 'false', security: ns, start: '0x00000000', + size: '0x00000020'}, {index: '4', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}, {index: '5', enabled: 'false', security: ns, start: '0x00000000', + size: '0x00000020'}, {index: '6', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}, {index: '7', enabled: 'false', security: ns, start: '0x00000000', + size: '0x00000020'}] +- global_options: + - no: + - id: [AIRCR_PRIS, AIRCR_BFHFNMINS, AIRCR_SYSRESETREQS, SCR_SLEEPDEEPS, SHCSR_SECUREFAULTENA, NSACR_CP2, NSACR_CP3, NSACR_CP4, NSACR_CP5, NSACR_CP6, NSACR_CP7, + CPPWR_SU0, CPPWR_SUS0, CPPWR_SU1, CPPWR_SUS1, CPPWR_SU2, CPPWR_SUS2, CPPWR_SU3, CPPWR_SUS3, CPPWR_SU4, CPPWR_SUS4, CPPWR_SU5, CPPWR_SUS5, CPPWR_SU6, CPPWR_SUS6, + CPPWR_SU7, CPPWR_SUS7, CPPWR_SU10, CPPWR_SUS10, CPPWR_SU11, CPPWR_SUS11, SEC_GPIO_MASK0_LOCK, SEC_GPIO_MASK1_LOCK, SEC_CPU1_INT_MASK0_LOCK, SEC_CPU1_INT_MASK1_LOCK, + MASTER_SEC_LEVEL_LOCK, CPU0_LOCK_NS_VTOR, CPU0_LOCK_NS_MPU, CPU0_LOCK_S_VTAIRCR, CPU0_LOCK_S_MPU, CPU0_LOCK_SAU, CPU0_LOCK_REG_LOCK, CPU1_LOCK_NS_VTOR, CPU1_LOCK_NS_MPU, + CPU1_LOCK_REG_LOCK, AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK, AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK, AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT, AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE, + AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE, AHB_MISC_CTRL_REG_IDAU_ALL_NS] + - yes: + - id: [NSACR_CP0, NSACR_CP1, NSACR_CP10, NSACR_CP11, AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING, AHB_MISC_CTRL_REG_WRITE_LOCK, _legacy_source_names_] + - c_code: + - id: [_output_type_] +- user_memory_regions: [{id: Region_1, security: s_priv, name: Secure Code, start: '0x10000000', size: '0x0000FE00'}, {id: Region_2, security: nsc_priv, name: Veneer + Table, start: '0x1000FE00', size: '0x00000200'}, {id: Region_3, security: s_priv, name: Secure Stack and Data, start: '0x30000000', size: '0x00008000'}, {id: Region_4, + security: ns_user, name: Non-secure Code, description: Privilege check is disabled so reset value (NS-User) can be used, start: '0x00010000', size: '0x00068000'}, + {id: Region_5, security: ns_user, name: Non-secure Stack and Data, description: 'Privilege check is disabled so reset value (NS-User) can be used. ', start: '0x20008000', + size: '0x0002B000'}] +- mpus: + - mpu: + - enabled: 'false' + - id: 's' + - priv_default_map: 'false' + - handler_enabled: 'false' + - generate_code_for_disabled_regions: 'false' + - attributes: [{index: '0', id: '0', memory_type: device, device: nGnRE}, {index: '1', id: '1', memory_type: device, device: nGnRE}, {index: '2', id: '2', memory_type: device, + device: nGnRE}, {index: '3', id: '3', memory_type: device, device: nGnRE}, {index: '4', id: '4', memory_type: device, device: nGnRE}, {index: '5', id: '5', + memory_type: device, device: nGnRE}, {index: '6', id: '6', memory_type: device, device: nGnRE}, {index: '7', id: '7', memory_type: device, device: nGnRE}] + - regions: [{executable: 'false', read_only: 'false', attributes_index: '0', index: '0', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, + {executable: 'false', read_only: 'false', attributes_index: '0', index: '1', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', + read_only: 'false', attributes_index: '0', index: '2', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', + attributes_index: '0', index: '3', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', + index: '4', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '5', + enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '6', enabled: 'false', + security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '7', enabled: 'false', security: priv, + start: '0x00000000', size: '0x00000020'}] + - mpu: + - enabled: 'false' + - id: 'ns' + - priv_default_map: 'false' + - handler_enabled: 'false' + - generate_code_for_disabled_regions: 'false' + - attributes: [{index: '0', id: '0', memory_type: device, device: nGnRE}, {index: '1', id: '1', memory_type: device, device: nGnRE}, {index: '2', id: '2', memory_type: device, + device: nGnRE}, {index: '3', id: '3', memory_type: device, device: nGnRE}, {index: '4', id: '4', memory_type: device, device: nGnRE}, {index: '5', id: '5', + memory_type: device, device: nGnRE}, {index: '6', id: '6', memory_type: device, device: nGnRE}, {index: '7', id: '7', memory_type: device, device: nGnRE}] + - regions: [{executable: 'false', read_only: 'false', attributes_index: '0', index: '0', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, + {executable: 'false', read_only: 'false', attributes_index: '0', index: '1', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', + read_only: 'false', attributes_index: '0', index: '2', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', + attributes_index: '0', index: '3', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', + index: '4', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '5', + enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '6', enabled: 'false', + security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '7', enabled: 'false', security: priv, + start: '0x00000000', size: '0x00000020'}] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * BOARD_InitTrustZone function + **********************************************************************************************************************/ +void BOARD_InitTrustZone() +{ + /* SAU configuration */ + + /* Set SAU Control register: Disable SAU and All Secure */ + SAU->CTRL = 0; + + /* Set SAU region number */ + SAU->RNR = 0; + /* Region base address */ + SAU->RBAR = SAU_REGION_0_BASE & SAU_RBAR_BADDR_Msk; + /* Region end address */ + SAU->RLAR = (SAU_REGION_0_END & SAU_RLAR_LADDR_Msk) + | ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) + | ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk); + + /* Set SAU region number */ + SAU->RNR = 1; + /* Region base address */ + SAU->RBAR = SAU_REGION_1_BASE & SAU_RBAR_BADDR_Msk; + /* Region end address */ + SAU->RLAR = (SAU_REGION_1_END & SAU_RLAR_LADDR_Msk) + | ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) + | ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk); + + /* Set SAU region number */ + SAU->RNR = 2; + /* Region base address */ + SAU->RBAR = SAU_REGION_2_BASE & SAU_RBAR_BADDR_Msk; + /* Region end address */ + SAU->RLAR = (SAU_REGION_2_END & SAU_RLAR_LADDR_Msk) + | ((1U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) + | ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk); + + /* Force memory writes before continuing */ + __DSB(); + /* Flush and refill pipeline with updated permissions */ + __ISB(); + + /* Set SAU Control register: Enable SAU and All Secure (applied only if disabled) */ + SAU->CTRL = ((0U << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) + | ((1U << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk); + + /* AHB configuration */ + + /*-------------------------------------------------------------------- + - AHB Security Level Configurations + -------------------------------------------------------------------*/ + /* Configuration of AHB Secure Controller + Possible values for every memory sector or peripheral rule: + 0 Non-secure, User access allowed. + 1 Non-secure, Privileged access allowed. + 2 Secure, User access allowed. + 3 Secure, Privileged access allowed. + */ + + /* Security level configuration of MPC checker */ + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] = 0x00000033U; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] = 0; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[2] = 0; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[3] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAMX[0].MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0] = 0x33333333U; + AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_USB_HS[0].MEM_RULE[0] = 0; + + /* Security level configuration of PPC checker */ + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 = 0xFCCCCCFFU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 = 0xFCCCFFCCU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 = 0xFFFFCFFFU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 = 0xFFFFCFFCU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 = 0xFFCCFCCCU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 = 0xFFCCFFFFU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 = 0xFFCFCCFCU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT8_SLAVE0_RULE = 0xCFCCFCFFU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT8_SLAVE1_RULE = 0xFFFCCCCCU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT9_SLAVE0_RULE = 0xCCCCFFFFU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT9_SLAVE1_RULE = 0xCFFCCFFCU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SLAVE0_RULE = 0xCCCCCCFCU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SLAVE1_RULE = 0xFFFFFFCCU; + + /* Security level configuration of masters */ + AHB_SECURE_CTRL->MASTER_SEC_LEVEL = 0x80000000U; + AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG = 0xBFFFFFFFU; + + /*-------------------------------------------------------------------- + - Pins: Reading GPIO state + -------------------------------------------------------------------*/ + /* Possible values for every pin: + * 0b0 Deny + * 0b1 Allow */ + AHB_SECURE_CTRL->SEC_GPIO_MASK0 = 0x9FFFFFFFU; + AHB_SECURE_CTRL->SEC_GPIO_MASK1 = 0xFFFFFFFFU; + + /*-------------------------------------------------------------------- + - Interrupts: Interrupt handling by Core1 + -------------------------------------------------------------------*/ + /* Possible values for every interrupt: + * 0b0 Deny + * 0b1 Allow */ + AHB_SECURE_CTRL->SEC_CPU_INT_MASK0 = 0xFFFFFFFFU; + AHB_SECURE_CTRL->SEC_CPU_INT_MASK1 = 0xFFFFFFFFU; + + /*-------------------------------------------------------------------- + - Interrupts: Interrupt security configuration + -------------------------------------------------------------------*/ + /* Possible values for every interrupt: + * 0b0 Secure + * 0b1 Non-secure */ + NVIC->ITNS[0] = 0; + NVIC->ITNS[1] = 0; + + /* Global Options */ + SCB->AIRCR = (SCB->AIRCR & 0x000009FF7U) | 0x005FA0000U; + SCB->SCR &= 0x0FFFFFFF7U; + SCB->SHCSR &= 0x0FFF7FFFFU; + SCB->NSACR = 0x00000C03U; + SCnSCB->CPPWR = 0; + AHB_SECURE_CTRL->SEC_MASK_LOCK = 0x00000AAAU; + AHB_SECURE_CTRL->MASTER_SEC_LEVEL = (AHB_SECURE_CTRL->MASTER_SEC_LEVEL & 0x03FFFFFFFU) | 0x080000000U; + AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG = (AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG & 0x03FFFFFFFU) | 0x080000000U; + AHB_SECURE_CTRL->CPU0_LOCK_REG = 0x800002AAU; + AHB_SECURE_CTRL->CPU1_LOCK_REG = 0x8000000AU; + AHB_SECURE_CTRL->MISC_CTRL_REG = (AHB_SECURE_CTRL->MISC_CTRL_REG & 0x0FFFF0003U) | 0x00000AAA4U; + AHB_SECURE_CTRL->MISC_CTRL_DP_REG = 0x0000AAA5U; +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.h index 8b48f7799..9cc45d1a0 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.h @@ -1,18 +1,18 @@ -#ifndef _TZM_CONFIG_H_
-#define _TZM_CONFIG_H_
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus */
-
-
-/***********************************************************************************************************************
- * Initialize TrustZone
- **********************************************************************************************************************/
-void BOARD_InitTrustZone(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* _TZM_CONFIG_H_ */
+#ifndef _TZM_CONFIG_H_ +#define _TZM_CONFIG_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +/*********************************************************************************************************************** + * Initialize TrustZone + **********************************************************************************************************************/ +void BOARD_InitTrustZone(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _TZM_CONFIG_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h new file mode 100644 index 000000000..681d846a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h @@ -0,0 +1,169 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/****************************************************************************** + See http://www.freertos.org/a00110.html for an explanation of the + definitions contained in this file. +******************************************************************************/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * https://www.FreeRTOS.org/a00110.html + *----------------------------------------------------------*/ + +#ifndef __IASMARM__ + #include "clock_config.h" +#endif + +/* Cortex M33 port configuration. */ +#define configENABLE_MPU 1 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 1 + +/* Constants related to the behaviour or the scheduler. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 1 +#define configMAX_PRIORITIES ( 5 ) +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */ + +/* Constants that describe the hardware and memory usage. */ +#define configCPU_CLOCK_HZ BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK +#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 ) +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) ) + +/* Constants that build features in or out. */ +#define configUSE_MUTEXES 1 +#define configUSE_TICKLESS_IDLE 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_TRACE_FACILITY 1 + +/* Constants that define which hook (callback) functions should be used. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 + +/* Constants provided for debugging and optimisation assistance. */ +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } +#define configQUEUE_REGISTRY_SIZE 0 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 3 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is + * only necessary if the linker does not automatically remove functions that are + * not referenced anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xSemaphoreGetMutexHolder 0 +#define INCLUDE_xTimerPendFunctionCall 1 + +/* This demo makes use of one or more example stats formatting functions. These + * format the raw data provided by the uxTaskGetSystemState() function in to + * human readable ASCII form. See the notes in the implementation of vTaskList() + * within FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter. + * See the FreeRTOS+CLI documentation for more information: + * https://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048 + +/* Interrupt priority configuration follows...................... */ + +/* Use the system definition, if there is one. */ +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 8 priority levels. */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" + * function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 + +/* The highest interrupt priority that can be used by any interrupt service + * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT + * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A + * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic + * to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) + +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) + +/* The #ifdef guards against the file being included from IAR assembly files. */ +#ifndef __IASMARM__ + + /* Constants related to the generation of run time stats. */ + #define configGENERATE_RUN_TIME_STATS 0 + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() + #define portGET_RUN_TIME_COUNTER_VALUE() 0 + #define configTICK_RATE_HZ ( ( TickType_t ) 100 ) + +#endif /* __IASMARM__ */ + +/* Enable static allocation. */ +#define configSUPPORT_STATIC_ALLOCATION 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/FreeRTOSDemo.eww b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/FreeRTOSDemo.eww new file mode 100644 index 000000000..f1093c989 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/FreeRTOSDemo.eww @@ -0,0 +1,22 @@ +<?xml version="1.0" encoding="iso-8859-1"?> +<workspace> + <batchBuild> + <batchDefinition> + <name>all</name> + <member> + <project>FreeRTOSDemo_s</project> + <configuration>debug</configuration> + </member> + <member> + <project>FreeRTOSDemo_ns</project> + <configuration>debug</configuration> + </member> + </batchDefinition> + </batchBuild> + <project> + <path>$WS_DIR$/Secure/FreeRTOSDemo_s.ewp</path> + </project> + <project> + <path>$WS_DIR$/NonSecure/FreeRTOSDemo_ns.ewp</path> + </project> +</workspace> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_flash_ns.icf b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_flash_ns.icf new file mode 100644 index 000000000..5345cea5c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_flash_ns.icf @@ -0,0 +1,144 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_privileged_text_start = 0x00010000; +define symbol m_privileged_text_end = 0x00017FFF; + +define symbol m_syscalls_text_start = 0x00018000; +define symbol m_syscalls_text_end = 0x0001FFFF; + +define symbol m_unprivileged_text_start = 0x00020000; +define symbol m_unprivileged_text_end = 0x00071FFF; + +define exported symbol core1_image_start = 0x00072000; +define exported symbol core1_image_end = 0x0009D7FF; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_privileged_data_start = 0x20008000; + define symbol m_privileged_data_end = 0x20017FFF; + + define symbol m_unprivileged_data_start = 0x20018000; + define symbol m_unprivileged_data_end = 0x20030FFF; + + define exported symbol rpmsg_sh_mem_start = 0x20031800; + define exported symbol rpmsg_sh_mem_end = 0x20032FFF; +} else { + define symbol m_privileged_data_start = 0x20008000; + define symbol m_privileged_data_end = 0x20017FFF; + + define symbol m_unprivileged_data_start = 0x20018000; + define symbol m_unprivileged_data_end = 0x20032FFF; +} + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40103FFF; + +define memory mem with size = 4G; + +define region TEXT_privileged_region = mem:[from m_privileged_text_start to m_privileged_text_end]; +define region TEXT_syscalls_region = mem:[from m_syscalls_text_start to m_syscalls_text_end]; +define region TEXT_unprivileged_region = mem:[from m_unprivileged_text_start to m_unprivileged_text_end]; + + +define region DATA_privileged_region = mem:[from m_privileged_data_start to m_privileged_data_end]; +define region DATA_unprivileged_region = mem:[from m_unprivileged_data_start to m_unprivileged_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_unprivileged_data_end-__size_cstack__+1 to m_unprivileged_data_end]; + +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block CORE1_IMAGE_WBLOCK { section __core1_image }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +/* Exported symbols. */ +define exported symbol __privileged_functions_start__ = m_privileged_text_start; +define exported symbol __privileged_functions_end__ = m_privileged_text_end; +define exported symbol __syscalls_flash_start__ = m_syscalls_text_start; +define exported symbol __syscalls_flash_end__ = m_syscalls_text_end; +define exported symbol __unprivileged_flash_start__ = m_unprivileged_text_start; +define exported symbol __unprivileged_flash_end__ = m_unprivileged_text_end; +define exported symbol __privileged_sram_start__ = m_privileged_data_start; +define exported symbol __privileged_sram_end__ = m_privileged_data_end; + +/* Placements. */ +place at address mem: m_privileged_text_start { readonly section .intvec }; + +place in TEXT_privileged_region { readonly section privileged_functions }; +place in TEXT_syscalls_region { readonly section freertos_system_calls }; +place in TEXT_unprivileged_region { readonly }; + +place in DATA_privileged_region { readwrite section privileged_data }; +place in DATA_unprivileged_region { block RW }; +place in DATA_unprivileged_region { block ZI }; +place in DATA_unprivileged_region { last block HEAP }; + +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block CORE1_IMAGE_WBLOCK }; + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd new file mode 100644 index 000000000..5f2320290 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd @@ -0,0 +1,12342 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<project> + + <fileVersion>3</fileVersion> + + <configuration> + + <name>debug</name> + + <toolchain> + + <name>ARM</name> + + </toolchain> + + <debug>1</debug> + + <settings> + + <name>C-SPY</name> + + <archiveVersion>2</archiveVersion> + + <data> + + <version>32</version> + + <wantNonLocal>1</wantNonLocal> + + <debug>1</debug> + + <option> + + <name>CInput</name> + + <state>1</state> + + </option> + + <option> + + <name>CEndian</name> + + <state>1</state> + + </option> + + <option> + + <name>CProcessor</name> + + <state>1</state> + + </option> + + <option> + + <name>OCVariant</name> + + <state>0</state> + + </option> + + <option> + + <name>MacOverride</name> + + <state>0</state> + + </option> + + <option> + + <name>MacFile</name> + + <state/> + + </option> + + <option> + + <name>MemOverride</name> + + <state>0</state> + + </option> + + <option> + + <name>MemFile</name> + + <state>$TOOLKIT_DIR$\config\devices\NXP\LPC\LPC5500\LPC55S69J_M33_CORE0.svd</state> + + </option> + + <option> + + <name>RunToEnable</name> + + <state>1</state> + + </option> + + <option> + + <name>RunToName</name> + + <state>main</state> + + </option> + + <option> + + <name>CExtraOptionsCheck</name> + + <state>0</state> + + </option> + + <option> + + <name>CExtraOptions</name> + + <state/> + + </option> + + <option> + + <name>CFpuProcessor</name> + + <state>1</state> + + </option> + + <option> + + <name>OCDDFArgumentProducer</name> + + <state/> + + </option> + + <option> + + <name>OCDownloadSuppressDownload</name> + + <state>0</state> + + </option> + + <option> + + <name>OCDownloadVerifyAll</name> + + <state>1</state> + + </option> + + <option> + + <name>OCProductVersion</name> + + <state>6.50.6.4952</state> + + </option> + + <option> + + <name>OCDynDriverList</name> + + <state>CMSISDAP_ID</state> + + </option> + + <option> + + <name>OCLastSavedByProductVersion</name> + + <state>8.30.2.18207</state> + + </option> + + <option> + + <name>UseFlashLoader</name> + + <state>1</state> + + </option> + + <option> + + <name>CLowLevel</name> + + <state>1</state> + + </option> + + <option> + + <name>OCBE8Slave</name> + + <state>1</state> + + </option> + + <option> + + <name>MacFile2</name> + + <state/> + + </option> + + <option> + + <name>CDevice</name> + + <state>1</state> + + </option> + + <option> + + <name>FlashLoadersV3</name> + + <state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashNXPLPC55xx.board</state> + + </option> + + <option> + + <name>OCImagesSuppressCheck1</name> + + <state>0</state> + + </option> + + <option> + + <name>OCImagesPath1</name> + + <state/> + + </option> + + <option> + + <name>OCImagesSuppressCheck2</name> + + <state>0</state> + + </option> + + <option> + + <name>OCImagesPath2</name> + + <state/> + + </option> + + <option> + + <name>OCImagesSuppressCheck3</name> + + <state>0</state> + + </option> + + <option> + + <name>OCImagesPath3</name> + + <state/> + + </option> + + <option> + + <name>OverrideDefFlashBoard</name> + + <state>0</state> + + </option> + + <option> + + <name>OCImagesOffset1</name> + + <state/> + + </option> + + <option> + + <name>OCImagesOffset2</name> + + <state/> + + </option> + + <option> + + <name>OCImagesOffset3</name> + + <state/> + + </option> + + <option> + + <name>OCImagesUse1</name> + + <state>0</state> + + </option> + + <option> + + <name>OCImagesUse2</name> + + <state>0</state> + + </option> + + <option> + + <name>OCImagesUse3</name> + + <state>0</state> + + </option> + + <option> + + <name>OCDeviceConfigMacroFile</name> + + <state>1</state> + + </option> + + <option> + + <name>OCDebuggerExtraOption</name> + + <state>1</state> + + </option> + + <option> + + <name>OCAllMTBOptions</name> + + <state>1</state> + + </option> + + <option> + + <name>OCMulticoreNrOfCores</name> + + <state>1</state> + + </option> + + <option> + + <name>OCMulticoreWorkspace</name> + + <state>$PROJ_DIR$/../FreeRTOSDemo.eww</state> + + </option> + + <option> + + <name>OCMulticoreSlaveProject</name> + + <state>FreeRTOSDemo_s</state> + + </option> + + <option> + + <name>OCMulticoreSlaveConfiguration</name> + + <state/> + + </option> + + <option> + + <name>OCDownloadExtraImage</name> + + <state>1</state> + + </option> + + <option> + + <name>OCAttachSlave</name> + + <state>1</state> + + </option> + + <option> + + <name>MassEraseBeforeFlashing</name> + + <state>0</state> + + </option> + + <option> + + <name>OCMulticoreNrOfCoresSlave</name> + + <state>1</state> + + </option> + + <option> + + <name>OCMulticoreAMPConfigType</name> + + <state>0</state> + + </option> + + <option> + + <name>OCMulticoreSessionFile</name> + + <state/> + + </option> + + <option> + + <name>OCTpiuBaseOption</name> + + <state>1</state> + + </option> + + </data> + + </settings> + + <settings> + + <name>ARMSIM_ID</name> + + <archiveVersion>2</archiveVersion> + + <data> + + <version>1</version> + + <wantNonLocal>1</wantNonLocal> + + <debug>1</debug> + + <option> + + <name>OCSimDriverInfo</name> + + <state>1</state> + + </option> + + <option> + + <name>OCSimEnablePSP</name> + + <state>0</state> + + </option> + + <option> + + <name>OCSimPspOverrideConfig</name> + + <state>0</state> + + </option> + + <option> + + <name>OCSimPspConfigFile</name> + + <state/> + + </option> + + </data> + + </settings> + + <settings> + + <name>CADI_ID</name> + + <archiveVersion>2</archiveVersion> + + <data> + + <version>0</version> + + <wantNonLocal>1</wantNonLocal> + + <debug>1</debug> + + <option> + + <name>CCadiMemory</name> + + <state>1</state> + + </option> + + <option> + + <name>Fast Model</name> + + <state/> + + </option> + + <option> + + <name>CCADILogFileCheck</name> + + <state>0</state> + + </option> + + <option> + + <name>CCADILogFileEditB</name> + + <state>$PROJ_DIR$\cspycomm.log</state> + + </option> + + <option> + + <name>OCDriverInfo</name> + + <state>1</state> + + </option> + + </data> + + </settings> + + <settings> + + <name>CMSISDAP_ID</name> + + <archiveVersion>2</archiveVersion> + + <data> + + <version>4</version> + + <wantNonLocal>1</wantNonLocal> + + <debug>1</debug> + + <option> + + <name>CatchSFERR</name> + + <state>1</state> + + </option> + + <option> + + <name>OCDriverInfo</name> + + <state>1</state> + + </option> + + <option> + + <name>OCIarProbeScriptFile</name> + + <state>1</state> + + </option> + + <option> + + <name>CMSISDAPResetList</name> + + <version>1</version> + + <state>4</state> + + </option> + + <option> + + <name>CMSISDAPHWResetDuration</name> + + <state>300</state> + + </option> + + <option> + + <name>CMSISDAPHWResetDelay</name> + + <state>200</state> + + </option> + + <option> + + <name>CMSISDAPDoLogfile</name> + + <state>0</state> + + </option> + + <option> + + <name>CMSISDAPLogFile</name> + + <state>$PROJ_DIR$\cspycomm.log</state> + + </option> + + <option> + + <name>CMSISDAPInterfaceRadio</name> + + <state>1</state> + + </option> + + <option> + + <name>CMSISDAPInterfaceCmdLine</name> + + <state>0</state> + + </option> + + <option> + + <name>CMSISDAPMultiTargetEnable</name> + + <state>0</state> + + </option> + + <option> + + <name>CMSISDAPMultiTarget</name> + + <state>0</state> + + </option> + + <option> + + <name>CMSISDAPJtagSpeedList</name> + + <version>0</version> + + <state>0</state> + + </option> + + <option> + + <name>CMSISDAPBreakpointRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>CMSISDAPRestoreBreakpointsCheck</name> + + <state>0</state> + + </option> + + <option> + + <name>CMSISDAPUpdateBreakpointsEdit</name> + + <state>_call_main</state> + + </option> + + <option> + + <name>RDICatchReset</name> + + <state>0</state> + + </option> + + <option> + + <name>RDICatchUndef</name> + + <state>0</state> + + </option> + + <option> + + <name>RDICatchSWI</name> + + <state>0</state> + + </option> + + <option> + + <name>RDICatchData</name> + + <state>0</state> + + </option> + + <option> + + <name>RDICatchPrefetch</name> + + <state>0</state> + + </option> + + <option> + + <name>RDICatchIRQ</name> + + <state>0</state> + + </option> + + <option> + + <name>RDICatchFIQ</name> + + <state>0</state> + + </option> + + <option> + + <name>CatchCORERESET</name> + + <state>0</state> + + </option> + + <option> + + <name>CatchMMERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CatchNOCPERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CatchCHKERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CatchSTATERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CatchBUSERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CatchINTERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CatchHARDERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CatchDummy</name> + + <state>0</state> + + </option> + + <option> + + <name>CMSISDAPMultiCPUEnable</name> + + <state>0</state> + + </option> + + <option> + + <name>CMSISDAPMultiCPUNumber</name> + + <state>0</state> + + </option> + + <option> + + <name>OCProbeCfgOverride</name> + + <state>0</state> + + </option> + + <option> + + <name>OCProbeConfig</name> + + <state/> + + </option> + + <option> + + <name>CMSISDAPProbeConfigRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>CMSISDAPSelectedCPUBehaviour</name> + + <state/> + + </option> + + <option> + + <name>ICpuName</name> + + <state/> + + </option> + + <option> + + <name>OCJetEmuParams</name> + + <state>1</state> + + </option> + + <option> + + <name>CCCMSISDAPUsbSerialNo</name> + + <state/> + + </option> + + <option> + + <name>CCCMSISDAPUsbSerialNoSelect</name> + + <state>0</state> + + </option> + + </data> + + </settings> + + <settings> + + <name>GDBSERVER_ID</name> + + <archiveVersion>2</archiveVersion> + + <data> + + <version>0</version> + + <wantNonLocal>1</wantNonLocal> + + <debug>1</debug> + + <option> + + <name>OCDriverInfo</name> + + <state>1</state> + + </option> + + <option> + + <name>TCPIP</name> + + <state>aaa.bbb.ccc.ddd</state> + + </option> + + <option> + + <name>DoLogfile</name> + + <state>0</state> + + </option> + + <option> + + <name>LogFile</name> + + <state>$PROJ_DIR$\cspycomm.log</state> + + </option> + + <option> + + <name>CCJTagBreakpointRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>CCJTagDoUpdateBreakpoints</name> + + <state>0</state> + + </option> + + <option> + + <name>CCJTagUpdateBreakpoints</name> + + <state>_call_main</state> + + </option> + + </data> + + </settings> + + <settings> + + <name>IJET_ID</name> + + <archiveVersion>2</archiveVersion> + + <data> + + <version>9</version> + + <wantNonLocal>1</wantNonLocal> + + <debug>1</debug> + + <option> + + <name>CatchSFERR</name> + + <state>1</state> + + </option> + + <option> + + <name>OCDriverInfo</name> + + <state>1</state> + + </option> + + <option> + + <name>OCIarProbeScriptFile</name> + + <state>1</state> + + </option> + + <option> + + <name>IjetResetList</name> + + <version>1</version> + + <state>10</state> + + </option> + + <option> + + <name>IjetHWResetDuration</name> + + <state>300</state> + + </option> + + <option> + + <name>IjetHWResetDelay</name> + + <state>200</state> + + </option> + + <option> + + <name>IjetPowerFromProbe</name> + + <state>1</state> + + </option> + + <option> + + <name>IjetPowerRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetDoLogfile</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetLogFile</name> + + <state>$PROJ_DIR$\cspycomm.log</state> + + </option> + + <option> + + <name>IjetInterfaceRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetInterfaceCmdLine</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetMultiTargetEnable</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetMultiTarget</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetScanChainNonARMDevices</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetIRLength</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetJtagSpeedList</name> + + <version>0</version> + + <state>0</state> + + </option> + + <option> + + <name>IjetProtocolRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetSwoPin</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetCpuClockEdit</name> + + <state>72.0</state> + + </option> + + <option> + + <name>IjetSwoPrescalerList</name> + + <version>1</version> + + <state>0</state> + + </option> + + <option> + + <name>IjetBreakpointRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetRestoreBreakpointsCheck</name> + + <state>0</state> + + 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<name>CatchSTATERR</name> + + <state>1</state> + + </option> + + <option> + + <name>CatchBUSERR</name> + + <state>1</state> + + </option> + + <option> + + <name>CatchINTERR</name> + + <state>1</state> + + </option> + + <option> + + <name>CatchHARDERR</name> + + <state>1</state> + + </option> + + <option> + + <name>CatchDummy</name> + + <state>0</state> + + </option> + + <option> + + <name>OCProbeCfgOverride</name> + + <state>0</state> + + </option> + + <option> + + <name>OCProbeConfig</name> + + <state/> + + </option> + + <option> + + <name>IjetProbeConfigRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetMultiCPUEnable</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetMultiCPUNumber</name> + + <state>0</state> + + </option> + + <option> + + <name>IjetSelectedCPUBehaviour</name> + + <state>0</state> + + </option> + + <option> + + <name>ICpuName</name> + + <state/> + + </option> + + <option> + + <name>OCJetEmuParams</name> + + <state>1</state> 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<name>CCSTLinkCatchCORERESET</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkCatchMMERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkCatchNOCPERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkCatchCHRERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkCatchSTATERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkCatchBUSERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkCatchINTERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkCatchSFERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkCatchHARDERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkCatchDummy</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkUsbSerialNo</name> + + <state/> + + </option> + + <option> + + <name>CCSTLinkUsbSerialNoSelect</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkJtagSpeedList</name> + + <version>2</version> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkDAPNumber</name> + + <state/> + + </option> + + <option> + + <name>CCSTLinkDebugAccessPortRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkUseServerSelect</name> + + <state>0</state> + + </option> + + <option> + + <name>CCSTLinkProbeList</name> + + <version>1</version> + + <state>0</state> + + </option> + + </data> + + </settings> + + <settings> + + <name>THIRDPARTY_ID</name> + + <archiveVersion>2</archiveVersion> + + <data> + + <version>0</version> + + <wantNonLocal>1</wantNonLocal> + + <debug>1</debug> + + <option> + + <name>CThirdPartyDriverDll</name> + + <state>###Uninitialized###</state> + + </option> + + <option> + + <name>CThirdPartyLogFileCheck</name> + + <state>0</state> + + </option> + + <option> + + <name>CThirdPartyLogFileEditB</name> + + <state>$PROJ_DIR$\cspycomm.log</state> + + </option> + + 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<state>0</state> + + </option> + + <option> + + <name>TIPackage</name> + + <state/> + + </option> + + <option> + + <name>BoardFile</name> + + <state/> + + </option> + + <option> + + <name>DoLogfile</name> + + <state>0</state> + + </option> + + <option> + + <name>LogFile</name> + + <state>$PROJ_DIR$\cspycomm.log</state> + + </option> + + <option> + + <name>CCXds100BreakpointRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100DoUpdateBreakpoints</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100UpdateBreakpoints</name> + + <state>_call_main</state> + + </option> + + <option> + + <name>CCXds100CatchReset</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchUndef</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchSWI</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchData</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchPrefetch</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchIRQ</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchFIQ</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchCORERESET</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchMMERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchNOCPERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchCHRERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchSTATERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchBUSERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchINTERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchSFERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchHARDERR</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CatchDummy</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100CpuClockEdit</name> + + <state/> + + </option> + + <option> + + <name>CCXds100SwoClockAuto</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100SwoClockEdit</name> + + <state>1000</state> + + </option> + + <option> + + <name>CCXds100HWResetDelay</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100ResetList</name> + + <version>0</version> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100UsbSerialNo</name> + + <state/> + + </option> + + <option> + + <name>CCXds100UsbSerialNoSelect</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100JtagSpeedList</name> + + <version>0</version> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100InterfaceRadio</name> + + <state>0</state> + + </option> + + <option> + + <name>CCXds100InterfaceCmdLine</name> + + <state>0</state> + + </option> + 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<file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + <plugin> + + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + + <loadFlag>0</loadFlag> + + </plugin> + + </debuggerPlugins> + + </configuration> + +</project> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp new file mode 100644 index 000000000..f6535af54 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp @@ -0,0 +1,1422 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>35</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>BrowseInfoPath</name> + <state>Debug/BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>$PROJ_DIR$/Debug</state> + </option> + <option> + <name>ObjPath</name> + <state>$PROJ_DIR$/Debug/Objects</state> + </option> + <option> + <name>ListPath</name> + <state>$PROJ_DIR$/Debug/Listings</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>No specifier a, A, no specifier n, no float nor long long, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>6.50.6.4952</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>9.32.2.57275</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>LPC55S69_core0 NXP LPC55S69_core0</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>0</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>1</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>32</version> + <state>61</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> 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<name>$PROJ_DIR$\..\..\..\..\..\Source\queue.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\stream_buffer.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\tasks.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\timers.c</name> + </file> + </group> + <group> + <name>NXP_Code</name> + <group> + <name>board</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\board.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\board.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\clock_config.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\clock_config.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\pin_mux.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\pin_mux.h</name> + </file> + </group> + <group> + <name>CMSIS</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_compiler.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_gcc.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_iccarm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_version.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\core_cm33.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\mpu_armv8.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\tz_context.h</name> + </file> + </group> + <group> + <name>component</name> + <group> + <name>lists</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\component\lists\fsl_component_generic_list.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\component\lists\fsl_component_generic_list.h</name> + </file> + </group> + <group> + <name>uart</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\component\uart\fsl_adapter_uart.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\component\uart\fsl_adapter_usart.c</name> + </file> + </group> + </group> + <group> + <name>device</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\device\fsl_device_registers.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\device\LPC55S69_cm33_core0.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\device\LPC55S69_cm33_core0_features.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\device\system_LPC55S69_cm33_core0.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\device\system_LPC55S69_cm33_core0.h</name> + </file> + </group> + <group> + <name>drivers</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_clock.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_clock.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common_arm.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common_arm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_flexcomm.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_flexcomm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_gpio.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_gpio.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_iocon.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_power.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_power.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_reset.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_reset.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_usart.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_usart.h</name> + </file> + </group> + <group> + <name>startup</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\startup\startup_LPC55S69_cm33_core0.s</name> + </file> + </group> + <group> + <name>utilities</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_assert.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_debug_console.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_debug_console.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_str.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_str.h</name> + </file> + </group> + </group> + <group> + <name>User</name> + <file> + <name>$PROJ_DIR$\fault_handler.s</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\User\NonSecure\main_ns.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\RegTests\reg_tests.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\RegTests\reg_tests.h</name> + </file> + </group> +</project> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/fault_handler.s b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/fault_handler.s new file mode 100644 index 000000000..70cba7358 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/fault_handler.s @@ -0,0 +1,42 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + EXTERN vHandleMemoryFault + PUBLIC MemManage_Handler + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +MemManage_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vHandleMemoryFault +/*-----------------------------------------------------------*/ + + END diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_flash_s.icf b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_flash_s.icf new file mode 100644 index 000000000..fbccbfc44 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_flash_s.icf @@ -0,0 +1,122 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +/* Only the first 64kB of flash is used as secure memory. */ +define symbol m_interrupts_start = 0x10000000; +define symbol m_interrupts_end = 0x100001FF; + +define symbol m_text_start = 0x10000200; +define symbol m_text_end = 0x1000FDFF; + +define exported symbol core1_image_start = 0x10072000; +define exported symbol core1_image_end = 0x1009D7FF; + +/* Only first 32kB of data RAM is used as secure memory. */ +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_data_start = 0x30000000; + define symbol m_data_end = 0x30007FFF; + define exported symbol rpmsg_sh_mem_start = 0x30031800; + define exported symbol rpmsg_sh_mem_end = 0x30032FFF; +} else { + define symbol m_data_start = 0x30000000; + define symbol m_data_end = 0x30007FFF; +} + +/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */ +define symbol m_veneer_table_start = 0x1000FE00; +define symbol m_veneer_table_size = 0x200; + +define symbol m_usb_sram_start = 0x50100000; +define symbol m_usb_sram_end = 0x50103FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define region VENEER_TABLE_region = mem:[from m_veneer_table_start to m_veneer_table_start + m_veneer_table_size - 1]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block CORE1_IMAGE_WBLOCK { section __core1_image }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in VENEER_TABLE_region { section Veneer$$CMSE }; + +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block CORE1_IMAGE_WBLOCK }; + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd new file mode 100644 index 000000000..b23ea7ac4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd @@ -0,0 +1,1554 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state></state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\LPC55S69_core0.ddf</state> + </option> + <option> + <name>RunToEnable</name> + <state>1</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>1</state> + </option> + <option> + <name>OCProductVersion</name> + <state>6.50.6.4952</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>CMSISDAP_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>9.32.2.57275</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>1</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$/config/flashloader/NXP/FlashLPC5500.board</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>1</state> + </option> + <option> + <name>OCImagesPath1</name> + <state>$PROJ_DIR$/../NonSecure/Debug/FreeRTOSDemo_ns.out</state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state>0x0</state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state>$PROJ_DIR$/../FreeRTOSDemo.eww</state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state>FreeRTOSDemo_ns</state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>1</state> + </option> + <option> + <name>MassEraseBeforeFlashing</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreNrOfCoresSlave</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreAMPConfigType</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreSessionFile</name> + <state></state> + </option> + <option> + <name>OCTpiuBaseOption</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCSimEnablePSP</name> + <state>0</state> + </option> + <option> + <name>OCSimPspOverrideConfig</name> + <state>0</state> + </option> + <option> + <name>OCSimPspConfigFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>CADI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + 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</option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + <option> + <name>CCXDSTargetVccEnable</name> + <state>0</state> + </option> + <option> + <name>CCXDSTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>OCXDSDigitalStatesConfigFile</name> + <state>1</state> + </option> + <option> + <name>OCSelectedCoreName</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp new file mode 100644 index 000000000..0ab1d3272 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp @@ -0,0 +1,1340 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>35</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>BrowseInfoPath</name> + <state>Debug/BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>$PROJ_DIR$/Debug</state> + </option> + <option> + <name>ObjPath</name> + <state>$PROJ_DIR$/Debug/Objects</state> + </option> + <option> + <name>ListPath</name> + <state>$PROJ_DIR$/Debug/Listings</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>No specifier a, A, no specifier n, no float nor long long, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>6.50.6.4952</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>9.32.2.57275</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>LPC55S69_core0 NXP LPC55S69_core0</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>0</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>1</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>32</version> + <state>61</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>32</version> + <state>61</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>LPC55S69_core0 NXP LPC55S69_core0</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>6</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>NEON</name> + <state>0</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>32</version> + <state>61</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>1</state> + </option> + <option> + <name>TrustZone</name> + <state>1</state> + </option> + <option> + <name>TrustZoneModes</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGAarch64Abi</name> + <state>0</state> + </option> + <option> + <name>OG_32_64Device</name> + <state>0</state> + </option> + <option> + <name>BuildFilesPath</name> + <state>Debug</state> + </option> + <option> + <name>PointerAuthentication</name> + <state>0</state> + </option> + <option> + <name>FPU64</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>37</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCDefines</name> + <state>DEBUG</state> + <state>CPU_LPC55S69JBD100_cm33_core0</state> + <state>MCUXPRESSO_SDK</state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>1</state> + </option> + <option> + <name>CCListCMessages</name> + <state>1</state> + </option> + <option> + <name>CCListAssFile</name> + <state>1</state> + </option> + <option> + <name>CCListAssSource</name> + <state>1</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state>Pa082,Pa050</state> + </option> + <option> + <name>CCDiagRemark</name> + <state></state> + </option> + <option> + <name>CCDiagWarning</name> + <state></state> + </option> + <option> + <name>CCDiagError</name> + <state></state> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>00100000</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>1</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>1</state> + </option> + <option> + <name>IExtraOptions</name> + <state>--cmse</state> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CCIncludePath2</name> + <state>$PROJ_DIR$\..\Config</state> + <state>$PROJ_DIR$\..\..\..\NXP_Code\board</state> + <state>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS</state> + <state>$PROJ_DIR$\..\..\..\NXP_Code\component\lists</state> + <state>$PROJ_DIR$\..\..\..\NXP_Code\component\uart</state> + <state>$PROJ_DIR$\..\..\..\NXP_Code\device</state> + <state>$PROJ_DIR$\..\..\..\NXP_Code\drivers</state> + <state>$PROJ_DIR$\..\..\..\NXP_Code\trustzone</state> + <state>$PROJ_DIR$\..\..\..\NXP_Code\utilities</state> + <state>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure</state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>1</state> + </option> + <option> + <name>CCOptLevel</name> + <state>1</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>0</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + <option> + <name>OICompilerExtraOption</name> + <state>1</state> + </option> + <option> + <name>CCStackProtection</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>11</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>AWarnEnable</name> + <state>1</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state></state> + </option> + <option> + <name>AWarnRange1</name> + <state></state> + </option> + <option> + <name>AWarnRange2</name> + <state></state> + </option> + <option> + <name>ADebug</name> + <state>1</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>1</state> + </option> + <option> + <name>ADefines</name> + <state>DEBUG</state> + </option> + <option> + <name>AList</name> + <state>0</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>0</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>AOutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state>$PROJ_DIR$\..\Config</state> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state></state> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>3</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>0</state> + </option> + <option> + <name>OOCOutputFile</name> + <state>FreeRTOSDemo_s.bin</state> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <hasPrio>1</hasPrio> + <buildSequence>inputOutputBased</buildSequence> + </data> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild></prebuild> + <postbuild></postbuild> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>27</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>FreeRTOSDemo_s.out</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryFile</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign</name> + <state></state> + </option> + <option> + <name>IlinkDefines</name> + <state></state> + </option> + <option> + <name>IlinkConfigDefines</name> + <state></state> + </option> + <option> + <name>IlinkMapFile</name> + <state>1</state> + </option> + <option> + <name>IlinkLogFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInitialization</name> + <state>0</state> + </option> + <option> + <name>IlinkLogModule</name> + <state>0</state> + </option> + <option> + <name>IlinkLogSection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogVeneer</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfOverride</name> + <state>1</state> + </option> + <option> + <name>IlinkIcfFile</name> + <state>$PROJ_DIR$/FreeRTOSDemo_flash_s.icf</state> + </option> + <option> + <name>IlinkIcfFileSlave</name> + <state></state> + </option> + <option> + <name>IlinkEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>IlinkSuppressDiags</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsRem</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsWarn</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsErr</name> + <state></state> + </option> + <option> + <name>IlinkWarningsAreErrors</name> + <state>0</state> + </option> + <option> + <name>IlinkUseExtraOptions</name> + <state>0</state> + </option> + <option> + <name>IlinkExtraOptions</name> + <state></state> + </option> + <option> + <name>IlinkLowLevelInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkAutoLibEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkAdditionalLibs</name> + <state></state> + </option> + <option> + <name>IlinkOverrideProgramEntryLabel</name> + <state>1</state> + </option> + <option> + <name>IlinkProgramEntryLabelSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabel</name> + <state>Reset_Handler</state> + </option> + <option> + <name>DoFill</name> + <state>0</state> + </option> + <option> + <name>FillerByte</name> + <state>0xFF</state> + </option> + <option> + <name>FillerStart</name> + <state>0x0</state> + </option> + <option> + <name>FillerEnd</name> + <state>0x0</state> + </option> + <option> + <name>CrcSize</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CrcAlign</name> + <state>1</state> + </option> + <option> + <name>CrcPoly</name> + <state>0x11021</state> + </option> + <option> + <name>CrcCompl</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcBitOrder</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcInitialValue</name> + <state>0x0</state> + </option> + <option> + <name>DoCrc</name> + <state>0</state> + </option> + <option> + <name>IlinkBE8Slave</name> + <state>1</state> + </option> + <option> + <name>IlinkBufferedTerminalOutput</name> + <state>1</state> + </option> + <option> + <name>IlinkStdoutInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>CrcFullSize</name> + <state>0</state> + </option> + <option> + <name>IlinkIElfToolPostProcess</name> + <state>0</state> + </option> + <option> + <name>IlinkLogAutoLibSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkLogRedirSymbols</name> + <state>0</state> + </option> + <option> + <name>IlinkLogUnusedFragments</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcReverseByteOrder</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcUseAsInput</name> + <state>1</state> + </option> + <option> + <name>IlinkOptInline</name> + <state>0</state> + </option> + <option> + <name>IlinkOptExceptionsAllow</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsForce</name> + <state>0</state> + </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state></state> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state></state> + </option> + <option> + <name>CrcAlgorithm</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CrcUnitSize</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IlinkThreadsSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkLogCallGraph</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile_AltDefault</name> + <state></state> + </option> + <option> + <name>IlinkEncInput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>IlinkHeapSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkLocaleSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkTrustzoneImportLibraryOut</name> + <state>FreeRTOSDemo_s_import_lib.o</state> + </option> + <option> + <name>OILinkExtraOption</name> + <state>1</state> + </option> + <option> + <name>IlinkRawBinaryFile2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign2</name> + <state></state> + </option> + <option> + <name>IlinkLogCrtRoutineSelection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFragmentInfo</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInlining</name> + <state>0</state> + </option> + <option> + <name>IlinkLogMerging</name> + <state>0</state> + </option> + <option> + <name>IlinkDemangle</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFileEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFile</name> + <state></state> + </option> + <option> + <name>IlinkProcessor</name> + <state>1</state> + </option> + <option> + <name>IlinkFpuProcessor</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + </configuration> + <group> + <name>Config</name> + <file> + <name>$PROJ_DIR$\..\Config\FreeRTOSConfig.h</name> + </file> + </group> + <group> + <name>Demos</name> + <group> + <name>reg_tests</name> + <file> + <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\reg_tests\IAR\ARM_CM33\secure\secure_reg_test.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\reg_tests\IAR\ARM_CM33\secure\secure_reg_test_asm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\reg_tests\IAR\ARM_CM33\secure\secure_reg_test_asm.s</name> + </file> + </group> + </group> + <group> + <name>FreeRTOS</name> + <group> + <name>portable</name> + <group> + <name>IAR</name> + <group> + <name>ARM_CM33</name> + <group> + <name>secure</name> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_context.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_context.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_context_port_asm.s</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_heap.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_heap.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_init.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_init.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_port_macros.h</name> + </file> + </group> + </group> + </group> + </group> + </group> + <group> + <name>NSC_Functions</name> + <file> + <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\tz_demo\nsc_functions.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\tz_demo\nsc_functions.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NSC_Functions\nsc_printf.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NSC_Functions\nsc_printf.h</name> + </file> + </group> + <group> + <name>NXP_Code</name> + <group> + <name>board</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\board.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\board.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\clock_config.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\clock_config.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\pin_mux.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\board\pin_mux.h</name> + </file> + </group> + <group> + <name>CMSIS</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_compiler.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_gcc.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_iccarm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_version.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\core_cm33.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\mpu_armv8.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\CMSIS\tz_context.h</name> + </file> + </group> + <group> + <name>component</name> + <group> + <name>lists</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\component\lists\fsl_component_generic_list.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\component\lists\fsl_component_generic_list.h</name> + </file> + </group> + <group> + <name>uart</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\component\uart\fsl_adapter_uart.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\component\uart\fsl_adapter_usart.c</name> + </file> + </group> + </group> + <group> + <name>device</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\device\fsl_device_registers.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\device\LPC55S69_cm33_core0.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\device\LPC55S69_cm33_core0_features.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\device\system_LPC55S69_cm33_core0.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\device\system_LPC55S69_cm33_core0.h</name> + </file> + </group> + <group> + <name>drivers</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_clock.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_clock.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common_arm.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common_arm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_flexcomm.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_flexcomm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_gpio.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_gpio.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_iocon.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_power.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_power.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_reset.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_reset.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_usart.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_usart.h</name> + </file> + </group> + <group> + <name>startup</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\startup\startup_LPC55S69_cm33_core0.s</name> + </file> + </group> + <group> + <name>trustzone</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\trustzone\tzm_config.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\trustzone\tzm_config.h</name> + </file> + </group> + <group> + <name>utilities</name> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_assert.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_debug_console.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_debug_console.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_str.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_str.h</name> + </file> + </group> + </group> + <group> + <name>User</name> + <file> + <name>$PROJ_DIR$\..\..\..\User\Secure\main_s.c</name> + </file> + </group> +</project> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h index a1348de26..7d56eee98 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h @@ -25,8 +25,8 @@ */
/******************************************************************************
- See http://www.freertos.org/a00110.html for an explanation of the
- definitions contained in this file.
+ See http://www.freertos.org/a00110.html for an explanation of the
+ definitions contained in this file.
******************************************************************************/
#ifndef FREERTOS_CONFIG_H
@@ -46,122 +46,122 @@ #include "clock_config.h"
/* Cortex M33 port configuration. */
-#define configENABLE_MPU 1
-#define configENABLE_FPU 1
-#define configENABLE_TRUSTZONE 1
+#define configENABLE_MPU 1
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 1
/* Constants related to the behaviour or the scheduler. */
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define configUSE_PREEMPTION 1
-#define configUSE_TIME_SLICING 1
-#define configMAX_PRIORITIES ( 5 )
-#define configIDLE_SHOULD_YIELD 1
-#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configUSE_PREEMPTION 1
+#define configUSE_TIME_SLICING 1
+#define configMAX_PRIORITIES ( 5 )
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */
/* Constants that describe the hardware and memory usage. */
-#define configCPU_CLOCK_HZ BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK
-#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )
-#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
-#define configMAX_TASK_NAME_LEN ( 12 )
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )
+#define configCPU_CLOCK_HZ BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK
+#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )
+#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
+#define configMAX_TASK_NAME_LEN ( 12 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )
/* Constants that build features in or out. */
-#define configUSE_MUTEXES 1
-#define configUSE_TICKLESS_IDLE 1
-#define configUSE_APPLICATION_TASK_TAG 0
-#define configUSE_NEWLIB_REENTRANT 0
-#define configUSE_COUNTING_SEMAPHORES 1
-#define configUSE_RECURSIVE_MUTEXES 1
-#define configUSE_QUEUE_SETS 0
-#define configUSE_TASK_NOTIFICATIONS 1
-#define configUSE_TRACE_FACILITY 1
+#define configUSE_MUTEXES 1
+#define configUSE_TICKLESS_IDLE 1
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_TRACE_FACILITY 1
/* Constants that define which hook (callback) functions should be used. */
-#define configUSE_IDLE_HOOK 0
-#define configUSE_TICK_HOOK 0
-#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0
/* Constants provided for debugging and optimisation assistance. */
-#define configCHECK_FOR_STACK_OVERFLOW 2
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
-#define configQUEUE_REGISTRY_SIZE 0
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+#define configQUEUE_REGISTRY_SIZE 0
/* Software timer definitions. */
-#define configUSE_TIMERS 1
-#define configTIMER_TASK_PRIORITY ( 3 )
-#define configTIMER_QUEUE_LENGTH 5
-#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( 3 )
+#define configTIMER_QUEUE_LENGTH 5
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
/* Set the following definitions to 1 to include the API function, or zero
* to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is
* only necessary if the linker does not automatically remove functions that are
* not referenced anyway. */
-#define INCLUDE_vTaskPrioritySet 1
-#define INCLUDE_uxTaskPriorityGet 1
-#define INCLUDE_vTaskDelete 1
-#define INCLUDE_vTaskCleanUpResources 0
-#define INCLUDE_vTaskSuspend 1
-#define INCLUDE_vTaskDelayUntil 1
-#define INCLUDE_vTaskDelay 1
-#define INCLUDE_uxTaskGetStackHighWaterMark 0
-#define INCLUDE_xTaskGetIdleTaskHandle 0
-#define INCLUDE_eTaskGetState 1
-#define INCLUDE_xTaskResumeFromISR 0
-#define INCLUDE_xTaskGetCurrentTaskHandle 1
-#define INCLUDE_xTaskGetSchedulerState 0
-#define INCLUDE_xSemaphoreGetMutexHolder 0
-#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 1
+#define INCLUDE_xTaskResumeFromISR 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xSemaphoreGetMutexHolder 0
+#define INCLUDE_xTimerPendFunctionCall 1
/* This demo makes use of one or more example stats formatting functions. These
* format the raw data provided by the uxTaskGetSystemState() function in to
* human readable ASCII form. See the notes in the implementation of vTaskList()
* within FreeRTOS/Source/tasks.c for limitations. */
-#define configUSE_STATS_FORMATTING_FUNCTIONS 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1
/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter.
* See the FreeRTOS+CLI documentation for more information:
* https://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */
-#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048
/* Interrupt priority configuration follows...................... */
/* Use the system definition, if there is one. */
#ifdef __NVIC_PRIO_BITS
- #define configPRIO_BITS __NVIC_PRIO_BITS
+ #define configPRIO_BITS __NVIC_PRIO_BITS
#else
- #define configPRIO_BITS 3 /* 8 priority levels. */
+ #define configPRIO_BITS 3 /* 8 priority levels. */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
* function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07
/* The highest interrupt priority that can be used by any interrupt service
* routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT
* CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A
* HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
* to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
* See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )
/* The #ifdef guards against the file being included from IAR assembly files. */
#ifndef __IASMARM__
- /* Constants related to the generation of run time stats. */
- #define configGENERATE_RUN_TIME_STATS 0
- #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
- #define portGET_RUN_TIME_COUNTER_VALUE() 0
- #define configTICK_RATE_HZ ( ( TickType_t ) 100 )
+ /* Constants related to the generation of run time stats. */
+ #define configGENERATE_RUN_TIME_STATS 0
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+ #define portGET_RUN_TIME_COUNTER_VALUE() 0
+ #define configTICK_RATE_HZ ( ( TickType_t ) 100 )
#endif /* __IASMARM__ */
/* Enable static allocation. */
-#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_STATIC_ALLOCATION 1
#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject index e5ea92f11..9d63c2c65 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject @@ -115,6 +115,8 @@ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.include.paths.88237135" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="../../Config"/>
<listOptionValue builtIn="false" value="../../Secure"/>
+ <listOptionValue builtIn="false" value="../../../../NSC_Functions"/>
+ <listOptionValue builtIn="false" value="../../../../RegTests"/>
<listOptionValue builtIn="false" value="../../../../NXP_Code"/>
<listOptionValue builtIn="false" value="../../../../NXP_Code/board"/>
<listOptionValue builtIn="false" value="../../../../NXP_Code/source"/>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project index 4afbd6e4e..8588fa7ec 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project @@ -83,19 +83,24 @@ <locationURI>PARENT-4-PROJECT_LOC/Common/ARMv8M/tz_demo/tz_demo.h</locationURI>
</link>
<link>
+ <name>User/fault_handler.c</name>
+ <type>1</type>
+ <locationURI>PROJECT_LOC/fault_handler.c</locationURI>
+ </link>
+ <link>
<name>User/main_ns.c</name>
<type>1</type>
- <locationURI>PROJECT_LOC/main_ns.c</locationURI>
+ <locationURI>DEMO_ROOT/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NonSecure/main_ns.c</locationURI>
</link>
<link>
- <name>User/res_tests.c</name>
+ <name>User/reg_tests.c</name>
<type>1</type>
- <locationURI>PROJECT_LOC/reg_tests.c</locationURI>
+ <locationURI>DEMO_ROOT/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.c</locationURI>
</link>
</linkedResources>
<filteredResources>
<filter>
- <id>1681724631111</id>
+ <id>1682451970778</id>
<name></name>
<type>6</type>
<matcher>
@@ -104,7 +109,7 @@ </matcher>
</filter>
<filter>
- <id>1681724631147</id>
+ <id>1682451970814</id>
<name></name>
<type>6</type>
<matcher>
@@ -113,6 +118,15 @@ </matcher>
</filter>
<filter>
+ <id>1682451751797</id>
+ <name>NXP_Code</name>
+ <type>10</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-trustzone</arguments>
+ </matcher>
+ </filter>
+ <filter>
<id>1681721788469</id>
<name>reg_tests</name>
<type>9</type>
@@ -158,6 +172,15 @@ </matcher>
</filter>
<filter>
+ <id>1682451733052</id>
+ <name>NXP_Code/startup</name>
+ <type>6</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-startup_LPC55S69_cm33_core0.s</arguments>
+ </matcher>
+ </filter>
+ <filter>
<id>1681721804811</id>
<name>reg_tests/GCC</name>
<type>9</type>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.settings/org.eclipse.core.resources.prefs b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 000000000..99f26c020 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/<project>=UTF-8 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/fault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/fault_handler.c new file mode 100644 index 000000000..0a6d1b9ab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/fault_handler.c @@ -0,0 +1,50 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @brief The mem fault handler. + * + * It calls a function called vHandleMemoryFault. + */ +void MemManage_Handler( void ) __attribute__ ( ( naked ) ); +/*-----------------------------------------------------------*/ + +void MemManage_Handler( void ) /* __attribute__ ( ( naked ) ) */ +{ + __asm volatile + ( + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, handler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + " handler_address_const: .word vHandleMemoryFault \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/main_ns.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/main_ns.c deleted file mode 100644 index 7967a3c68..000000000 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/main_ns.c +++ /dev/null @@ -1,198 +0,0 @@ -/*
- * FreeRTOS V202212.00
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* FreeRTOS include. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Device includes. */
-#include "fsl_device_registers.h"
-#include "fsl_debug_console.h"
-#include "pin_mux.h"
-#include "board.h"
-#include "clock_config.h"
-#include "fsl_power.h"
-
-/* Demo includes. */
-#include "tz_demo.h"
-#include "mpu_demo.h"
-#include "reg_tests.h"
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Create all demo tasks.
- */
-static void prvCreateTasks( void );
-
-/**
- * @brief Setup hardware.
- */
-static void prvSetupHardware( void );
-
-/**
- * @brief Application-specific implementation of the SystemInit() weak
- * function.
- */
-void SystemInit( void );
-
-/**
- * @brief The mem fault handler.
- *
- * It calls a function called vHandleMemoryFault.
- */
-void MemManage_Handler( void ) __attribute__ ( ( naked ) );
-/*-----------------------------------------------------------*/
-
-/* For instructions on how to build and run this demo, visit the following link:
- * https://www.freertos.org/RTOS-Cortex-M33-LPC55S69-MCUXpresso-GCC.html
- */
-
-/* Non-Secure main. */
-int main( void )
-{
- /* Setup hardware. */
- prvSetupHardware();
-
- /* Create tasks. */
- prvCreateTasks();
-
- /* Start scheduler. */
- vTaskStartScheduler();
-
- /* Will not get here if the scheduler starts successfully. If you do end up
- here then there wasn't enough heap memory available to start either the idle
- task or the timer/daemon task. https://www.freertos.org/a00111.html */
-
- for( ; ; )
- {
- }
-}
-/*-----------------------------------------------------------*/
-
-static void prvCreateTasks( void )
-{
- /* Create tasks for the MPU Demo. */
- vStartMPUDemo();
-
- /* Create tasks for the TZ Demo. */
- vStartTZDemo();
-
- /* Create tasks for reg tests. */
- vStartRegTests();
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupHardware( void )
-{
- /* Set BOD VBAT level to 1.65V. */
- POWER_SetBodVbatLevel( kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false );
-}
-/*-----------------------------------------------------------*/
-
-void SystemInit( void )
-{
- /* Nothing needs to be initialized for Non-Secure project. */
-}
-/*-----------------------------------------------------------*/
-
-/* Stack overflow hook. */
-void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName )
-{
- /* Force an assert. */
- configASSERT( pcTaskName == 0 );
-}
-/*-----------------------------------------------------------*/
-
-/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
- * implementation of vApplicationGetIdleTaskMemory() to provide the memory that
- * is used by the Idle task. */
-void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
- StackType_t ** ppxIdleTaskStackBuffer,
- uint32_t * pulIdleTaskStackSize )
-{
- /* If the buffers to be provided to the Idle task are declared inside this
- * function then they must be declared static - otherwise they will be
- * allocated on the stack and so not exists after this function exits. */
- static StaticTask_t xIdleTaskTCB;
- static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
-
- /* Pass out a pointer to the StaticTask_t structure in which the Idle
- * task's state will be stored. */
- *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
-
- /* Pass out the array that will be used as the Idle task's stack. */
- *ppxIdleTaskStackBuffer = uxIdleTaskStack;
-
- /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
- * Note that, as the array is necessarily of type StackType_t,
- * configMINIMAL_STACK_SIZE is specified in words, not bytes. */
- *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
-}
-/*-----------------------------------------------------------*/
-
-/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
- * application must provide an implementation of vApplicationGetTimerTaskMemory()
- * to provide the memory that is used by the Timer service task. */
-void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
- StackType_t ** ppxTimerTaskStackBuffer,
- uint32_t * pulTimerTaskStackSize )
-{
- /* If the buffers to be provided to the Timer task are declared inside this
- * function then they must be declared static - otherwise they will be
- * allocated on the stack and so not exists after this function exits. */
- static StaticTask_t xTimerTaskTCB;
- static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__( ( aligned( 32 ) ) );
-
- /* Pass out a pointer to the StaticTask_t structure in which the Timer
- * task's state will be stored. */
- *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
-
- /* Pass out the array that will be used as the Timer task's stack. */
- *ppxTimerTaskStackBuffer = uxTimerTaskStack;
-
- /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
- * Note that, as the array is necessarily of type StackType_t,
- * configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
- *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
-}
-/*-----------------------------------------------------------*/
-
-void MemManage_Handler( void )
-{
- __asm volatile
- (
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
- " ldr r1, handler_address_const \n"
- " bx r1 \n"
- " \n"
- " .align 4 \n"
- " handler_address_const: .word vHandleMemoryFault \n"
- );
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject index 349cc5d2a..bbf6bfa1b 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject @@ -119,6 +119,7 @@ <listOptionValue builtIn="false" value="../../../../NXP_Code/CMSIS"/>
<listOptionValue builtIn="false" value="../../../../NXP_Code/device"/>
<listOptionValue builtIn="false" value="../../../../NXP_Code/startup"/>
+ <listOptionValue builtIn="false" value="../../../../NXP_Code/trustzone"/>
<listOptionValue builtIn="false" value="../../../../NXP_Code/utilities"/>
<listOptionValue builtIn="false" value="../../../../NXP_Code/component/uart"/>
<listOptionValue builtIn="false" value="../../../../NXP_Code/component/lists"/>
@@ -333,16 +334,6 @@ </tool>
</toolChain>
</folderInfo>
- <folderInfo id="com.crt.advproject.config.exe.debug.650465968.1580633237" name="/" resourcePath="reg_tests">
- <toolChain id="com.crt.advproject.toolchain.exe.debug.1643158192" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug" unusedChildren="">
- <tool id="com.crt.advproject.cpp.exe.debug.1303225074" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug.248036726"/>
- <tool id="com.crt.advproject.gcc.exe.debug.806639634" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug.1827685058"/>
- <tool id="com.crt.advproject.gas.exe.debug.2004350830" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug.355931849"/>
- <tool id="com.crt.advproject.link.cpp.exe.debug.141362876" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug.767850316"/>
- <tool id="com.crt.advproject.link.exe.debug.558086384" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug.1425769789"/>
- <tool id="com.crt.advproject.tool.debug.debug.404468304" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.debug.1632770985"/>
- </toolChain>
- </folderInfo>
<sourceEntries>
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Config"/>
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="NSCFunctions"/>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project index b4c624902..4c798137b 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project @@ -124,27 +124,17 @@ <link>
<name>User/main_s.c</name>
<type>1</type>
- <locationURI>PROJECT_LOC/main_s.c</locationURI>
+ <locationURI>DEMO_ROOT/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/Secure/main_s.c</locationURI>
</link>
<link>
<name>User/nsc_printf.c</name>
<type>1</type>
- <locationURI>PROJECT_LOC/nsc_printf.c</locationURI>
+ <locationURI>DEMO_ROOT/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c</locationURI>
</link>
<link>
<name>User/nsc_printf.h</name>
<type>1</type>
- <locationURI>PROJECT_LOC/nsc_printf.h</locationURI>
- </link>
- <link>
- <name>User/tzm_config.c</name>
- <type>1</type>
- <locationURI>PROJECT_LOC/tzm_config.c</locationURI>
- </link>
- <link>
- <name>User/tzm_config.h</name>
- <type>1</type>
- <locationURI>PROJECT_LOC/tzm_config.h</locationURI>
+ <locationURI>DEMO_ROOT/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h</locationURI>
</link>
</linkedResources>
<filteredResources>
@@ -176,6 +166,15 @@ </matcher>
</filter>
<filter>
+ <id>1682451336783</id>
+ <name>NXP_Code/startup</name>
+ <type>6</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-startup_LPC55S69_cm33_core0.s</arguments>
+ </matcher>
+ </filter>
+ <filter>
<id>1681721650651</id>
<name>reg_tests/GCC</name>
<type>9</type>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.settings/org.eclipse.core.resources.prefs b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 000000000..99f26c020 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/<project>=UTF-8 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/Config/FreeRTOSConfig.h new file mode 100644 index 000000000..64b7bcb9c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/Config/FreeRTOSConfig.h @@ -0,0 +1,170 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/****************************************************************************** + See http://www.freertos.org/a00110.html for an explanation of the + definitions contained in this file. +******************************************************************************/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * https://www.FreeRTOS.org/a00110.html + *----------------------------------------------------------*/ + +#ifndef __IASMARM__ + #include "clock_config.h" +#endif + +/* Cortex M33 port configuration. */ +#define configENABLE_MPU 1 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configRUN_FREERTOS_SECURE_ONLY 1 + +/* Constants related to the behaviour or the scheduler. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 1 +#define configMAX_PRIORITIES ( 5 ) +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */ + +/* Constants that describe the hardware and memory usage. */ +#define configCPU_CLOCK_HZ BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK +#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 ) +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) ) + +/* Constants that build features in or out. */ +#define configUSE_MUTEXES 1 +#define configUSE_TICKLESS_IDLE 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_TRACE_FACILITY 1 + +/* Constants that define which hook (callback) functions should be used. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 + +/* Constants provided for debugging and optimisation assistance. */ +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } +#define configQUEUE_REGISTRY_SIZE 0 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 3 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is + * only necessary if the linker does not automatically remove functions that are + * not referenced anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xSemaphoreGetMutexHolder 0 +#define INCLUDE_xTimerPendFunctionCall 1 + +/* This demo makes use of one or more example stats formatting functions. These + * format the raw data provided by the uxTaskGetSystemState() function in to + * human readable ASCII form. See the notes in the implementation of vTaskList() + * within FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter. + * See the FreeRTOS+CLI documentation for more information: + * https://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048 + +/* Interrupt priority configuration follows...................... */ + +/* Use the system definition, if there is one. */ +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 8 priority levels. */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" + * function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 + +/* The highest interrupt priority that can be used by any interrupt service + * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT + * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A + * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic + * to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) + +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) + +/* The #ifdef guards against the file being included from IAR assembly files. */ +#ifndef __IASMARM__ + + /* Constants related to the generation of run time stats. */ + #define configGENERATE_RUN_TIME_STATS 0 + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() + #define portGET_RUN_TIME_COUNTER_VALUE() 0 + #define configTICK_RATE_HZ ( ( TickType_t ) 100 ) + +#endif /* __IASMARM__ */ + +/* Enable static allocation. */ +#define configSUPPORT_STATIC_ALLOCATION 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewd new file mode 100644 index 000000000..b23ea7ac4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewd @@ -0,0 +1,1554 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state></state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\LPC55S69_core0.ddf</state> + </option> + <option> + <name>RunToEnable</name> + <state>1</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>1</state> + </option> + <option> + <name>OCProductVersion</name> + <state>6.50.6.4952</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>CMSISDAP_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>9.32.2.57275</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>1</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$/config/flashloader/NXP/FlashLPC5500.board</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>1</state> + </option> + <option> + <name>OCImagesPath1</name> + <state>$PROJ_DIR$/../NonSecure/Debug/FreeRTOSDemo_ns.out</state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state>0x0</state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state>$PROJ_DIR$/../FreeRTOSDemo.eww</state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state>FreeRTOSDemo_ns</state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>1</state> + </option> + <option> + <name>MassEraseBeforeFlashing</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreNrOfCoresSlave</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreAMPConfigType</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreSessionFile</name> + <state></state> + </option> + <option> + <name>OCTpiuBaseOption</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCSimEnablePSP</name> + <state>0</state> + </option> + <option> + <name>OCSimPspOverrideConfig</name> + <state>0</state> + </option> + <option> + <name>OCSimPspConfigFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>CADI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + <name>Fast Model</name> + <state></state> + </option> + <option> + <name>CCADILogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CCADILogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CMSISDAP_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>4</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CatchSFERR</name> + <state>1</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPResetList</name> + <version>1</version> + <state>4</state> + </option> + <option> + <name>CMSISDAPHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>CMSISDAPHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>CMSISDAPDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CMSISDAPInterfaceRadio</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CMSISDAPBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>0</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>0</state> + </option> + <option> + <name>RDICatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>RDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>RDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CatchCHKERR</name> + <state>0</state> + </option> + <option> + <name>CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiCPUEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiCPUNumber</name> + <state>0</state> + </option> + <option> + <name>OCProbeCfgOverride</name> + <state>0</state> + </option> + <option> + <name>OCProbeConfig</name> + <state>$TOOLKIT_DIR$/config/debugger/NXP/LPC55S69_cpu0.ProbeConfig</state> + </option> + <option> + <name>CMSISDAPProbeConfigRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPSelectedCPUBehaviour</name> + <state></state> + </option> + <option> + <name>ICpuName</name> + <state></state> + </option> + <option> + <name>OCJetEmuParams</name> + <state>1</state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNoSelect</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>GDBSERVER_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJTagBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJTagDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJTagUpdateBreakpoints</name> + <state>_call_main</state> + </option> + </data> + </settings> + <settings> + <name>IJET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>9</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CatchSFERR</name> + <state>1</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>IjetResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>IjetHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>IjetHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>IjetPowerFromProbe</name> + <state>1</state> + </option> + <option> + <name>IjetPowerRadio</name> + <state>0</state> + </option> + <option> + <name>IjetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>IjetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>IjetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>IjetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>IjetMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>IjetMultiTarget</name> + <state>0</state> + </option> + <option> + <name>IjetScanChainNonARMDevices</name> + <state>0</state> + </option> + <option> + <name>IjetIRLength</name> + <state>0</state> + </option> + <option> + <name>IjetJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IjetProtocolRadio</name> + <state>0</state> + </option> + <option> + <name>IjetSwoPin</name> + <state>0</state> + </option> + <option> + <name>IjetCpuClockEdit</name> + <state>72.0</state> + </option> + <option> + <name>IjetSwoPrescalerList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>IjetBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>IjetRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>IjetUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>1</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>1</state> + </option> + <option> + <name>RDICatchPrefetch</name> + <state>1</state> + </option> + <option> + <name>RDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>RDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CatchMMERR</name> + <state>1</state> + </option> + <option> + <name>CatchNOCPERR</name> + <state>1</state> + </option> + <option> + <name>CatchCHKERR</name> + <state>1</state> + </option> + <option> + <name>CatchSTATERR</name> + <state>1</state> + </option> + <option> + <name>CatchBUSERR</name> + <state>1</state> + </option> + <option> + <name>CatchINTERR</name> + <state>1</state> + </option> + <option> + <name>CatchHARDERR</name> + <state>1</state> + </option> + <option> + <name>CatchDummy</name> + <state>0</state> + </option> + <option> + <name>OCProbeCfgOverride</name> + <state>0</state> + </option> + <option> + <name>OCProbeConfig</name> + <state></state> + </option> + <option> + <name>IjetProbeConfigRadio</name> + <state>0</state> + </option> + <option> + <name>IjetMultiCPUEnable</name> + <state>0</state> + </option> + <option> + <name>IjetMultiCPUNumber</name> + <state>0</state> + </option> + <option> + <name>IjetSelectedCPUBehaviour</name> + <state>0</state> + </option> + <option> + <name>ICpuName</name> + <state></state> + </option> + <option> + <name>OCJetEmuParams</name> + <state>1</state> + </option> + <option> + <name>IjetPreferETB</name> + <state>1</state> + </option> + <option> + <name>IjetTraceSettingsList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IjetTraceSizeList</name> + <version>0</version> + <state>4</state> + </option> + <option> + <name>FlashBoardPathSlave</name> + <state>0</state> + </option> + <option> + <name>CCIjetUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCIjetUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARReset</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL3S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL3S</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL3S</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>JLINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>16</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCCatchSFERR</name> + <state>0</state> + </option> + <option> + <name>JLinkSpeed</name> + <state>32</state> + </option> + <option> + <name>CCJLinkDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCJLinkLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJLinkHWResetDelay</name> + <state>0</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>JLinkInitialSpeed</name> + <state>32</state> + </option> + <option> + <name>CCDoJlinkMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CCScanChainNonARMDevices</name> + <state>0</state> + </option> + <option> + <name>CCJLinkMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CCJLinkIRLength</name> + <state>0</state> + </option> + <option> + <name>CCJLinkCommRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkTCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>CCJLinkSpeedRadioV2</name> + <state>0</state> + </option> + <option> + <name>CCUSBDevice</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CCRDICatchReset</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchData</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCJLinkBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJLinkUpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCJLinkInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkResetList</name> + <version>6</version> + <state>5</state> + </option> + <option> + <name>CCJLinkInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCCatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCCatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchDummy</name> + <state>0</state> + </option> + <option> + <name>OCJLinkScriptFile</name> + <state>1</state> + </option> + <option> + <name>CCJLinkUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCTcpIpAlt</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCJLinkTcpIpSerialNo</name> + <state></state> + </option> + <option> + <name>CCCpuClockEdit</name> + <state>72.0</state> + </option> + <option> + <name>CCSwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCSwoClockEdit</name> + <state>2000</state> + </option> + <option> + <name>OCJLinkTraceSource</name> + <state>0</state> + </option> + <option> + <name>OCJLinkTraceSourceDummy</name> + <state>0</state> + </option> + <option> + <name>OCJLinkDeviceName</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>LMIFTDI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>3</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>LmiftdiSpeed</name> + <state>500</state> + </option> + <option> + <name>CCLmiftdiDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCLmiFtdiInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCLmiFtdiInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCLmiftdiUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiResetList</name> + <version>0</version> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>NULINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + </data> + </settings> + <settings> + <name>PEMICRO_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>3</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCJPEMicroShowSettings</name> + <state>0</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + </data> + </settings> + <settings> + <name>STLINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>8</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCSTLinkInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkResetList</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>CCCpuClockEdit</name> + <state>72.0</state> + </option> + <option> + <name>CCSwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCSwoClockEdit</name> + <state>2000</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCSTLinkDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCSTLinkCatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCSTLinkUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkJtagSpeedList</name> + <version>2</version> + <state>0</state> + </option> + <option> + <name>CCSTLinkDAPNumber</name> + <state></state> + </option> + <option> + <name>CCSTLinkDebugAccessPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUseServerSelect</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkProbeList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>CCSTLinkTargetVccEnable</name> + <state>1</state> + </option> + <option> + <name>CCSTLinkTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + </data> + </settings> + <settings> + <name>THIRDPARTY_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CThirdPartyDriverDll</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CThirdPartyLogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CThirdPartyLogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>TIFET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetResetList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVccTypeDefault</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CCMSPFetVCCDefault</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetTargetSettlingtime</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetRadioJtagSpeedType</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetConnection</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetUsbComPort</name> + <state>Automatic</state> + </option> + <option> + <name>CCMSPFetAllowAccessToBSL</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCMSPFetRadioEraseFlash</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>XDS100_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>9</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TIPackageOverride</name> + <state>0</state> + </option> + <option> + <name>TIPackage</name> + <state></state> + </option> + <option> + <name>BoardFile</name> + <state></state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCXds100BreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100DoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCXds100UpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + <option> + <name>CCXDSTargetVccEnable</name> + <state>0</state> + </option> + <option> + <name>CCXDSTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>OCXDSDigitalStatesConfigFile</name> + <state>1</state> + </option> + <option> + <name>OCSelectedCoreName</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewp new file mode 100644 index 000000000..78820cddd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewp @@ -0,0 +1,1355 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>35</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>BrowseInfoPath</name> + <state>Debug/BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>$PROJ_DIR$/Debug</state> + </option> + <option> + <name>ObjPath</name> + <state>$PROJ_DIR$/Debug/Objects</state> + </option> + <option> + <name>ListPath</name> + <state>$PROJ_DIR$/Debug/Listings</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>No specifier a, A, no specifier n, no float nor long long, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>A compact configuration of the C/C++14 runtime library. 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<state>0</state> + </option> + <option> + <name>IlinkLogMerging</name> + <state>0</state> + </option> + <option> + <name>IlinkDemangle</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFileEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFile</name> + <state></state> + </option> + <option> + <name>IlinkProcessor</name> + <state>1</state> + </option> + <option> + <name>IlinkFpuProcessor</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + </configuration> + <group> + <name>Config</name> + <file> + <name>$PROJ_DIR$\..\Config\FreeRTOSConfig.h</name> + </file> + </group> + <group> + <name>Demos</name> + <group> + <name>mpu_demo</name> + <file> + <name>$PROJ_DIR$\..\..\..\Common\ARMv8M\mpu_demo\mpu_demo.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\Common\ARMv8M\mpu_demo\mpu_demo.h</name> + </file> + </group> + <group> + <name>reg_tests</name> + <file> + <name>$PROJ_DIR$\..\..\..\Common\ARMv8M\reg_tests\IAR\ARM_CM33\non_secure\reg_test_asm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\Common\ARMv8M\reg_tests\IAR\ARM_CM33\non_secure\reg_test_asm.s</name> + </file> + </group> + </group> + <group> + <name>FreeRTOS</name> + <group> + <name>Common</name> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\portable\Common\mpu_wrappers.c</name> + </file> + </group> + <group> + <name>MemMang</name> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\portable\MemMang\heap_4.c</name> + </file> + </group> + <group> + <name>portable</name> + <group> + <name>IAR</name> + <group> + <name>ARM_CM33_NTZ</name> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM33_NTZ\non_secure\port.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM33_NTZ\non_secure\portasm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM33_NTZ\non_secure\portasm.s</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM33_NTZ\non_secure\portmacro.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM33_NTZ\non_secure\portmacrocommon.h</name> + </file> + </group> + </group> + </group> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\event_groups.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\list.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\queue.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\stream_buffer.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\tasks.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\Source\timers.c</name> + </file> + </group> + <group> + <name>NXP_Code</name> + <group> + <name>board</name> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\board\board.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\board\board.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\board\clock_config.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\board\clock_config.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\board\pin_mux.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\board\pin_mux.h</name> + </file> + </group> + <group> + <name>CMSIS</name> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\CMSIS\cmsis_compiler.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\CMSIS\cmsis_gcc.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\CMSIS\cmsis_iccarm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\CMSIS\cmsis_version.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\CMSIS\core_cm33.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\CMSIS\mpu_armv8.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\CMSIS\tz_context.h</name> + </file> + </group> + <group> + <name>component</name> + <group> + <name>lists</name> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\component\lists\fsl_component_generic_list.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\component\lists\fsl_component_generic_list.h</name> + </file> + </group> + <group> + <name>uart</name> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\component\uart\fsl_adapter_uart.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\component\uart\fsl_adapter_usart.c</name> + </file> + </group> + </group> + <group> + <name>device</name> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\device\fsl_device_registers.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\device\LPC55S69_cm33_core0.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\device\LPC55S69_cm33_core0_features.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\device\system_LPC55S69_cm33_core0.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\device\system_LPC55S69_cm33_core0.h</name> + </file> + </group> + <group> + <name>drivers</name> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_clock.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_clock.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_common.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_common.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_common_arm.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_common_arm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_flexcomm.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_flexcomm.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_gpio.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_gpio.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_iocon.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_power.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_power.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_reset.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_reset.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_usart.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\drivers\fsl_usart.h</name> + </file> + </group> + <group> + <name>startup</name> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\startup\startup_LPC55S69_cm33_core0.s</name> + </file> + </group> + <group> + <name>utilities</name> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\utilities\fsl_assert.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\utilities\fsl_debug_console.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\utilities\fsl_debug_console.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\utilities\fsl_str.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\NXP_Code\utilities\fsl_str.h</name> + </file> + </group> + </group> + <group> + <name>RegTests</name> + <file> + <name>$PROJ_DIR$\..\..\RegTests\reg_tests.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\RegTests\reg_tests.h</name> + </file> + </group> + <group> + <name>User</name> + <file> + <name>$PROJ_DIR$\fault_handler.s</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\User\NTZ\main.c</name> + </file> + </group> +</project> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.eww b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.eww new file mode 100644 index 000000000..118c86d5e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.eww @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="iso-8859-1"?> +<workspace> + <batchBuild> + <batchDefinition> + <name>all</name> + <member> + <project>FreeRTOSDemo</project> + <configuration>debug</configuration> + </member> + </batchDefinition> + </batchBuild> + <project> + <path>$WS_DIR$/FreeRTOSDemo.ewp</path> + </project> +</workspace> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo_flash.icf b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo_flash.icf new file mode 100644 index 000000000..a00ba246b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo_flash.icf @@ -0,0 +1,144 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_privileged_text_start = 0x10000000; +define symbol m_privileged_text_end = 0x10007FFF; + +define symbol m_syscalls_text_start = 0x10008000; +define symbol m_syscalls_text_end = 0x1000FFFF; + +define symbol m_unprivileged_text_start = 0x10010000; +define symbol m_unprivileged_text_end = 0x10071FFF; + +define exported symbol core1_image_start = 0x10072000; +define exported symbol core1_image_end = 0x1009D7FF; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_privileged_data_start = 0x30000000; + define symbol m_privileged_data_end = 0x3000FFFF; + + define symbol m_unprivileged_data_start = 0x30010000; + define symbol m_unprivileged_data_end = 0x30030FFF; + + define exported symbol rpmsg_sh_mem_start = 0x30031800; + define exported symbol rpmsg_sh_mem_end = 0x30032FFF; +} else { + define symbol m_privileged_data_start = 0x30000000; + define symbol m_privileged_data_end = 0x3000FFFF; + + define symbol m_unprivileged_data_start = 0x30010000; + define symbol m_unprivileged_data_end = 0x30032FFF; +} + +define symbol m_usb_sram_start = 0x50100000; +define symbol m_usb_sram_end = 0x50103FFF; + +define memory mem with size = 4G; + +define region TEXT_privileged_region = mem:[from m_privileged_text_start to m_privileged_text_end]; +define region TEXT_syscalls_region = mem:[from m_syscalls_text_start to m_syscalls_text_end]; +define region TEXT_unprivileged_region = mem:[from m_unprivileged_text_start to m_unprivileged_text_end]; + + +define region DATA_privileged_region = mem:[from m_privileged_data_start to m_privileged_data_end]; +define region DATA_unprivileged_region = mem:[from m_unprivileged_data_start to m_unprivileged_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_unprivileged_data_end-__size_cstack__+1 to m_unprivileged_data_end]; + +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block CORE1_IMAGE_WBLOCK { section __core1_image }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +/* Exported symbols. */ +define exported symbol __privileged_functions_start__ = m_privileged_text_start; +define exported symbol __privileged_functions_end__ = m_privileged_text_end; +define exported symbol __syscalls_flash_start__ = m_syscalls_text_start; +define exported symbol __syscalls_flash_end__ = m_syscalls_text_end; +define exported symbol __unprivileged_flash_start__ = m_unprivileged_text_start; +define exported symbol __unprivileged_flash_end__ = m_unprivileged_text_end; +define exported symbol __privileged_sram_start__ = m_privileged_data_start; +define exported symbol __privileged_sram_end__ = m_privileged_data_end; + +/* Placements. */ +place at address mem: m_privileged_text_start { readonly section .intvec }; + +place in TEXT_privileged_region { readonly section privileged_functions }; +place in TEXT_syscalls_region { readonly section freertos_system_calls }; +place in TEXT_unprivileged_region { readonly }; + +place in DATA_privileged_region { readwrite section privileged_data }; +place in DATA_unprivileged_region { block RW }; +place in DATA_unprivileged_region { block ZI }; +place in DATA_unprivileged_region { last block HEAP }; + +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block CORE1_IMAGE_WBLOCK }; + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/fault_handler.s b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/fault_handler.s new file mode 100644 index 000000000..70cba7358 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/fault_handler.s @@ -0,0 +1,42 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + EXTERN vHandleMemoryFault + PUBLIC MemManage_Handler + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +MemManage_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vHandleMemoryFault +/*-----------------------------------------------------------*/ + + END diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/.cproject b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/.cproject new file mode 100644 index 000000000..6527228ac --- /dev/null +++ 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b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/Config/FreeRTOSConfig.h @@ -0,0 +1,168 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/****************************************************************************** + See http://www.freertos.org/a00110.html for an explanation of the + definitions contained in this file. +******************************************************************************/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * https://www.FreeRTOS.org/a00110.html + *----------------------------------------------------------*/ + +#include "clock_config.h" + +/* Cortex M33 port configuration. */ +#define configENABLE_MPU 1 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configRUN_FREERTOS_SECURE_ONLY 1 + +/* Constants related to the behaviour or the scheduler. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 1 +#define configMAX_PRIORITIES ( 5 ) +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */ + +/* Constants that describe the hardware and memory usage. */ +#define configCPU_CLOCK_HZ BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK +#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 ) +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) ) + +/* Constants that build features in or out. */ +#define configUSE_MUTEXES 1 +#define configUSE_TICKLESS_IDLE 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_TRACE_FACILITY 1 + +/* Constants that define which hook (callback) functions should be used. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 + +/* Constants provided for debugging and optimisation assistance. */ +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } +#define configQUEUE_REGISTRY_SIZE 0 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 3 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is + * only necessary if the linker does not automatically remove functions that are + * not referenced anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xSemaphoreGetMutexHolder 0 +#define INCLUDE_xTimerPendFunctionCall 1 + +/* This demo makes use of one or more example stats formatting functions. These + * format the raw data provided by the uxTaskGetSystemState() function in to + * human readable ASCII form. See the notes in the implementation of vTaskList() + * within FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter. + * See the FreeRTOS+CLI documentation for more information: + * https://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048 + +/* Interrupt priority configuration follows...................... */ + +/* Use the system definition, if there is one. */ +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 8 priority levels. */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" + * function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 + +/* The highest interrupt priority that can be used by any interrupt service + * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT + * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A + * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic + * to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) + +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) + +/* The #ifdef guards against the file being included from IAR assembly files. */ +#ifndef __IASMARM__ + + /* Constants related to the generation of run time stats. */ + #define configGENERATE_RUN_TIME_STATS 0 + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() + #define portGET_RUN_TIME_COUNTER_VALUE() 0 + #define configTICK_RATE_HZ ( ( TickType_t ) 100 ) + +#endif /* __IASMARM__ */ + +/* Enable static allocation. */ +#define configSUPPORT_STATIC_ALLOCATION 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FaultHandler/fault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FaultHandler/fault_handler.c new file mode 100644 index 000000000..0a6d1b9ab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FaultHandler/fault_handler.c @@ -0,0 +1,50 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @brief The mem fault handler. + * + * It calls a function called vHandleMemoryFault. + */ +void MemManage_Handler( void ) __attribute__ ( ( naked ) ); +/*-----------------------------------------------------------*/ + +void MemManage_Handler( void ) /* __attribute__ ( ( naked ) ) */ +{ + __asm volatile + ( + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, handler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + " handler_address_const: .word vHandleMemoryFault \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FreeRTOSDemo.ld b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FreeRTOSDemo.ld new file mode 100644 index 000000000..1fc09ff1a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FreeRTOSDemo.ld @@ -0,0 +1,213 @@ +GROUP ( + "libgcc.a" + "libc_nano.a" + "libm.a" + "libcr_newlib_semihost.a" +) + +MEMORY +{ + /* Define each memory region. */ + PROGRAM_FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x82000 + Ram0 (rwx) : ORIGIN = 0x30000000, LENGTH = 0x33000 +} + +/* Define a symbol for the top of each memory region. */ +__base_PROGRAM_FLASH = 0x10000000; /* PROGRAM_FLASH. */ +__base_Flash = 0x10000000; /* Flash. */ +__top_PROGRAM_FLASH = 0x10000000 + 0x82000; +__top_Flash = 0x10000000 + 0x82000; + +__base_Ram0 = 0x30000000; /* Ram0. */ +__base_RAM = 0x30000000; /* RAM. */ +__top_Ram0 = 0x30000000 + 0x33000; +__top_RAM = 0x30000000 + 0x33000; + +/* Entry point. */ +ENTRY(ResetISR) + +SECTIONS +{ + /* Vector Table Section. */ + .text : ALIGN(4) + { + FILL(0xff) + __vectors_start__ = ABSOLUTE(.); + KEEP(*(.isr_vector)) + + /* Global Section Table. */ + . = ALIGN(4); + __section_table_start = .; + + __data_section_table = .; + LONG(LOADADDR(.data)); + LONG( ADDR(.data)); + LONG( SIZEOF(.data)); + __data_section_table_end = .; + + __bss_section_table = .; + LONG( ADDR(.bss)); + LONG( SIZEOF(.bss)); + __bss_section_table_end = .; + + __section_table_end = .; + /* End of Global Section Table. */ + + *(.after_vectors*) + } > PROGRAM_FLASH + + /* Privileged functions - Section needs to be 32 byte aligned to satisfy MPU requirements. */ + .privileged_functions : ALIGN(32) + { + . = ALIGN(32); + __privileged_functions_start__ = .; + *(privileged_functions) + . = ALIGN(32); + /* End address must be the last address in the region, therefore, -1. */ + __privileged_functions_end__ = . - 1; + } > PROGRAM_FLASH + + /* FreeRTOS System calls - Section needs to be 32 byte aligned to satisfy MPU requirements. */ + .freertos_system_calls : ALIGN(32) + { + . = ALIGN(32); + __syscalls_flash_start__ = .; + *(freertos_system_calls) + . = ALIGN(32); + /* End address must be the last address in the region, therefore, -1. */ + __syscalls_flash_end__ = . - 1; + } > PROGRAM_FLASH + + /* Main Text Section - Section needs to be 32 byte aligned to satisfy MPU requirements. */ + .text : ALIGN(32) + { + . = ALIGN(32); + __unprivileged_flash_start__ = .; + *(.text*) + *(.rodata .rodata.* .constdata .constdata.*) + . = ALIGN(32); + /* End address must be the last address in the region, therefore, -1. */ + __unprivileged_flash_end__ = . - 1; + } > PROGRAM_FLASH + + /* For exception handling/unwind - some Newlib functions (in common + * with C++ and StdC++) use this. */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > PROGRAM_FLASH + + .ARM.exidx : ALIGN(4) + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > PROGRAM_FLASH + + /* Text Section End. */ + _etext = .; + + /* Uninit Reserved Section. */ + .uninit_RESERVED : ALIGN(4) + { + KEEP(*(.bss.$RESERVED*)) + . = ALIGN(4); + _end_uninit_RESERVED = .; + } > Ram0 + + /* Main Data section (Ram0). */ + .data : ALIGN(4) + { + FILL(0xff) + _data = .; + PROVIDE(__start_data_RAM = .); + PROVIDE(__start_data_Ram0 = .); + + /* Privileged data - It needs to be 32 byte aligned to satisfy MPU requirements. */ + . = ALIGN(32); + __privileged_sram_start__ = .; + *(privileged_data) + . = ALIGN(32); + /* End address must be the last address in the region, therefore, -1. */ + __privileged_sram_end__ = . - 1; + + *(vtable) + *(.ramfunc*) + *(.data*) + _edata = .; + PROVIDE(__end_data_RAM = .); + PROVIDE(__end_data_Ram0 = .); + } > Ram0 AT>PROGRAM_FLASH + + /* Main BSS Section. */ + .bss : ALIGN(4) + { + _bss = .; + PROVIDE(__start_bss_RAM = .); + PROVIDE(__start_bss_Ram0 = .); + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + PROVIDE(__end_bss_RAM = .); + PROVIDE(__end_bss_Ram0 = .); + PROVIDE(end = .); + } > Ram0 AT>Ram0 + + /* Default Noinit Section. */ + .noinit (NOLOAD) : ALIGN(4) + { + _noinit = .; + PROVIDE(__start_noinit_RAM = .); + PROVIDE(__start_noinit_Ram0 = .); + *(.noinit*) + . = ALIGN(4); + _end_noinit = .; + PROVIDE(__end_noinit_RAM = .); + PROVIDE(__end_noinit_Ram0 = .); + } > Ram0 AT>Ram0 + + /* Reserve space and place heap in memory map. */ + _HeapSize = 0x1000; + .heap : ALIGN(4) + { + _pvHeapStart = .; + . += _HeapSize; + . = ALIGN(4); + _pvHeapLimit = .; + } > Ram0 + + /* Reserve space for stack in memory. */ + _StackSize = 0x1000; + .heap2stackfill : + { + . += _StackSize; + } > Ram0 + + /* Place actual stack in memory map. */ + .stack ORIGIN(Ram0) + LENGTH(Ram0) - _StackSize - 0 : ALIGN(4) + { + _vStackBase = .; + . = ALIGN(4); + _vStackTop = . + _StackSize; + } > Ram0 + + /* Create checksum value (used in startup). */ + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined. */ + + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined. */ + + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined. */ + ) ); + + /* Provide basic symbols giving location and size of main text block, + * including initial values of RW data sections. Note that these will need + * extending to give a complete picture with complex images + * (e.g multiple Flash banks). */ + _image_start = LOADADDR(.text); + _image_end = LOADADDR(.data) + SIZEOF(.data); + _image_size = _image_end - _image_start; +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.c index 831ec6479..1492dfea9 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.c @@ -31,10 +31,13 @@ /* Reg test includes. */ #include "reg_tests.h" #include "reg_test_asm.h" -#include "secure_reg_test_asm.h" -/* Printf includes. */ -#include "nsc_printf.h" +#if( configENABLE_TRUSTZONE == 1 ) + #include "secure_reg_test_asm.h" + #include "nsc_printf.h" +#else + #include "fsl_debug_console.h" +#endif /* * Functions that implement reg test tasks. @@ -43,8 +46,11 @@ static void prvRegTest1_Task( void * pvParameters ); static void prvRegTest2_Task( void * pvParameters ); static void prvRegTest3_Task( void * pvParameters ); static void prvRegTest4_Task( void * pvParameters ); -static void prvRegTest_Secure_Task( void * pvParameters ); -static void prvRegTest_NonSecureCallback_Task( void * pvParameters ); +#if( configENABLE_TRUSTZONE == 1 ) + static void prvRegTest_Secure_Task( void * pvParameters ); + static void prvRegTest_NonSecureCallback_Task( void * pvParameters ); +#endif + /* * Check task periodically checks that reg tests tasks * are running fine. @@ -82,8 +88,10 @@ static void prvCheckTask( void * pvParameters ); */ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; volatile unsigned long ulRegTest3LoopCounter = 0UL, ulRegTest4LoopCounter = 0UL; -volatile unsigned long ulRegTestSecureLoopCounter = 0UL; -volatile unsigned long ulRegTestNonSecureCallbackLoopCounter = 0UL; +#if( configENABLE_TRUSTZONE == 1 ) + volatile unsigned long ulRegTestSecureLoopCounter = 0UL; + volatile unsigned long ulRegTestNonSecureCallbackLoopCounter = 0UL; +#endif /** * Counter to keep a count of how may times the check task loop has detected @@ -98,9 +106,11 @@ static StackType_t xRegTest1TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( static StackType_t xRegTest2TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); static StackType_t xRegTest3TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); static StackType_t xRegTest4TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); -static StackType_t xRegTestSecureTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); -static StackType_t xRegTestNonSecureCallbackTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); static StackType_t xCheckTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); +#if( configENABLE_TRUSTZONE == 1 ) + static StackType_t xRegTestSecureTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); + static StackType_t xRegTestNonSecureCallbackTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); +#endif TaskParameters_t xRegTest1TaskParameters = { @@ -158,35 +168,6 @@ TaskParameters_t xRegTest4TaskParameters = { 0, 0, 0 } } }; -TaskParameters_t xRegTestSecureTaskParameters = -{ - .pvTaskCode = prvRegTest_Secure_Task, - .pcName = "RegTestSecure", - .usStackDepth = configMINIMAL_STACK_SIZE, - .pvParameters = REG_TEST_SECURE_TASK_PARAMETER, - .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT, - .puxStackBuffer = xRegTestSecureTaskStack, - .xRegions = { - { 0, 0, 0 }, - { 0, 0, 0 }, - { 0, 0, 0 } - } -}; -TaskParameters_t xRegTestNonSecureCallbackTaskParameters = -{ - .pvTaskCode = prvRegTest_NonSecureCallback_Task, - .pcName = "RegTestNonSecureCallback", - .usStackDepth = configMINIMAL_STACK_SIZE, - .pvParameters = REG_TEST_NON_SECURE_CALLBACK_TASK_PARAMETER, - .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT, - .puxStackBuffer = xRegTestNonSecureCallbackTaskStack, - .xRegions = { - { 0, 0, 0 }, - { 0, 0, 0 }, - { 0, 0, 0 } - } -}; - TaskParameters_t xCheckTaskParameters = { .pvTaskCode = prvCheckTask, @@ -202,13 +183,49 @@ TaskParameters_t xCheckTaskParameters = } }; +#if( configENABLE_TRUSTZONE == 1 ) + + TaskParameters_t xRegTestSecureTaskParameters = + { + .pvTaskCode = prvRegTest_Secure_Task, + .pcName = "RegTestSecure", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = REG_TEST_SECURE_TASK_PARAMETER, + .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT, + .puxStackBuffer = xRegTestSecureTaskStack, + .xRegions = { + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 } + } + }; + TaskParameters_t xRegTestNonSecureCallbackTaskParameters = + { + .pvTaskCode = prvRegTest_NonSecureCallback_Task, + .pcName = "RegTestNonSecureCallback", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = REG_TEST_NON_SECURE_CALLBACK_TASK_PARAMETER, + .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT, + .puxStackBuffer = xRegTestNonSecureCallbackTaskStack, + .xRegions = { + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 } + } + }; + +#endif /* configENABLE_TRUSTZONE */ + xTaskCreateRestricted( &( xRegTest1TaskParameters ), NULL ); xTaskCreateRestricted( &( xRegTest2TaskParameters ), NULL ); xTaskCreateRestricted( &( xRegTest3TaskParameters ), NULL ); xTaskCreateRestricted( &( xRegTest4TaskParameters ), NULL ); - xTaskCreateRestricted( &( xRegTestSecureTaskParameters ), NULL ); - xTaskCreateRestricted( &( xRegTestNonSecureCallbackTaskParameters ), NULL ); xTaskCreateRestricted( &( xCheckTaskParameters ), NULL ); + #if( configENABLE_TRUSTZONE == 1 ) + xTaskCreateRestricted( &( xRegTestSecureTaskParameters ), NULL ); + xTaskCreateRestricted( &( xRegTestNonSecureCallbackTaskParameters ), NULL ); + #endif + } /*-----------------------------------------------------------*/ @@ -288,6 +305,8 @@ static void prvRegTest4_Task( void * pvParameters ) } /*-----------------------------------------------------------*/ +#if( configENABLE_TRUSTZONE == 1 ) + static void prvRegTest_Secure_Task( void * pvParameters ) { /* This task is going to call secure side functions. */ @@ -318,8 +337,12 @@ static void prvRegTest_Secure_Task( void * pvParameters ) * an error. */ vTaskDelete( NULL ); } + +#endif /* configENABLE_TRUSTZONE */ /*-----------------------------------------------------------*/ +#if( configENABLE_TRUSTZONE == 1 ) + static void prvRegTest_NonSecureCallback_Task( void * pvParameters ) { /* This task is going to call secure side functions. */ @@ -351,6 +374,8 @@ static void prvRegTest_NonSecureCallback_Task( void * pvParameters ) * an error. */ vTaskDelete( NULL ); } + +#endif /* configENABLE_TRUSTZONE */ /*-----------------------------------------------------------*/ static void prvCheckTask( void * pvParameters ) @@ -360,11 +385,14 @@ TickType_t xLastExecutionTime; unsigned long ulErrorFound = pdFALSE; static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; static unsigned long ulLastRegTest3Value = 0, ulLastRegTest4Value = 0; -static unsigned long ulLastRegTestSecureValue = 0, ulLastRegTestNonSecureCallbackValue = 0; + +#if( configENABLE_TRUSTZONE == 1 ) + static unsigned long ulLastRegTestSecureValue = 0, ulLastRegTestNonSecureCallbackValue = 0; /* This task is going to call secure side functions for * printing messages. */ portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE ); +#endif /* Just to stop compiler warnings. */ ( void ) pvParameters; @@ -412,34 +440,46 @@ static unsigned long ulLastRegTestSecureValue = 0, ulLastRegTestNonSecureCallbac } ulLastRegTest4Value = ulRegTest4LoopCounter; - /* Check that the register test secure task is still running. */ - if( ulLastRegTestSecureValue == ulRegTestSecureLoopCounter ) - { - ulErrorFound |= 1UL << 4UL; - } - ulLastRegTestSecureValue = ulRegTestSecureLoopCounter; - - /* Check that the register test non-secure callback task is - * still running. */ - if( ulLastRegTestNonSecureCallbackValue == ulRegTestNonSecureCallbackLoopCounter ) + #if( configENABLE_TRUSTZONE == 1 ) { - ulErrorFound |= 1UL << 5UL; + /* Check that the register test secure task is still running. */ + if( ulLastRegTestSecureValue == ulRegTestSecureLoopCounter ) + { + ulErrorFound |= 1UL << 4UL; + } + ulLastRegTestSecureValue = ulRegTestSecureLoopCounter; + + /* Check that the register test non-secure callback task is + * still running. */ + if( ulLastRegTestNonSecureCallbackValue == ulRegTestNonSecureCallbackLoopCounter ) + { + ulErrorFound |= 1UL << 5UL; + } + ulLastRegTestNonSecureCallbackValue = ulRegTestNonSecureCallbackLoopCounter; } - ulLastRegTestNonSecureCallbackValue = ulRegTestNonSecureCallbackLoopCounter; + #endif /* configENABLE_TRUSTZONE */ if( ulErrorFound != pdFALSE ) { /* An error has been detected in one of the tasks. */ xDelayPeriod = ERROR_CHECK_TASK_PERIOD; - NSC_Printf( "ERROR detected!\r\n" ); + #if( configENABLE_TRUSTZONE == 1 ) + NSC_Printf( "ERROR detected!\r\n" ); + #else + PRINTF( "ERROR detected!\r\n" ); + #endif /* Increment error detection count. */ ulCheckTaskLoops++; } else { - NSC_Printf( "No errors.\r\n" ); + #if( configENABLE_TRUSTZONE == 1 ) + NSC_Printf( "No errors.\r\n" ); + #else + PRINTF( "No errors.\r\n" ); + #endif } } } diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.h index 0837aad72..0837aad72 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.h diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NTZ/main.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NTZ/main.c new file mode 100644 index 000000000..340418c00 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NTZ/main.c @@ -0,0 +1,161 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Device includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "board.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "fsl_power.h" + +/* Demo includes. */ +#include "mpu_demo.h" +#include "reg_tests.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Create all demo tasks. + */ +static void prvCreateTasks( void ); + +/** + * @brief Setup hardware. + */ +static void prvSetupHardware( void ); +/*-----------------------------------------------------------*/ + +int main(void) +{ + /* Setup hardware. */ + prvSetupHardware(); + + /* Create tasks. */ + prvCreateTasks(); + + /* Start scheduler. */ + vTaskStartScheduler(); + + /* Will not get here if the scheduler starts successfully. If you do end up + * here then there wasn't enough heap memory available to start either the idle + * task or the timer/daemon task. https://www.freertos.org/a00111.html */ + for( ; ; ) + { + /* Should not reach here. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvCreateTasks( void ) +{ + /* Create tasks for the MPU Demo. */ + vStartMPUDemo(); + + /* Create tasks for reg tests. */ + vStartRegTests(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Set BOD VBAT level to 1.65V. */ + POWER_SetBodVbatLevel( kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false ); + + /* Attach main clock divide to FLEXCOMM0 (debug console). */ + CLOCK_AttachClk( BOARD_DEBUG_UART_CLK_ATTACH ); + + /* Init board hardware. */ + BOARD_InitPins(); + BOARD_BootClockFROHF96M(); + BOARD_InitDebugConsole(); +} +/*-----------------------------------------------------------*/ + +/* Stack overflow hook. */ +void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName ) +{ + /* Force an assert. */ + configASSERT( pcTaskName == 0 ); +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that + * is used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) +{ + /* If the buffers to be provided to the Idle task are declared inside this + * function then they must be declared static - otherwise they will be + * allocated on the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); + + /* Pass out a pointer to the StaticTask_t structure in which the Idle + * task's state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) +{ + /* If the buffers to be provided to the Timer task are declared inside this + * function then they must be declared static - otherwise they will be + * allocated on the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__( ( aligned( 32 ) ) ); + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NonSecure/main_ns.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NonSecure/main_ns.c new file mode 100644 index 000000000..532355c97 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NonSecure/main_ns.c @@ -0,0 +1,173 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS include. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Device includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "board.h" +#include "clock_config.h" +#include "fsl_power.h" + +/* Demo includes. */ +#include "tz_demo.h" +#include "mpu_demo.h" +#include "reg_tests.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Create all demo tasks. + */ +static void prvCreateTasks( void ); + +/** + * @brief Setup hardware. + */ +static void prvSetupHardware( void ); + +/** + * @brief Application-specific implementation of the SystemInit() weak + * function. + */ +void SystemInit( void ); +/*-----------------------------------------------------------*/ + +/* For instructions on how to build and run this demo, visit the following link: + * https://www.freertos.org/RTOS-Cortex-M33-LPC55S69-MCUXpresso-GCC.html + */ + +/* Non-Secure main. */ +int main( void ) +{ + /* Setup hardware. */ + prvSetupHardware(); + + /* Create tasks. */ + prvCreateTasks(); + + /* Start scheduler. */ + vTaskStartScheduler(); + + /* Will not get here if the scheduler starts successfully. If you do end up + * here then there wasn't enough heap memory available to start either the idle + * task or the timer/daemon task. https://www.freertos.org/a00111.html */ + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +static void prvCreateTasks( void ) +{ + /* Create tasks for the MPU Demo. */ + vStartMPUDemo(); + + /* Create tasks for the TZ Demo. */ + vStartTZDemo(); + + /* Create tasks for reg tests. */ + vStartRegTests(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Set BOD VBAT level to 1.65V. */ + POWER_SetBodVbatLevel( kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false ); +} +/*-----------------------------------------------------------*/ + +void SystemInit( void ) +{ + /* Nothing needs to be initialized for Non-Secure project. */ +} +/*-----------------------------------------------------------*/ + +/* Stack overflow hook. */ +void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName ) +{ + /* Force an assert. */ + configASSERT( pcTaskName == 0 ); +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that + * is used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) +{ + /* If the buffers to be provided to the Idle task are declared inside this + * function then they must be declared static - otherwise they will be + * allocated on the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); + + /* Pass out a pointer to the StaticTask_t structure in which the Idle + * task's state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) +{ + /* If the buffers to be provided to the Timer task are declared inside this + * function then they must be declared static - otherwise they will be + * allocated on the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__( ( aligned( 32 ) ) ); + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/main_s.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/Secure/main_s.c index abe5b7d85..636b5b9f9 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/main_s.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/Secure/main_s.c @@ -1,131 +1,131 @@ -/*
- * FreeRTOS V202212.00
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* FreeRTOS includes. */
-#include "secure_port_macros.h"
-
-/* Device includes. */
-#include "fsl_device_registers.h"
-#include "fsl_debug_console.h"
-#include "arm_cmse.h"
-#include "board.h"
-#include "tzm_config.h"
-#include "pin_mux.h"
-#include "clock_config.h"
-#include "fsl_power.h"
-
-#if ( __ARM_FEATURE_CMSE & 1 ) == 0
- #error "Need ARMv8-M security extensions"
-#elif ( __ARM_FEATURE_CMSE & 2 ) == 0
- #error "Compile with --cmse"
-#endif
-
-/* Start address of non-secure application. */
-#define mainNONSECURE_APP_START_ADDRESS ( 0x00010000UL )
-
-/* typedef for non-secure Reset Handler. */
-typedef void ( *NonSecureResetHandler_t ) ( void ) __attribute__( ( cmse_nonsecure_call ) );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Boots into the non-secure code.
- *
- * @param[in] ulNonSecureStartAddress Start address of the non-secure application.
- */
-static void prvBootNonSecure( uint32_t ulNonSecureStartAddress );
-
-/**
- * @brief Application-specific implementation of the SystemInitHook() weak
- * function.
- */
-void SystemInitHook( void );
-/*-----------------------------------------------------------*/
-
-/* For instructions on how to build and run this demo, visit the following link:
- * https://www.freertos.org/RTOS-Cortex-M33-LPC55S69-MCUXpresso-GCC.html
- */
-
-/* Secure main(). */
-int main(void)
-{
- /* Set BOD VBAT level to 1.65V. */
- POWER_SetBodVbatLevel( kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false );
-
- /* Attach main clock divide to FLEXCOMM0 (debug console). */
- CLOCK_AttachClk( BOARD_DEBUG_UART_CLK_ATTACH );
-
- /* Init board hardware. */
- BOARD_InitPins();
- BOARD_BootClockFROHF96M();
- BOARD_InitDebugConsole();
-
- /* Boot the non-secure code. */
- PRINTF( "Booting Non-Secure World.\r\n" );
- prvBootNonSecure( mainNONSECURE_APP_START_ADDRESS );
-
- /* Non-secure software does not return, this code is not executed. */
- for( ; ; )
- {
- /* Should not reach here. */
- }
-}
-/*-----------------------------------------------------------*/
-
-static void prvBootNonSecure( uint32_t ulNonSecureStartAddress )
-{
- NonSecureResetHandler_t pxNonSecureResetHandler;
-
- /* Setup the non-secure vector table. */
- SCB_NS->VTOR = ulNonSecureStartAddress;
-
- /* Main Stack Pointer value for the non-secure side is the first entry in
- * the non-secure vector table. Read the first entry and assign the same to
- * the non-secure main stack pointer(MSP_NS). */
- secureportSET_MSP_NS( *( ( uint32_t * )( ulNonSecureStartAddress ) ) );
-
- /* Reset Handler for the non-secure side is the second entry in the
- * non-secure vector table. Read the second entry to get the non-secure
- * Reset Handler. */
- pxNonSecureResetHandler = ( NonSecureResetHandler_t )( * ( ( uint32_t * ) ( ( ulNonSecureStartAddress ) + 4U ) ) );
-
- /* Start non-secure state software application by jumping to the non-secure
- * Reset Handler. */
- pxNonSecureResetHandler();
-}
-/*-----------------------------------------------------------*/
-
-void SystemInitHook( void )
-{
- /* Set CP10 and CP11 full access from Non-Secure code. */
- SCB_NS->CPACR |= ( ( 3UL << 10 * 2 ) | ( 3UL << 11 * 2 ) );
-
- /* The TrustZone should be configured as early as possible after RESET.
- * Therefore it is called from SystemInit() during startup. The
- * SystemInitHook() weak function overloading is used for this purpose.
- */
- BOARD_InitTrustZone();
-}
-/*-----------------------------------------------------------*/
+/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "secure_port_macros.h" + +/* Device includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "arm_cmse.h" +#include "board.h" +#include "tzm_config.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "fsl_power.h" + +#if ( __ARM_FEATURE_CMSE & 1 ) == 0 + #error "Need ARMv8-M security extensions" +#elif ( __ARM_FEATURE_CMSE & 2 ) == 0 + #error "Compile with --cmse" +#endif + +/* Start address of non-secure application. */ +#define mainNONSECURE_APP_START_ADDRESS ( 0x00010000UL ) + +/* typedef for non-secure Reset Handler. */ +typedef void ( *NonSecureResetHandler_t ) ( void ) __attribute__( ( cmse_nonsecure_call ) ); +/*-----------------------------------------------------------*/ + +/** + * @brief Boots into the non-secure code. + * + * @param[in] ulNonSecureStartAddress Start address of the non-secure application. + */ +static void prvBootNonSecure( uint32_t ulNonSecureStartAddress ); + +/** + * @brief Application-specific implementation of the SystemInitHook() weak + * function. + */ +void SystemInitHook( void ); +/*-----------------------------------------------------------*/ + +/* For instructions on how to build and run this demo, visit the following link: + * https://www.freertos.org/RTOS-Cortex-M33-LPC55S69-MCUXpresso-GCC.html + */ + +/* Secure main(). */ +int main(void) +{ + /* Set BOD VBAT level to 1.65V. */ + POWER_SetBodVbatLevel( kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false ); + + /* Attach main clock divide to FLEXCOMM0 (debug console). */ + CLOCK_AttachClk( BOARD_DEBUG_UART_CLK_ATTACH ); + + /* Init board hardware. */ + BOARD_InitPins(); + BOARD_BootClockFROHF96M(); + BOARD_InitDebugConsole(); + + /* Boot the non-secure code. */ + PRINTF( "Booting Non-Secure World.\r\n" ); + prvBootNonSecure( mainNONSECURE_APP_START_ADDRESS ); + + /* Non-secure software does not return, this code is not executed. */ + for( ; ; ) + { + /* Should not reach here. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvBootNonSecure( uint32_t ulNonSecureStartAddress ) +{ + NonSecureResetHandler_t pxNonSecureResetHandler; + + /* Setup the non-secure vector table. */ + SCB_NS->VTOR = ulNonSecureStartAddress; + + /* Main Stack Pointer value for the non-secure side is the first entry in + * the non-secure vector table. Read the first entry and assign the same to + * the non-secure main stack pointer(MSP_NS). */ + secureportSET_MSP_NS( *( ( uint32_t * )( ulNonSecureStartAddress ) ) ); + + /* Reset Handler for the non-secure side is the second entry in the + * non-secure vector table. Read the second entry to get the non-secure + * Reset Handler. */ + pxNonSecureResetHandler = ( NonSecureResetHandler_t )( * ( ( uint32_t * ) ( ( ulNonSecureStartAddress ) + 4U ) ) ); + + /* Start non-secure state software application by jumping to the non-secure + * Reset Handler. */ + pxNonSecureResetHandler(); +} +/*-----------------------------------------------------------*/ + +void SystemInitHook( void ) +{ + /* Set CP10 and CP11 full access from Non-Secure code. */ + SCB_NS->CPACR |= ( ( 3UL << 10 * 2 ) | ( 3UL << 11 * 2 ) ); + + /* The TrustZone should be configured as early as possible after RESET. + * Therefore it is called from SystemInit() during startup. The + * SystemInitHook() weak function overloading is used for this purpose. + */ + BOARD_InitTrustZone(); +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.c b/FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.c index c6793ee53..c3b04b3d7 100644 --- a/FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.c +++ b/FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.c @@ -60,7 +60,7 @@ static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 * @note We are declaring a region of 32 bytes even though we need only one. The
* reason is that the size of an MPU region must be a multiple of 32 bytes.
*/
-static uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ) = { 0 };
+static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ) = { 0 };
/*-----------------------------------------------------------*/
/**
@@ -234,19 +234,19 @@ void vStartMPUDemo( void ) .puxStackBuffer = xROAccessTaskStack,
.xRegions =
{
- { ucSharedMemory, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
#if ( configTOTAL_MPU_REGIONS == 16 )
- { ucSharedMemory1, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory2, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory3, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory4, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory5, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory6, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory7, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory8, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory1, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory2, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory3, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory4, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory5, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory6, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory7, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory8, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },
#endif /* configTOTAL_MPU_REGIONS == 16 */
- { ucROTaskFaultTracker, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
- { 0, 0, 0 },
+ { ( void * ) ucROTaskFaultTracker, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
+ { 0, 0, 0 },
}
};
TaskParameters_t xRWAccessTaskParameters =
@@ -259,19 +259,19 @@ void vStartMPUDemo( void ) .puxStackBuffer = xRWAccessTaskStack,
.xRegions =
{
- { ucSharedMemory, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
#if ( configTOTAL_MPU_REGIONS == 16 )
- { ucSharedMemory1, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory2, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory3, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory4, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory5, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory6, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory7, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
- { ucSharedMemory8, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory1, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory2, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory3, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory4, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory5, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory6, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory7, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
+ { ( void * ) ucSharedMemory8, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },
#endif /* configTOTAL_MPU_REGIONS == 16 */
- { 0, 0, 0 },
- { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
}
};
diff --git a/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.h b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.h new file mode 100644 index 000000000..e6e7f57d3 --- /dev/null +++ b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.h @@ -0,0 +1,48 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef REG_TEST_ASM_H +#define REG_TEST_ASM_H + +/** + * @brief Functions that implement reg tests in assembly. + * + * These are called from the FreeRTOS tasks on the non-secure side. + */ +void vRegTest1Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest2Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest3Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest4Asm_NonSecure( void ) __attribute__( ( naked ) ); + +/** + * @brief Function that implements reg tests in assembly. + * + * This is passed as function pointer to the secure side and called + * from the secure side. + */ +void vRegTestAsm_NonSecureCallback( void ); + +#endif /* REG_TEST_ASM_H */ diff --git a/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.s b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.s new file mode 100644 index 000000000..8f46cf762 --- /dev/null +++ b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.s @@ -0,0 +1,1194 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * "Reg tests" - These tests fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + + EXTERN ulRegTest1LoopCounter + EXTERN ulRegTest2LoopCounter + EXTERN ulRegTest3LoopCounter + EXTERN ulRegTest4LoopCounter + + PUBLIC vRegTest1Asm_NonSecure + PUBLIC vRegTest2Asm_NonSecure + PUBLIC vRegTest3Asm_NonSecure + PUBLIC vRegTest4Asm_NonSecure + PUBLIC vRegTestAsm_NonSecureCallback + +/*-----------------------------------------------------------*/ + +vRegTest1Asm_NonSecure: + /* Fill the core registers with known values. */ + movs r0, #100 + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + /* Fill the FPU registers with known values. */ + vmov.f32 s1, #1.5 + vmov.f32 s2, #2.5 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.5 + vmov.f32 s5, #5.5 + vmov.f32 s6, #6.5 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.5 + vmov.f32 s9, #9.5 + vmov.f32 s10, #10.5 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.5 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.5 + vmov.f32 s15, #1.0 + vmov.f32 s16, #2.0 + vmov.f32 s17, #3.0 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.0 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.0 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.0 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.0 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.0 + vmov.f32 s28, #14.0 + vmov.f32 s29, #1.5 + vmov.f32 s30, #2.5 + vmov.f32 s31, #3.5 + + reg1_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + cmp r8, #108 + bne reg1_error_loop + cmp r9, #109 + bne reg1_error_loop + cmp r10, #110 + bne reg1_error_loop + cmp r11, #111 + bne reg1_error_loop + cmp r12, #112 + bne reg1_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s0, #1.5 /* s0 = 1.5. */ + vcmp.f32 s1, s0 /* Compare s0 and s1. */ + vmrs APSR_nzcv, FPSCR /* Copy floating point flags (FPSCR flags) to ASPR flags - needed for next bne to work. */ + bne reg1_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s2, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s3, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #4.5 + vcmp.f32 s4, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #5.5 + vcmp.f32 s5, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #6.5 + vcmp.f32 s6, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #7.5 + vcmp.f32 s7, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #8.5 + vcmp.f32 s8, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #9.5 + vcmp.f32 s9, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #10.5 + vcmp.f32 s10, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #11.5 + vcmp.f32 s11, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #12.5 + vcmp.f32 s12, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #13.5 + vcmp.f32 s13, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #14.5 + vcmp.f32 s14, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #1.0 + vcmp.f32 s15, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s16, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s17, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #4.0 + vcmp.f32 s18, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #5.0 + vcmp.f32 s19, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #6.0 + vcmp.f32 s20, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #7.0 + vcmp.f32 s21, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #8.0 + vcmp.f32 s22, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #9.0 + vcmp.f32 s23, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #10.0 + vcmp.f32 s24, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #11.0 + vcmp.f32 s25, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #12.0 + vcmp.f32 s26, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #13.0 + vcmp.f32 s27, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #14.0 + vcmp.f32 s28, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #1.5 + vcmp.f32 s29, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s30, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s31, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_ICSR. */ + lsls r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Start again. */ + b reg1_loop + + reg1_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg1_error_loop + nop + ltorg +/*-----------------------------------------------------------*/ + +vRegTest2Asm_NonSecure: + /* Fill the core registers with known values. */ + movs r0, #0 + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, #8 + mov r9, #9 + movs r10, #10 + movs r11, #11 + movs r12, #12 + + /* Fill the FPU registers with known values. */ + vmov.f32 s1, #1.0 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.0 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.0 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.0 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.0 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.5 + vmov.f32 s17, #3.5 + vmov.f32 s18, #4.5 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.5 + vmov.f32 s21, #7.5 + vmov.f32 s22, #8.5 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.5 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.5 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.5 + vmov.f32 s29, #1.0 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.0 + + reg2_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #0 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + cmp r8, #8 + bne reg2_error_loop + cmp r9, #9 + bne reg2_error_loop + cmp r10, #10 + bne reg2_error_loop + cmp r11, #11 + bne reg2_error_loop + cmp r12, #12 + bne reg2_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s0, #1.0 + vcmp.f32 s1, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s2, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s3, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #4.0 + vcmp.f32 s4, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #5.0 + vcmp.f32 s5, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #6.0 + vcmp.f32 s6, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #7.0 + vcmp.f32 s7, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #8.0 + vcmp.f32 s8, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #9.0 + vcmp.f32 s9, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #10.0 + vcmp.f32 s10, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #11.0 + vcmp.f32 s11, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #12.0 + vcmp.f32 s12, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #13.0 + vcmp.f32 s13, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #14.0 + vcmp.f32 s14, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #1.5 + vcmp.f32 s15, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s16, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s17, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #4.5 + vcmp.f32 s18, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #5.5 + vcmp.f32 s19, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #6.5 + vcmp.f32 s20, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #7.5 + vcmp.f32 s21, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #8.5 + vcmp.f32 s22, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #9.5 + vcmp.f32 s23, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #10.5 + vcmp.f32 s24, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #11.5 + vcmp.f32 s25, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #12.5 + vcmp.f32 s26, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #13.5 + vcmp.f32 s27, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #14.5 + vcmp.f32 s28, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #1.0 + vcmp.f32 s29, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s30, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s31, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0, r1 } + + /* Start again. */ + b reg2_loop + + reg2_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg2_error_loop + nop + ltorg +/*-----------------------------------------------------------*/ + +vRegTest3Asm_NonSecure: + /* Fill the core registers with known values. */ + movs r0, #100 + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + /* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.5 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.5 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.5 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.0 + vmov.f32 s17, #3.5 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.5 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.0 + vmov.f32 s29, #1.5 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.5 + + reg3_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #100 + bne reg3_error_loop + cmp r1, #101 + bne reg3_error_loop + cmp r2, #102 + bne reg3_error_loop + cmp r3, #103 + bne reg3_error_loop + cmp r4, #104 + bne reg3_error_loop + cmp r5, #105 + bne reg3_error_loop + cmp r6, #106 + bne reg3_error_loop + cmp r7, #107 + bne reg3_error_loop + cmp r8, #108 + bne reg3_error_loop + cmp r9, #109 + bne reg3_error_loop + cmp r10, #110 + bne reg3_error_loop + cmp r11, #111 + bne reg3_error_loop + cmp r12, #112 + bne reg3_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.5 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest3LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_ICSR. */ + lsls r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Start again. */ + b reg3_loop + + reg3_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg3_error_loop + nop + ltorg +/*-----------------------------------------------------------*/ + +vRegTest4Asm_NonSecure: + /* Fill the core registers with known values. */ + movs r0, #0 + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, #8 + mov r9, #9 + movs r10, #10 + movs r11, #11 + movs r12, #12 + + /* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.5 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.0 + vmov.f32 s4, #4.5 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.5 + vmov.f32 s11, #11.0 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.0 + vmov.f32 s16, #2.5 + vmov.f32 s17, #3.0 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.0 + vmov.f32 s22, #8.5 + vmov.f32 s23, #9.0 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.0 + vmov.f32 s28, #14.5 + vmov.f32 s29, #1.0 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.5 + + reg4_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #0 + bne reg4_error_loop + cmp r1, #1 + bne reg4_error_loop + cmp r2, #2 + bne reg4_error_loop + cmp r3, #3 + bne reg4_error_loop + cmp r4, #4 + bne reg4_error_loop + cmp r5, #5 + bne reg4_error_loop + cmp r6, #6 + bne reg4_error_loop + cmp r7, #7 + bne reg4_error_loop + cmp r8, #8 + bne reg4_error_loop + cmp r9, #9 + bne reg4_error_loop + cmp r10, #10 + bne reg4_error_loop + cmp r11, #11 + bne reg4_error_loop + cmp r12, #12 + bne reg4_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.5 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #4.5 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #5.0 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #9.0 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #10.5 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #11.0 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #1.0 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #2.5 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #7.0 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #8.5 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #9.0 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #13.0 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #14.5 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #1.0 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest4LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0, r1 } + + /* Start again. */ + b reg4_loop + + reg4_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg4_error_loop + nop + ltorg +/*-----------------------------------------------------------*/ + +vRegTestAsm_NonSecureCallback: + /* Store callee saved registers. */ + push { r4-r12 } + + /* Fill the core registers with known values. */ + movs r0, #150 + movs r1, #151 + movs r2, #152 + movs r3, #153 + movs r4, #154 + movs r5, #155 + movs r6, #156 + movs r7, #157 + movs r8, #158 + movs r9, #159 + movs r10, #160 + movs r11, #161 + movs r12, #162 + + /* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.0 + vmov.f32 s2, #2.5 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.5 + vmov.f32 s6, #6.5 + vmov.f32 s7, #7.0 + vmov.f32 s8, #8.5 + vmov.f32 s9, #9.5 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.5 + vmov.f32 s13, #13.0 + vmov.f32 s14, #14.5 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.0 + vmov.f32 s17, #3.5 + vmov.f32 s18, #4.5 + vmov.f32 s19, #5.0 + vmov.f32 s20, #6.5 + vmov.f32 s21, #7.5 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.5 + vmov.f32 s25, #11.0 + vmov.f32 s26, #12.5 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.0 + vmov.f32 s29, #1.5 + vmov.f32 s30, #2.5 + vmov.f32 s31, #3.0 + + /* Force a context switch by pending sv. */ + push { r0, r1 } + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_ICSR. */ + lsls r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Verify that core registers contain correct values. */ + cmp r0, #150 + bne reg_nscb_error_loop + cmp r1, #151 + bne reg_nscb_error_loop + cmp r2, #152 + bne reg_nscb_error_loop + cmp r3, #153 + bne reg_nscb_error_loop + cmp r4, #154 + bne reg_nscb_error_loop + cmp r5, #155 + bne reg_nscb_error_loop + cmp r6, #156 + bne reg_nscb_error_loop + cmp r7, #157 + bne reg_nscb_error_loop + cmp r8, #158 + bne reg_nscb_error_loop + cmp r9, #159 + bne reg_nscb_error_loop + cmp r10, #160 + bne reg_nscb_error_loop + cmp r11, #161 + bne reg_nscb_error_loop + cmp r12, #162 + bne reg_nscb_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.0 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #2.5 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #6.5 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #7.0 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #8.5 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #12.5 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #13.0 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #14.5 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #4.5 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #5.0 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #6.5 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #10.5 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #11.0 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #12.5 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #2.5 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + + /* Everything passed, finish. */ + b reg_nscb_success + + reg_nscb_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg_nscb_error_loop + nop + + reg_nscb_success: + /* Restore callee saved registers. */ + pop { r4-r12 } + bx lr + ltorg +/*-----------------------------------------------------------*/ + + END diff --git a/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test.c b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test.c new file mode 100644 index 000000000..cbef60113 --- /dev/null +++ b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test.c @@ -0,0 +1,61 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include <stdint.h> +#include <arm_cmse.h> + +/* Interface includes. */ +#include "secure_reg_test_asm.h" + +/* FreeRTOS includes. */ +#include "secure_port_macros.h" + +/* Implemented in assembly. */ +extern void vRegTestAsm_SecureImpl( void ); + +/* typedef for non-secure callback function. */ +typedef __cmse_nonsecure_call void ( * NonSecureRegTestCallback_t ) ( void ); +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void vRegTestAsm_Secure( void ) +{ + /* Call the function implemented in assembly. */ + vRegTestAsm_SecureImpl(); +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback ) +{ + NonSecureRegTestCallback_t pxNonSecureRegTestCallback; + + /* Return function pointer with cleared LSB. */ + pxNonSecureRegTestCallback = ( NonSecureRegTestCallback_t ) cmse_nsfptr_create( pxRegTestCallback ); + + /* Invoke the callback which runs reg tests. */ + pxNonSecureRegTestCallback(); +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.h b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.h new file mode 100644 index 000000000..3b59c88d2 --- /dev/null +++ b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.h @@ -0,0 +1,49 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SECURE_REG_TEST_ASM_H +#define SECURE_REG_TEST_ASM_H + +/* Callback function pointer definition. */ +typedef void ( * RegTestCallback_t )( void ); + +/** + * @brief Function that implements reg tests for the secure side. + * + * This function is exported as "non-secure callable" and is called + * from a FreeRTOS task on the non-secure side. + */ +void vRegTestAsm_Secure( void ); + +/** + * @brief Invokes the supplied reg test callback on the non-secure side. + * + * This function is exported as "non-secure callable" and is called + * from a FreeRTOS task on the non-secure side.. + */ +void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback ); + +#endif /* SECURE_REG_TEST_ASM_H */ diff --git a/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.s b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.s new file mode 100644 index 000000000..a6f5d5823 --- /dev/null +++ b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.s @@ -0,0 +1,265 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + + PUBLIC vRegTestAsm_SecureImpl +/*-----------------------------------------------------------*/ + +vRegTestAsm_SecureImpl: + /* Store callee saved registers. */ + push { r4-r12 } + + /* Fill the core registers with known values. */ + movs r0, #200 + movs r1, #201 + movs r1, #201 + movs r2, #202 + movs r3, #203 + movs r4, #204 + movs r5, #205 + movs r6, #206 + movs r7, #207 + movs r8, #208 + movs r9, #209 + movs r10, #210 + movs r11, #211 + movs r12, #212 + + /* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.0 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.5 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.5 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.5 + vmov.f32 s13, #13.0 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.5 + vmov.f32 s17, #3.0 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.5 + vmov.f32 s21, #7.0 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.5 + vmov.f32 s25, #11.0 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.5 + vmov.f32 s29, #1.0 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.5 + + /* Force a context switch by pending non-secure sv. */ + push { r0, r1 } + movs r0, #0x01 + ldr r1, =0xe002ed04 /* NVIC_ICSR_NS. */ + lsls r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Verify that core registers contain correct values. */ + cmp r0, #200 + bne secure_reg_test_error_loop + cmp r1, #201 + bne secure_reg_test_error_loop + cmp r2, #202 + bne secure_reg_test_error_loop + cmp r3, #203 + bne secure_reg_test_error_loop + cmp r4, #204 + bne secure_reg_test_error_loop + cmp r5, #205 + bne secure_reg_test_error_loop + cmp r6, #206 + bne secure_reg_test_error_loop + cmp r7, #207 + bne secure_reg_test_error_loop + cmp r8, #208 + bne secure_reg_test_error_loop + cmp r9, #209 + bne secure_reg_test_error_loop + cmp r10, #210 + bne secure_reg_test_error_loop + cmp r11, #211 + bne secure_reg_test_error_loop + cmp r12, #212 + bne secure_reg_test_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.0 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #4.5 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #5.0 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #8.5 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #9.0 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #12.5 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #13.0 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #2.5 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #6.5 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #7.0 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #10.5 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #11.0 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #14.5 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #1.0 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + + /* Everything passed, finish. */ + b secure_reg_test_success + + secure_reg_test_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b secure_reg_test_error_loop + nop + + secure_reg_test_success: + /* Restore callee saved registers. */ + pop { r4-r12 } + bx lr +/*-----------------------------------------------------------*/ + + END |