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* ODROID-N2L: N2L sys_led(red) sync to power_on/off.ckkim2022-10-111-0/+3
| | | | | Signed-off-by: ckkim <changkon12@gmail.com> Change-Id: I7c4b8bc88f3655bbf81686de01c8a75dc80cf936
* ODROID-N2:support splash screen on odroid-vu7cckkim2022-02-151-2/+5
| | | | | Signed-off-by: ckkim <changkon12@gmail.com> Change-Id: Ia0831c0bfdc38a4da69cef418ce880b502a78c9e
* ODROID-C4:Add amlogic i2c_bus_2 for odroid-vu7cckkim2022-02-151-0/+6
| | | | | Signed-off-by: ckkim <changkon12@gmail.com> Change-Id: I830ecb59a4b51ee02ce2e58845e4b42761cd6309
* Revert "ODROID-COMMON: Add selfinstall status at boot and scripts."travis/odroidn2-171travis/odroidc4-171g12_9.0.0_64_20210108g12_9.0.0_64_20201221Luke go2020-12-091-1/+0
| | | | | | This reverts commit I017f4b84881ebb0a3266b78f3636de81ae9f1ecc. Change-Id: I60b9c55be3bd42bf172e8448802c2afad07b7553
* BACKPORT: Change cec flag for active source changePortisch2020-05-031-1/+1
| | | | Change-Id: Ia89bfb292fab9981807e4a9c631b2cec7a562a3e
* BACKPORT: cec: wake up on CEC_OC_ROUTING_INFORMATIONPortisch2020-05-031-1/+24
| | | | Change-Id: Ia00c6fd0f3471b66f4370c7f2659900c94554b1e
* BACKPORT: g12a/b: CEC_OC_ACTIVE_SOURCE: ignore phy address if broadcastPortisch2020-05-032-4/+4
| | | | Change-Id: Ib4937aa2b02d25824faaff7770d515884632686c
* BACKPORT: pwr_ctrl: enable and fix IR remote wakeup for g12a/bPortisch2020-05-032-8/+6
| | | | Change-Id: I404a55bb7e09e1490772626cff7ff29ead2d64f5
* Fixup: ODROID-N2: spdif: Fix high output after shutdown Revert gpio handling ↵Portisch2020-03-121-17/+12
| | | | | | to Amlogic code style Change-Id: I1f8e19d4309e49638702493ccee8602b61457831
* hdmitx: correct vid pll div shift preset length [3/3]Hang Cheng2020-02-188-16/+16
| | | | | | | | | | | | | | | | | PD#SWPL-9589 Problem: shift preset length of vid pll div is wrong Solution: modify shift preset length of vid pll div Verify: gxl-p281 Change-Id: Ibac6efe889630d32c30219618daa1f4d994a67bf Signed-off-by: Hang Cheng <hang.cheng@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
* hdmitx: add dithering control [1/1]Zongdong Jiao2020-02-184-0/+66
| | | | | | | | | | | | | | | PD#OTT-4800 Problem: Lack dithering control Solution: Add dithering control Verify: G12/U212 Change-Id: I49aee092e2b0ac239266a2884632013a2f4e1f1a
* ODROID-N2: spdif: Fix high output after shutdownHyeonki Hong2020-02-131-3/+20
| | | | | | | | SPDIF output remained high-level when odroid was turned off using shutdown command. So, add code to set pin mode to input mode. Change-Id: I3bd5f064c008a4542bebb84e697e1e66519f0bf1 (cherry picked from commit 267c12cffd5a8828f330976424756facea549d03)
* g12a/g12b: scp_task: add enable/disable of 5V system powerPortisch2020-02-102-0/+10
| | | | Change-Id: I6ee95ee196daa02aa73a99ef9c024f0503152474
* g12a/g12b: Add IR power key mask handling through SCPI SCPI_CL_REMOTE_MASKPortisch2020-02-104-10/+20
| | | | Change-Id: I390fa07f8224860641a313a6a7adcb095b2ffcdd
* g12a/g12b: scp_remote: rename RC6 to RC6A and add RC6 ir protocolPortisch2020-02-102-24/+52
| | | | Change-Id: I812b186b13b619988b0c0731502d47f2b135c289
* g12a/g12b: scp_remote: tune RC5 bit detectionPortisch2020-02-102-8/+8
| | | | Change-Id: If55b8c6d4f7415af32e8aa784757b774ef7a3520
* g12a/g12b: scp_remote: add support for Samsung IR remotes Standard NEC use ↵Portisch2020-02-102-10/+10
| | | | | | 9000µs/4500µs sync pulse. Samsung use NEC protocol but with 4500µs/4500µs sync pulse. Change-Id: I84896234c4b8e786aedea98891f42879548ea0f3
* g12a/g12b: scp_remote: add register setup for software decodePortisch2020-02-102-0/+18
| | | | Change-Id: I225dffd860af8c6cb92f9179d5fb6cf6f7d045cc
* g12a/g12b: Add IR protocol handling through SCPIRay2020-02-104-26/+202
| | | | | | | SCPI_CL_IRPROTO Also add RC5, RC6, NEC_RC5_2in1, NEC_RC6_2in1 Change-Id: I1282ee47a37448c69c9e92ba1b2eb4d692e9c704
* gxb/gxl/gxm: enable CEC wakeup from power off statePortisch2020-02-102-2/+2
| | | | Change-Id: I1e79ef397bb544af125c42889fde5d248a7b8e4b
* gxb/gxl/gxm: prepare suspend parameter for LED controlPortisch2020-02-104-4/+4
| | | | Change-Id: I73512141b68410071ad886063097e14ebb07a444
* gxb/gxl/gxm: do not turn off hdmi power on suspendPortisch2020-02-104-4/+4
| | | | Change-Id: Id62166a7666c95b8675544b162b0bbc25ff22e92
* ODROID-C4: scp_task: add gpio wake-up functionJoy Cho2020-02-104-0/+301
| | | | Change-Id: Idaa9f5738b02d7815762aba6a1513fefcc4deda6
* CE: CEC: Add CECB as wakeup src powerRay2020-02-101-26/+24
| | | | Change-Id: Id8c2f640436b085c27477e7cdf396fc728aa924b
* ODROID-C4: scp_task: add to support Wake On Lan enableDongjin Kim2020-02-102-0/+18
| | | | Change-Id: Ie880f1bf14ab61581c069d573b338bbc541a669c
* vout: support vout2 command for viu2 display [1/1]Evoke Zhang2020-02-1027-311/+139
| | | | | | | | | | | | | | | | | | | PD#TV-5428 Problem: need viu2 display support Solution: add vout2 management you can use "vout2 output ${outputmode}" to enable vout2 display Verify: x301 Change-Id: Id47e430453ebdf7c32f41d271d6e926fd5cf0f6b Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com> Signed-off-by: Dongjin Kim <tobetter@gmail.com>
* ODROID-COMMON: bootm-fdt: change 'CONFIG_ODROID_N2' to 'CONFIG_ODROID_COMMON'Dongjin Kim2020-02-101-2/+2
| | | | | Change-Id: If235ecb6da599fdacf4ec4d71d1e4d16103d2f90 Signed-off-by: Dongjin Kim <tobetter@gmail.com>
* uboot: update ddr and emmc driver. [1/3]xiaobo gu2020-02-104-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 6a2a443 storage: mmc/nand: support support to read saved ddr parameter [1/1] cb80c6c uboot: emmc: setup emmc hs400 debug environment in uboot [1/1] 9927af4 ddr: timing:G12A/G12B/TL1/TM2 update LPDDR4_PHY_V_0_1_14 bl33 [2/3] c9dfa59 ddr: driver:G12A/G12B/TL1 update LPDDR4_PHY_V_0_1_13 bl33 [2/3] ac463ed ddr: timing:G12A/G12B/TL1_update_LPDDR4_PHY_V_0_1_12_bl33 [2/3] 3fead4a dram: scramble: update scramble key config [2/2] dram: scramble: update scramble key config [2/2] PD#SWPL-3152 Problem: can not configure non-sec memory scramble key in uboot Solution: add config interface in ddr function Verity: test pass on u200/w400/x301 Change-Id: Ie987ecc336483518913dc3cb850cbe04d348720e Signed-off-by: xiaobo gu <xiaobo.gu@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com> ddr: timing:G12A/G12B/TL1_update_LPDDR4_PHY_V_0_1_12_bl33 [2/3] PD#SWPL-5973 Problem: none Solution: DDR_DRIVER_VERSION "LPDDR4_PHY_V_0_1_12" 20190128 1 reduice funciton ddr_init_soc_calculate_impedence_ctrl code size 2 modify ddr4 DqDqsRcvCntrl register for swith to extend vref range improve vref training 3 adjust 16bit lpddr4 dfi mode register and DMC_DRAM_DFI_CTRL register for 16bit test 4 change ddr scramble to after exter_ddrtest 5 add amlogic vref correction function 6 combine g12 rev-a and rev-b 7 repair tl1 ddr3 autosize function 8 config cfg_ddr_dqs=5 improve rank switch speed 9 change ddr4 rtt_park to 0 for ddr4 dqs level will increase vddq power 10 add fail_pass_ddr test method 11 disable asr only apd after ddrtest 12 add ddr_fast_boot function 13 add lpddr4 fast boot vt function Verify: test pass at x301 Change-Id: I19c0100cd08990854ab1f006d5e7060e7c2cc1bf Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com> ddr: driver:G12A/G12B/TL1 update LPDDR4_PHY_V_0_1_13 bl33 [2/3] PD#SWPL-7341 Problem: none. Solution: DDR_DRIVER_VERSION "LPDDR4_PHY_V_0_1_13" 20190417 1 add ddr_fast_boot data sha2 checksum 2 repair ddr reinit training all use for auto frequency scan 3 adjust tl1 bl2 stack link 4 reparir cs0 4GB support ,limit ddr addtest <=3928M 5 change tl1 board id to ddr id Verify: test pass at x301 and u200. Change-Id: I582fc6b67d6b565ef260b9bc4c144425ece95cc4 Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com> ddr: timing:G12A/G12B/TL1/TM2 update LPDDR4_PHY_V_0_1_14 bl33 [2/3] PD#SWPL-7880 Problem: none. Solution: DDR_DRIVER_VERSION "LPDDR4_PHY_V_0_1_14" 20190426 1 add soc window vref offset function 2 add usb_download_full test function 3 repair lpddr4 CA delay offset function 4 repair suspend resume test command 5 2400 ddr4 change cl from 16 to 18. compatibility new JEDEC 6 add dfi_mrl max value limmit 7 change lpddr4 init soc vref value Verify: test pass at T309,U200,W400. Change-Id: Ie92971f4a009511b72b22eea6dba56c461438d2b Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com> uboot: emmc: setup emmc hs400 debug environment in uboot [1/1] PD#SWPL-1265 Problem: HS400 enviroment is too complexity to debug Solution: setup HS400 environment in uboot Verify: verify on tl1_skt Change-Id: Iddc3ec8bdad496baf5792457d5417fe06ac3ce9b Signed-off-by: Ruixuan Li <ruixuan.li@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com> storage: mmc/nand: support support to read saved ddr parameter [1/1] PD#SWPL-5550 Problem: Implement to the function that can read ddr parameter which saved in reserved area. Solution: provide interface. Verify: tl1-x301 axg-s400 Change-Id: I68a0a83ac435ad6d4a11e01edc290aedae650941 Signed-off-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Qiang Li <qiang.li@amlogic.com> Signed-off-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
* ODROID-N2: g12b: add missing '#include <usb.h>'Dongjin Kim2020-02-101-0/+1
| | | | | Change-Id: I94cb61ba7ad57ab99158f7578703e67050fb9948 Signed-off-by: Dongjin Kim <tobetter@gmail.com>
* ODROID-C4: display: g12a: Add new display modes on HDMI PHYJoy Cho2020-02-103-12/+887
| | | | | | | | | | | | | | | | | | | | | - 1024x600p60hz - 1024x768p60hz - 1280x1024p60hz - 1280x800p60hz - 1360x768p60hz - 1440x900p60hz - 1600x1200p60hz - 1600x900p60hz - 1920x1200p60hz - 2560x1080p60hz - 2560x1440p60hz - 2560x1600p60hz - 480x320p60hz - 640x480p60hz - 800x480p60hz - 800x600p60hz Change-Id: Ib91cc394c88fb4e868dec808b40f9949d72344c0
* ODROID-C4: introduce display auto detection logicJoy Cho2020-02-101-0/+64
| | | | Change-Id: I969bb06881382fc963d8c4a4e8bb875ed2941481
* usb: some udisk amldevread data failed [1/1]he.he2020-02-101-0/+1
| | | | | | | | | | | | | | | | | | | PD#SWPL-5292 Problem: g12b-revB, some u disk amldevread test failed Solution: Changing the register 0x54 to 0x2a, enabled the hs rx idle noise filter, and the abnormal u-disk has no problem in the amldevread test. Verify: g12b revB, PASS Test: pass Change-Id: I3ddf566ad53ee3bb7ac42de8f8411a44147163ba Signed-off-by: he.he <he.he@amlogic.com>
* usb: check SoC sm1 [1/1]Yue Wang2020-02-102-17/+76
| | | | | | | | | | | | | | | | PD#SWPL-5385 Problem: Need to check Soc family id to distinguish SM1. Solution: Check Soc family set rev_flag for 1. Verify: SM1 Change-Id: Ia78cb91dc3a51c03a976690d3b3ffb03eb13379f Signed-off-by: Yue Wang <yue.wang@amlogic.com>
* uboot-usb: set pll registers of revB usb [2/2]he.he2020-02-101-18/+19
| | | | | | | | | | | | | | | | | | | PD#SWPL-4941 Problem: revB: EL27,28,29,31 failed in the el compliance test in kernel, and have been solved by modifing some usb pll parameters. Solution: The usb pll registers in uboot need keep consistent with kernel. Verify: verify on revB Test: Pass Change-Id: I953538bc47fc1b3e2f4f6c85f7eb335ad112f573 Signed-off-by: he.he <he.he@amlogic.com>
* uboot-usb: check SoC rev [2/2]he.he2020-02-101-1/+29
| | | | | | | | | | | | | | | | | | | PD#SWPL-4582 Problem: Need to check Soc rev to distinguish G12B revB. Solution: Check Soc rev set rev_flag for 0(revA) and 1(revB/revC). Verify: W400 Test: Pass Change-Id: Ic9b6c964d0e90fc7a5ef25ddaf8e001f7ccc3fd2 Signed-off-by: he.he <he.he@amlogic.com> Signed-off-by: qi duan <qi.duan@amlogic.com>
* ODROID-C3/N2: scp_task: reset CEC when transmit error happensDongjin Kim2019-06-222-0/+2
| | | | | Change-Id: Ifdb0d98f37597ab0794b88e28c00fcae930a9656 Signed-off-by: Dongjin Kim <tobetter@gmail.com>
* BACKPORT: CE: fix cec_node_init for all arm8 cpusPortisch2019-06-227-0/+7
| | | | Change-Id: Ic03f1abd2b91476f9fb26e02fc56c5edfc83e75c
* BACKPORT: CE: g12b/CEC: Reset cec if there is no finish flag on TXRay2019-06-201-0/+8
| | | | Change-Id: I132199b0ad54837788e95e8b97d84e7e24cb214c
* BACKPORT: CE: Use AO_CECB_INTR_STAT for IRQ checks.Portisch2019-06-201-23/+19
| | | | | | | This is a workaround because the irq is never triggered in WAKEUP_SRC_IRQ_ADDR_BASE. Change-Id: Ibcbba4575bb558c77f30d02d5f06787b5a34c98c
* BACKPORT: CE: CEC: only wake when TV is destinationRay2019-06-202-26/+10
| | | | Change-Id: I92d922ff4768c4b002deaf5ec604abb2a8bbdd27
* BACKPORT: CE: CEC: wakeup on routing changeRay2019-06-205-7/+85
| | | | Change-Id: I6f07550c1ad1bc4698c6d9fbae54ddded548d117
* BACKPORT: CE: CEC: Change to default CEC_RECORDING_DEVICERay2019-06-206-18/+18
| | | | Change-Id: Id1c026773c832257ff0357a2b8bb827476c3f522
* BACKPORT: CE: split CEC wakeup maskRay2019-06-2010-5/+20
| | | | Change-Id: I64abd590c3c9dbe2325786dcfce603f2c8b56a95
* BACKPORT: CE: use kernel CEC address in u-bootPortisch2019-06-204-2/+56
| | | | Change-Id: If213187b2d8b1e109ea63d2a1c1af9ba0dc4424c
* BACKPORT: CE: gpio_key: ignore gpio wakeup when gpio is not setPortisch2019-06-201-0/+3
| | | | Change-Id: Ib49e26173923c86a2f87834e93162664da325158
* ODROID-C3/N2: arch/arm: fix to COMMAND_LINE_SIZE as 2048 bytes for ARM64Dongjin Kim2019-06-171-0/+4
| | | | | | | | This patch is to set the COMMAND_LINE_SIZE same as the kernel one which is defined in 'arch/arm64/include/uapi/asm/setup.h'. Change-Id: I4a23441957632f0601b310273ffe8c7a6ce09d9b Signed-off-by: Dongjin Kim <tobetter@gmail.com>
* suspend: modify stack size for tm2 [1/2]Hong Guo2019-05-162-4/+14
| | | | | | | | | | | | | | | | PD#SWPL-7291 Problem: modify stack size for tm2 Solution: modify stack size for tm2 Verify: test pass on t962e2_ab319 Change-Id: Id761c1945fc3cc433d93d92e9ff659469d0066c3 Signed-off-by: Hong Guo <hong.guo@amlogic.com>
* virtual_counter: fix abnormal CNTVCT value for ARMv8 AARCH32 mode [1/4]Jiamin Ma2019-05-161-1/+1
| | | | | | | | | | | | | | | | | | PD#SWPL-7033 Problem: The start counter value of the virtual counter value for global counter in ARMv8 AARCH32 mode is a quite large one. aka. 0x926A55C29C88EBF3, which is abnormal Solution: Clear virtual offset(cntvoff_el2) in suitable places Verify: Ampere && R311 Change-Id: I8ba3d5f76c21b9066ee64b568d367127ab616405 Signed-off-by: Jiamin Ma <jiamin.ma@amlogic.com>
* TM2: enable 3 user taskes [2/2]Qiufang Dai2019-05-167-305/+3199
| | | | | | | | | | | | | | | | PD#SWPL-5624 Problem: Need enable 3 user taskes Solution: Porting 301 to riscv Verify: tm2_t962e2_ab319 Change-Id: I9d4223096090db7601365de95a6a84444b84c390 Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
* tm2: add mailbox interface for dsp sec reg ops [2/3]zhiqiang liang2019-05-162-0/+13
| | | | | | | | | | | | | | | | PD#SWPL-6583 Problem: tm2 dsp bring up Solution: add the mbox interface Verify: AB311 Change-Id: I80a97acd28de2c527150b5e2bec9fe3b91fac4df Signed-off-by: zhiqiang liang <zhiqiang.liang@amlogic.com>
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